JP6031253B2 - ハイブリッドmosfetデバイスの製造方法およびそれにより得られるハイブリッドmosfet - Google Patents
ハイブリッドmosfetデバイスの製造方法およびそれにより得られるハイブリッドmosfet Download PDFInfo
- Publication number
- JP6031253B2 JP6031253B2 JP2012105801A JP2012105801A JP6031253B2 JP 6031253 B2 JP6031253 B2 JP 6031253B2 JP 2012105801 A JP2012105801 A JP 2012105801A JP 2012105801 A JP2012105801 A JP 2012105801A JP 6031253 B2 JP6031253 B2 JP 6031253B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- iii
- region
- mosfet
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims description 36
- 238000004519 manufacturing process Methods 0.000 title claims description 20
- 239000000758 substrate Substances 0.000 claims description 59
- 239000012212 insulator Substances 0.000 claims description 49
- 239000000463 material Substances 0.000 claims description 46
- 239000004065 semiconductor Substances 0.000 claims description 46
- 150000001875 compounds Chemical class 0.000 claims description 16
- 238000002955 isolation Methods 0.000 claims description 8
- 229910052710 silicon Inorganic materials 0.000 claims description 8
- 239000010703 silicon Substances 0.000 claims description 8
- 229910052732 germanium Inorganic materials 0.000 claims description 6
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 2
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 2
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 2
- 230000002093 peripheral effect Effects 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 230000010354 integration Effects 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 2
- 229910000673 Indium arsenide Inorganic materials 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 2
- 239000004615 ingredient Substances 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- 229910005883 NiSi Inorganic materials 0.000 description 1
- 238000007792 addition Methods 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000008094 contradictory effect Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000002123 temporal effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/8258—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using a combination of technologies covered by H01L21/8206, H01L21/8213, H01L21/822, H01L21/8252, H01L21/8254 or H01L21/8256
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28255—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor belonging to Group IV and not being elemental silicon, e.g. Ge, SiGe, SiGeC
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66651—Lateral single gate silicon transistors with a single crystalline channel formed on the silicon substrate after insulating device isolation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Description
少なくとも第1領域に、第1チャネル材料として機能するのに適したIV族半導体材料の半導体層を含む第1基板を提供する工程と、
露出した絶縁体層に覆われて、これと接続するIII−V層を含む第2基板であって、III−V層は、第2チャネル材料として機能するのに適したIII−V化合物を含む第2基板を供給する工程と、
第1基板を第2基板にダイレクト基板ボンディングして、III−Vオン絶縁体スタックを第1基板上に形成する工程であって、III−Vオン絶縁体スタックは、第1領域と第2領域の上で第1基板を覆いこれと接続する絶縁体層と、第1領域と第2領域の上で絶縁体層を覆いこれと接続するIII−V層とを含む工程と、
第1領域のIII−V層と絶縁体層とを選択的に除去して、第1領域で半導体層を露出させる工程と、
第1領域で露出した半導体層の上に、第1MOSFETの第1ゲートスタックを形成する工程と、
第2領域で、III−V層の上に第2MOSFETの第2ゲートスタックを形成する工程と、を含む。
Claims (14)
- 第1チャネル材料を有する第1MOSFETと、第2チャネル材料を有する第2MOSFETとを含むハイブリッドMOSFETデバイスの製造方法であって、
少なくとも第1領域(I、I’)に、第1チャネル材料として機能するのに適したIV族半導体材料の半導体層(107、108、207、208)を含む第1基板(A)を提供する工程と、
露出した絶縁体層(104)に覆われて、これと接続するIII−V層(103)を含む第2基板(B)であって、III−V層は、第2チャネル材料として機能するのに適したIII−V化合物を含む第2基板を供給する工程と、
第1基板(A)を第2基板(B)にダイレクト基板ボンディングして、III−Vオン絶縁体スタック(C)を第1基板(A)上に形成する工程であって、III−Vオン絶縁体スタック(C)は、第1領域(I、I’)と第2領域(II)の上で第1基板(A)を覆いこれと接続する絶縁体層(104、204、304)と、第1領域(I、I’)と第2領域(II)の上で絶縁体層(104、204、304)を覆いこれと接続するIII−V層(103、203、303)とを含む工程と、
第1領域(I、I’)のIII−V層(103、203、303)と絶縁体層(104、204、304)とを選択的に除去して、第1領域(I、I’)で半導体層(107、108、207、208)を露出させる工程と、
第1領域(I、I’)で露出した半導体層の上に、第1MOSFETの第1ゲートスタック(109、109’)を形成する工程と、
第2領域(II)で、III−V層の上に第2MOSFETの第2ゲートスタック(109”)を形成する工程と、を含み、
シャロウトレンチ分離パターン(105、105’)は、III−Vオン絶縁体スタック(C)がその上に形成される前に第1基板中に形成され、第2領域(II)から第1領域(I、I’)を絶縁する方法。 - 第1ゲートスタックと第2ゲートスタックとは同時に形成される請求項1に記載の方法。
- 第2基板(B)は、最初に、半導体基板(100’)、半導体基板の上の段階的なバッファ層(102)、段階的なバッファ層の上のIII−V層(103、203、303)、およびIII−V層(103、203.303)の上の絶縁体層(104、204、304)を含み、
半導体基板(100’)および段階的なバッファ層(102)は、ダイレクト基板ボンディングの後に、III−V層を露出させるために除去される請求項1または2に記載の方法。 - IV族半導体材料(107、108)は、シリコンおよび/またはゲルマニウムを含む請求項1〜3のいずれかに記載の方法。
- 第1領域(I、I’)中のIII−Vオン絶縁体スタック(C)を除去した後に、第1領域(I、I’)中の露出した半導体層の上に第2のIV族半導体材料(207、208)が続いて成長され、第2のIV族半導体材料は、第1チャネル材料として機能するのに適した請求項1〜4のいずれかに記載の方法。
- 第2のIV族半導体材料(207、208)は、シリコンおよび/またはゲルマニウムを含む請求項1〜5のいずれかに記載の方法。
- 第1MOSFETはp−MOSFETで、第2MOSFETはn−MOSFETである請求項1〜6のいずれかに記載の方法。
- 更に、第2MOSFET(II)のソース領域およびドレイン領域に対応する領域で、III−V絶縁体スタック(C)を除去し、半導体基板(300)中にリセスを形成する工程と、続いて第2MOSFETのソース(301)およびドレイン(301’)の領域のそれぞれにドープされたIV族半導体材料の選択エピタキシャル再成長を行い、その後に、第1MOSFETと第2MOSFETの上に同時にソースコンタクトとドレインコンタクトを形成する工程とを含む請求項1〜7のいずれかに記載の方法。
- 段階的なバッファ層(102)のサブレイヤは、エッチストップ層として機能する請求項1〜8のいずれかに記載の方法。
- 絶縁体層(104)は、誘電体ボンディング層として機能するのに適した酸化物を含む請求項1〜9のいずれかに記載の方法。
- 絶縁体層(104)は、シリコン酸化物またはアルミニウム酸化物を含む請求項1〜10のいずれかに記載の方法。
- III−Vオン絶縁体スタック(C)は15nmより薄い膜厚を有する請求項1〜11のいずれかに記載の方法。
- 第1チャネル材料を有する第1MOSFETと、第2チャネル材料を有する第2MOSFETとを含むハイブリッドMOSFETデバイスであって、
少なくとも第1領域(I、I’)に、第1チャネル材料として機能するのに適した、IV族半導体材料の露出した半導体層(107、108、207、208)を含む第1基板(A)と、
第1基板(A)に接続されたIII−Vオン絶縁体スタック(C)であって、III−Vオン絶縁体スタック(C)は、第2領域(II)の上で第1基板(A)を覆いこれと接続する絶縁体層(104、204、304)と、第2領域(II)の上で絶縁体層(104、204、304)を覆いこれと接続するIII−V層(103、203、303)とを含み、III−V層は第2チャネル材料として機能するのに適したIII−V化合物を含む、III−Vオン絶縁体スタック(C)と、
第1領域(I、I’)で露出した半導体層の上に直接形成され、絶縁体層とIII−V層は存在しない第1MOSFETの第1ゲートスタック(109、109’)と、
第2領域(II)でIII−V層の上に形成された第2MOSFETの第2ゲートスタック(109”)と、を含み、
シャロウトレンチ分離パターン(105、105’)は、第1基板中に形成され、第2領域(II)から第1領域(I、I’)を絶縁し、
絶縁体層とIII−V層は、シャロウトレンチ分離パターン(105、105’)の上にも形成されているハイブリッドMOSFETデバイス。 - III−Vオン絶縁体スタック(C)は、15nmより薄い膜厚を有する請求項13に記載のハイブリッドMOSFETデバイス。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US201161482129P | 2011-05-03 | 2011-05-03 | |
US61/482,129 | 2011-05-03 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2012248830A JP2012248830A (ja) | 2012-12-13 |
JP6031253B2 true JP6031253B2 (ja) | 2016-11-24 |
Family
ID=46087497
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2012105801A Active JP6031253B2 (ja) | 2011-05-03 | 2012-05-07 | ハイブリッドmosfetデバイスの製造方法およびそれにより得られるハイブリッドmosfet |
Country Status (3)
Country | Link |
---|---|
US (1) | US8912055B2 (ja) |
EP (1) | EP2521168B8 (ja) |
JP (1) | JP6031253B2 (ja) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9396948B2 (en) * | 2013-05-03 | 2016-07-19 | Texas Instruments Incorporated | Layer transfer of silicon onto III-nitride material for heterogenous integration |
EP2849219A1 (en) * | 2013-09-11 | 2015-03-18 | IMEC vzw | Method for manufacturing transistors and associated substrate |
US9257407B2 (en) | 2013-10-28 | 2016-02-09 | Qualcomm Incorporated | Heterogeneous channel material integration into wafer |
US10014374B2 (en) | 2013-12-18 | 2018-07-03 | Intel Corporation | Planar heterogeneous device |
Family Cites Families (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0824162B2 (ja) * | 1989-07-10 | 1996-03-06 | 日本電装株式会社 | 半導体装置およびその製造方法 |
US5064781A (en) | 1990-08-31 | 1991-11-12 | Motorola, Inc. | Method of fabricating integrated silicon and non-silicon semiconductor devices |
JP2605597B2 (ja) * | 1993-09-09 | 1997-04-30 | 日本電気株式会社 | 半導体装置の製造方法 |
US5894152A (en) | 1997-06-18 | 1999-04-13 | International Business Machines Corporation | SOI/bulk hybrid substrate and method of forming the same |
US6563143B2 (en) | 1999-07-29 | 2003-05-13 | Stmicroelectronics, Inc. | CMOS circuit of GaAs/Ge on Si substrate |
US7329923B2 (en) * | 2003-06-17 | 2008-02-12 | International Business Machines Corporation | High-performance CMOS devices on hybrid crystal oriented substrates |
US7034362B2 (en) * | 2003-10-17 | 2006-04-25 | International Business Machines Corporation | Double silicon-on-insulator (SOI) metal oxide semiconductor field effect transistor (MOSFET) structures |
US7208815B2 (en) | 2004-05-28 | 2007-04-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | CMOS logic gate fabricated on hybrid crystal orientations and method of forming thereof |
US20050275018A1 (en) * | 2004-06-10 | 2005-12-15 | Suresh Venkatesan | Semiconductor device with multiple semiconductor layers |
US7560322B2 (en) * | 2004-10-27 | 2009-07-14 | Northrop Grumman Systems Corporation | Method of making a semiconductor structure for high power semiconductor devices |
US7282425B2 (en) | 2005-01-31 | 2007-10-16 | International Business Machines Corporation | Structure and method of integrating compound and elemental semiconductors for high-performance CMOS |
US7626246B2 (en) | 2005-07-26 | 2009-12-01 | Amberwave Systems Corporation | Solutions for integrated circuit integration of alternative active area materials |
US7385257B2 (en) | 2006-04-26 | 2008-06-10 | International Business Machines Corporation | Hybrid orientation SOI substrates, and method for forming the same |
US7749829B2 (en) * | 2007-05-01 | 2010-07-06 | Freescale Semiconductor, Inc. | Step height reduction between SOI and EPI for DSO and BOS integration |
US7790528B2 (en) | 2007-05-01 | 2010-09-07 | Freescale Semiconductor, Inc. | Dual substrate orientation or bulk on SOI integrations using oxidation for silicon epitaxy spacer formation |
KR101461206B1 (ko) | 2007-05-17 | 2014-11-12 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | 반도체장치 및 그의 제조방법 |
FR2917235B1 (fr) | 2007-06-06 | 2010-09-03 | Soitec Silicon On Insulator | Procede de realisation de composants hybrides. |
JP2009212413A (ja) * | 2008-03-06 | 2009-09-17 | Renesas Technology Corp | 半導体装置及び半導体装置の製造方法 |
EP2254148B1 (en) * | 2009-05-18 | 2011-11-30 | S.O.I.Tec Silicon on Insulator Technologies | Fabrication process of a hybrid semiconductor substrate |
-
2012
- 2012-05-02 US US13/462,694 patent/US8912055B2/en active Active
- 2012-05-03 EP EP12166646.5A patent/EP2521168B8/en active Active
- 2012-05-07 JP JP2012105801A patent/JP6031253B2/ja active Active
Also Published As
Publication number | Publication date |
---|---|
EP2521168B8 (en) | 2018-01-10 |
EP2521168A1 (en) | 2012-11-07 |
JP2012248830A (ja) | 2012-12-13 |
US8912055B2 (en) | 2014-12-16 |
EP2521168B1 (en) | 2017-11-29 |
US20120280326A1 (en) | 2012-11-08 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US8697523B2 (en) | Integration of SMT in replacement gate FINFET process flow | |
US7298009B2 (en) | Semiconductor method and device with mixed orientation substrate | |
JP4243671B2 (ja) | 集積回路構造及び形成方法 | |
JP5464850B2 (ja) | 改良されたキャリア移動度を有するマルチゲート半導体デバイスの製造方法 | |
US6995456B2 (en) | High-performance CMOS SOI devices on hybrid crystal-oriented substrates | |
US7034362B2 (en) | Double silicon-on-insulator (SOI) metal oxide semiconductor field effect transistor (MOSFET) structures | |
US8969155B2 (en) | Fin structure with varying isolation thickness | |
US12027607B2 (en) | Methods for GAA I/O formation by selective epi regrowth | |
CN104350597A (zh) | 具有混合沟道材料的场效应晶体管 | |
JP2009200471A5 (ja) | ||
JP2006527915A (ja) | ハイブリッド結晶配向基板上の高性能cmossoiデバイス | |
US9105746B2 (en) | Method for manufacturing a field effect transistor of a non-planar type | |
US10283418B2 (en) | Method of forming silicon germanium and silicon fins on oxide from bulk wafer | |
WO2012155830A1 (zh) | 锗和iii-v混合共平面的绝缘体上硅(s0i)半导体结构及其制备方法 | |
US8530355B2 (en) | Mixed orientation semiconductor device and method | |
JP6031253B2 (ja) | ハイブリッドmosfetデバイスの製造方法およびそれにより得られるハイブリッドmosfet | |
US9754969B2 (en) | Dual-material mandrel for epitaxial crystal growth on silicon | |
US10680065B2 (en) | Field-effect transistors with a grown silicon-germanium channel | |
US9356025B2 (en) | Enhancing MOSFET performance with corner stresses of STI | |
WO2012003611A1 (zh) | 半导体器件及其制作方法 | |
KR20220107969A (ko) | 3d 수평 나노시트 디바이스 성능 향상 방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20150403 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20160225 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20160301 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20160601 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20160621 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20160809 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20161018 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20161024 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 6031253 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |