201021132 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種半導體結構的製造方法，特別 係接面場效電晶體的製造方法。 【先前技術】 φ 接面場效電晶體（JFET)多用作類比開關及訊號放大 器，特別是低雜訊的放大器。 場效電晶體主要藉由控制訊號（閘極的電壓）造成載 體通道（channel)附近電場改變，使通道特性發生變化， 導致電流（源極與汲極之間）改變。故場效電晶體可以用作 電壓控制的可變電阻或電壓控制電流源(VCCS)等。其中 接面場效電晶體（JFET)之工作原理主要係利用閘極和源 極\汲極間PN接面間的空乏區寬度是逆向偏壓的函數， ❿ 以藉由改變空乏區寬度來改變通道寬度。 在接面場效電晶體中，當施加於閘極，且造成PN接 面的空乏區的電壓變大時，通道的厚度會變小。而當閘 極電壓大到一臨界值時，空乏區會寬到使通道完全消 失，這時稱此通道被夾止（pinch off)，電阻值變成很大， 且這時的閘極電壓值稱為夾止電壓（pinch-off voltage)。 本發明即是有關於調整夾止電壓之製程技術。 97012/0516-A41820-TW/fmal 201021132 【發明内容】201021132 IX. Description of the Invention: TECHNICAL FIELD OF THE INVENTION The present invention relates to a method of fabricating a semiconductor structure, and more particularly to a method of fabricating a field effect transistor. [Prior Art] φ junction field effect transistors (JFETs) are mostly used as analog switches and signal amplifiers, especially for low noise amplifiers. The field effect transistor mainly changes the electric field near the carrier channel by controlling the signal (the voltage of the gate), causing the channel characteristics to change, resulting in a change in current (between the source and the drain). The field effect transistor can be used as a voltage controlled variable resistor or voltage controlled current source (VCCS). The working principle of the junction field effect transistor (JFET) is mainly to use the width of the depletion region between the gate and the source/drain PN junction as a function of the reverse bias, ❿ to change by changing the width of the depletion region. Channel width. In the junction field effect transistor, when applied to the gate and the voltage of the depletion region causing the PN junction becomes large, the thickness of the channel becomes small. When the gate voltage is as large as a critical value, the depletion region will be wide enough to completely disappear the channel. At this time, the channel is called pinch off, the resistance value becomes large, and the gate voltage value at this time is called a clip. Pinch-off voltage. The present invention is a process technique for adjusting the clamping voltage. 97012/0516-A41820-TW/fmal 201021132 [Summary content]
本發明提供一種半導體結構的製造方法，包括下列 步驟：提供一第一型基底；於該第一型基底中形成數個 第一型井區；使用一罩幕進行一摻雜製程，以於該第一 型基底中形成數個第二型井區及數個第二型條狀摻雜 區；進行一退火製程使該些第二型條狀摻雜區擴散成一 第二型連續摻雜區，其中該第二型連續摻雜區與該些第 一型井區接觸，且該第二型連續摻雜區的第二型雜質濃 度小於該第二型條狀掺雜區；以及形成一第二型濃摻雜 區於該第二型井區中。 本發明也提供一種半導體結構，包括：一第一型基 底；數個第一型井區，形成於該第一型基底上；數個第 二型井區’形成於該第一型基底上；一第二型連= 區’與該些第—型井區相鄰，且該第二型連續摻雜區的 第-型雜質濃度小於該第二型㈣；以及—第二型源/ 汲極區，形成於該第二型井區上。 【實施方式】 本發明之實施例提供一種半導體結構的製造 ^關各實_之製造方式和使用方式係如下所詳述，並 伴隨圖示加以說明。其中，圖式和說明書中使用伽 的70件編號係表示相同或類似之it件。而在圖式中° 清楚和方便說明起見’有，施狀形狀和厚度或有= 97012/0516-A41820-TW/fmal 201021132 符實際之情形。而以下所描述者係特別針對本發明之裝 置的各項元件或其整合加以說明，然而，值得注意的是， 上述元件並不特別限定於所顯示或描述者，而是可以熟 習此技藝之人士所得知的各種形式，此外，當一層材料 層是位於另一材料層或基底之上時，其可以是直接位於 其表面上或另外插入有其他中介層。 第1圖為本發明一實施例之半導體結構的俯視圖。 第2圖為第1圖之半導體結構沿著虛線AA，部分的剖面 圖。第3圖為第！圖之半導體結構沿著虛線BB，部分的 剖面圖。 第2圖及第3圖顯示，半導體結構包括p型基底1〇〇 P型基底10具有N型井區20與P型井區3〇人及3〇B。 隔離結構50形成於N型井區劝或？型井區3〇A上。再 者’N型源極區21人及\型汲極區21B形成於n型井區 20上。P摻雜區31形成於p型井區3〇A上。第2圖與第 • 3圖的主要差異在於，第2圖中位於兩N型井區之間 的P型基底10上的是P型井區3〇B，而第3圖則是_ 通道區20A’。應注意的是，通道區2〇A，的摻雜質濃 度實質上是小於N型井區20。 再者，請參考第1圖，其顯示半導體結構中，N型井 區20、N型通道區源極區21A、Ns汲極區 ⑽^型井區篇及細及”推雜區^的俯視胃。 第2圖及第3圖中的隔離結構5〇則省略而未顯示於第i 97012/0516-A41820-TW/fmal 201021132 請參考第1圖，在一實施例中，於元件操作時，：^型 源極區21A連接-源極電壓％ (未顯示）且用作源極。N 型汲極區21B連接一汲極電壓ν〇(未顯示）且用作汲極。 此外，P型井區30B連接一閘極電壓¥(?(未顯示）。卩型 井區30B可視為一閘極區。 由於N型通道20A’的摻雜質濃度較淡，因此，在元The present invention provides a method of fabricating a semiconductor structure, comprising the steps of: providing a first type substrate; forming a plurality of first type well regions in the first type substrate; performing a doping process using a mask to Forming a plurality of second type well regions and a plurality of second type strip doped regions in the first type substrate; performing an annealing process to diffuse the second type strip doped regions into a second type continuous doped region, Wherein the second type continuous doped region is in contact with the first type well regions, and the second type continuous doped region has a second type impurity concentration smaller than the second type strip doped region; and forming a second The concentrated doped region is in the second well region. The present invention also provides a semiconductor structure comprising: a first type substrate; a plurality of first type well regions formed on the first type substrate; and a plurality of second type well regions 'formed on the first type substrate; a second type of junction = region 'is adjacent to the first type of well regions, and the second type of continuous doped region has a first type impurity concentration less than the second type (four); and - the second type source / drain a zone formed on the second type of well zone. [Embodiment] Embodiments of the present invention provide a manufacturing method and a usage mode of a semiconductor structure, which are described in detail below, and are illustrated with reference to the drawings. Here, the 70-numbers used in the drawings and the descriptions indicate the same or similar ones. In the figure, ° is clear and convenient for explanation. 'Yes, the shape and thickness of the application are either 97012/0516-A41820-TW/fmal 201021132. While the following description is specifically directed to the various elements of the device of the present invention or its integration, it is noted that the above-described elements are not particularly limited to those shown or described, but may be familiar to those skilled in the art. The various forms are known, and in addition, when a layer of material is placed over another layer or substrate of material, it may be directly on its surface or otherwise interposed with other intervening layers. Figure 1 is a plan view of a semiconductor structure in accordance with one embodiment of the present invention. Figure 2 is a cross-sectional view of a portion of the semiconductor structure of Figure 1 taken along the dashed line AA. Figure 3 is the first! The semiconductor structure of the figure is along a broken line BB, a partial cross-sectional view. 2 and 3 show that the semiconductor structure includes a p-type substrate. The P-type substrate 10 has an N-type well region 20 and a P-type well region 3 〇 and 3 〇 B. Is the isolation structure 50 formed in the N-well area to persuade? The well area is 3〇A. Further, the 'N-type source region 21' and the \-type bungee region 21B are formed on the n-type well region 20. The P doped region 31 is formed on the p-type well region 3A. The main difference between Figure 2 and Figure 3 is that in Figure 2, on the P-type substrate 10 between the two N-type wells, the P-type well area is 3〇B, and the third picture is the _-channel area. 20A'. It should be noted that the doping concentration of the channel region 2A is substantially smaller than the N-well region 20. Furthermore, please refer to FIG. 1 , which shows a semiconductor structure in which an N-type well region 20, an N-type channel region source region 21A, a Ns-drain region (10), a well region, and a fine The isolation structure 5〇 in FIGS. 2 and 3 is omitted and is not shown in the first 97012/0516-A41820-TW/fmal 201021132. Referring to FIG. 1 , in an embodiment, during component operation, The ^ type source region 21A is connected to the source voltage % (not shown) and serves as a source. The N-type drain region 21B is connected to a drain voltage ν 〇 (not shown) and used as a drain. The well region 30B is connected to a gate voltage ¥(? (not shown). The 卩-type well region 30B can be regarded as a gate region. Since the doping concentration of the N-type channel 20A' is relatively light, therefore, the element is
件操作時，於N型通道20A，内形成空乏區的速度更快， 且元件的夾止電壓變小。 第4圖至第9圖顯示第i圖至第3圖中的半導體結 構的製造方法。首先，請參考第4圖，提供一半導體基 底10。在一實施例中，半導體基底1〇可包括絕緣層上有 矽（soi)基底、塊狀矽（Bulk silic〇n)基底、或基底上有矽 磊晶層之形式。半導體基底1〇可以為一第一導電型態， 例如P型或N型。在本例中，半導體基底忉為卩型^底 10 〇 接著’於P型基底10内形成P型井區及細。 在-實施射，可以藉由植入P型雜f以形成p型井區 30A或31P型雜質包括例如,、嫁、銘、姻、或前述 之組合。在-實施例中’P型井區3〇a及遍一 罩幕(未顯示)配合執行—植入 型井區30A及30B的摻雜質濃度相同。吁办珉且 請參考第5圖，形成N型井區 摻雜區20Λ於P型基底1〇内。N 複數個N型條狀 於N型井區20之間。N型條狀摻、狀摻雜區20A是位 夕雜區20A的厚度w可 97012/0516-A41820-TW/final 201021132 大於0.5μπι。兩鄰近的N型條狀摻雜區2〇A其彼此門、 相隔距離S可小於ΙΟμπι。於一較佳實施例中，厚度％ 與相隔距離S的大小實質上是幾乎相同的。於其他^施 例中，厚度w與相隔距離s的大小是不同的。可以藉L 植入Ν型雜質以形成Ν型井區20及Ν型條狀摻雜區 2〇Α°Ν型雜質包括例如磷、砷、氮、銻、或前述之組合。 於一實施例中，Ν型井區20及Ν型條狀摻雜區2〇Α^摻 雜濃度相同。在一較佳實施例中’ Ν型井區2〇及Ν型條 馨 狀摻雜區20Α是藉由一圖案化罩幕（未顯示）配合執行」 植入步驟同時形成，而不需額外的光罩或製程。 請參考第6圖’於Ρ型基底1〇上形成隔離結構5〇 以定義主動區。第6圖中所顯示之隔離結構5〇係利用局 部氧化隔離技術（local oxidation of silicon，LOCOS)所形 成場介電結構為例，但並不以此為限，其他各種隔離結 構例如淺溝槽隔離結構亦可採用。 φ 請參考第7圖’於P型井區30A内形成ρ型摻雜區 31。1>型摻雜區31係形成於P型井區30A的上部内。在 一實施例中’可以藉由植入P型雜質以形成ρ型摻雜區 31，摻雜質濃度可介於約1E15 atom/cm2至約1E16 atom/cm2。P型雜質包括例如硼、鎵、鋁、銦、或前述之 組合。在一實施例中，P型摻雜區31是藉由一圖案化罩 幕（未顯示）配合執行一植入步驟形成。During the operation of the device, the speed of forming the depletion region in the N-type channel 20A is faster, and the clamping voltage of the element becomes smaller. Figs. 4 to 9 show a method of manufacturing the semiconductor structure in the i-th to third figures. First, please refer to Fig. 4 to provide a semiconductor substrate 10. In one embodiment, the semiconductor substrate 1 may include a so-called (Soi) substrate, a bulk silicon germanium substrate, or a germanium epitaxial layer on the insulating layer. The semiconductor substrate 1 can be of a first conductivity type, such as a P-type or an N-type. In this example, the semiconductor substrate is a 卩-type substrate 10 〇 Next, a P-type well region and a thin portion are formed in the P-type substrate 10. In-spraying, a P-type well region 30A or 31P-type impurity can be formed by implanting a P-type impurity f including, for example, marry, marry, marry, or a combination of the foregoing. In the embodiment, the 'P-type well region 3'a and the over-the-surface mask (not shown) are cooperatively performed - the doping concentrations of the implanted well regions 30A and 30B are the same. Please refer to Figure 5 to form an N-type well region doped region 20 within the P-type substrate 1〇. N A plurality of N-shaped strips are formed between the N-type well regions 20. The N-type strip-like doped region 20A has a thickness w of the terracotta region 20A of 97012/0516-A41820-TW/final 201021132 of more than 0.5 μm. The two adjacent N-type strip-shaped doping regions 2A can be separated from each other by a gate S, which can be smaller than ΙΟμπι. In a preferred embodiment, the thickness % and the distance S are substantially the same in size. In other embodiments, the thickness w is different from the distance s. The yttrium-type impurity may be implanted by L to form the 井-type well region 20 and the Ν-type strip-shaped doped region. The 〇Α-type impurity includes, for example, phosphorus, arsenic, nitrogen, antimony, or a combination thereof. In one embodiment, the 井-type well region 20 and the 条-type strip-shaped doped region have the same doping concentration. In a preferred embodiment, the 'Ν-well zone 2〇 and the 条-shaped strip-shaped doped region 20Α are simultaneously formed by a patterned mask (not shown). The implantation step is simultaneously formed without additional Mask or process. Please refer to Fig. 6' to form an isolation structure 5 on the substrate 1 to define the active region. The isolation structure 5 shown in FIG. 6 is exemplified by a field dielectric structure formed by local oxidation of silicon (LOCOS), but is not limited thereto, and various other isolation structures such as shallow trenches. Isolation structures can also be used. φ Please refer to Fig. 7' to form a p-type doped region 31 in the P-type well region 30A. The 1>-type doped region 31 is formed in the upper portion of the P-type well region 30A. In one embodiment, the p-type impurity can be formed by implanting a P-type impurity, and the dopant concentration can be from about 1E15 atom/cm2 to about 1E16 atom/cm2. The P-type impurities include, for example, boron, gallium, aluminum, indium, or a combination thereof. In one embodiment, the P-doped region 31 is formed by a patterned mask (not shown) that cooperates to perform an implantation step.
請參考第8圖，於兩被隔開的N型井區20内分別 形成N型源極區21A及N型汲極區21B〇N型源極區21A 97012/0516-A41820-TW/final 9 201021132 及N型汲極區21B係形成型井區2〇的上部内。可 以藉由植入N型雜質以形成N型源極區21人或\型汲極 區21B，摻雜質濃度可介於約1E15 at〇m/cm2至約mb atom/cm2。N型雜質包括例如磷、砷、氮、銻、或前述之 組合。於-較佳實施射，N型源極區21A & n型没極 區21B是藉由一圖案化罩幕（未顯示）配合執行__植人步 驟同時形成。Referring to FIG. 8, an N-type source region 21A and an N-type drain region 21B〇N-type source region 21A 97012/0516-A41820-TW/final 9 are respectively formed in the two separated N-type well regions 20. The 201021132 and N-type bungee zone 21B are formed in the upper part of the 2井 well. The dopant concentration may be from about 1E15 at 〇m/cm 2 to about mb atom/cm 2 by implanting an N-type impurity to form an N-type source region 21 human or a K-type drain region 21B. The N-type impurities include, for example, phosphorus, arsenic, nitrogen, antimony, or a combination of the foregoing. Preferably, the N-type source region 21A & n-type non-polar region 21B is simultaneously formed by a patterned mask (not shown).
在本發明之-實施例中，較佳可於上述步驟完成後， 再進行一退火步驟’以使複數個N型條狀摻雜區2〇A的摻 雜質沿著橫向擴散(lateral diffused)，且互相連接以形成一 連續相的（或淡化的）N型井區，例如第9圖中的N型通 道區20A’。上述退火擴散步驟並不限定於上述所有元件形 成後進行，其亦可以在N型井區20及N型條狀摻雜區2〇A 形成後’及進行下個步驟之前進行。然而，在其他實施例 中，退火擴散步驟可在任合適當的時機進行。 應✓主意的是’在進行退火步驟以使N型條狀摻雜區 20A的摻雜質往橫向擴散的過程中，N型條狀摻雜區2〇a 的N型摻雜質濃度會逐漸變小。因此，最終所形成的N 型通道區20A’其摻雜質濃度會被淡化至少小於N型井區 20的濃度。在一實施例中’淡化的]s[型通道區20A，的雜 質濃度可介於 1E12 atom/cm2 至約 1E15 atom/cm2。In the embodiment of the present invention, preferably after the above steps are completed, an annealing step is performed to make the doping of the plurality of N-type strip doping regions 2〇A laterally diffused. And interconnected to form a continuous phase (or faded) N-type well region, such as N-type channel region 20A' in Figure 9. The annealing diffusion step is not limited to the formation of all of the above elements, and may be performed after the N-type well region 20 and the N-type strip-shaped doping region 2A are formed and before the next step. However, in other embodiments, the annealing diffusion step can be performed at any suitable time. It should be noted that 'the N-type dopant concentration of the N-type strip-shaped doped region 2〇a gradually increases during the annealing step to diffuse the doping of the N-type strip doping region 20A laterally. Become smaller. Therefore, the dopant concentration of the finally formed N-type channel region 20A' is diluted to be at least less than the concentration of the N-type well region 20. In one embodiment, the 'faded" channel region 20A may have a dopant concentration of from 1E12 atom/cm2 to about 1E15 atom/cm2.
本發明之實施例所揭露之半導體結構的方法中，為使 位於P型井區之間的N型通道的摻雜質濃度較小，是利 用使用一罩幕進行一摻雜製程，於基底内同時形成一 N 97012/0516-A41820-TW/fmal 201021132 型井區及減個N㈣狀軸區2GA，接著再崎退火（執 驅入(thenna】 drive-in))製程使上述N型條狀摻雜區2〇: 擴散成一連續的（或淡化的）N型通道2〇A，，因此不需要 額外的光罩或製程’以降低製程成本。此外，N型通道的 摻雜質滚度的大小可依元件所需的電性，例如夾止電壓 (pinch-off voltage)，利用將N型條狀摻雜區的結構或摻雜 質濃度以及製程上的調變，以作適當的調整。 此外，由於N型通道的摻雜質濃度較淡，因此，在元 件操作時，於N型通道内形成空乏區的速度更快，且元件 的夾止電壓變小。 以上之實施例僅用以本發明之範例，舉例來說，當討 論N通道接面場效電晶體(JFET)之實施例時，另一實施例 可以疋P通道接面場效電晶體。雖然本發明已以較佳實施 例揭露如上’然其並非用以限定本發明，任何熟悉此項技 藝者’在不脫離本發明之精神和範圍内，當可做些許更動 與潤飾’因此本發明之保護範圍當視後附之申請專利範圍 所界定者為準。 【圖式簡單說明】 第1圖為本發明一實施例之半導體結構的俯視圖。 第2圖為第1圖之半導體結構沿著虛線aa’部分的刹 面圖。 第3圖為第1圖之半導體結構沿著虛線bb，部分的剖 面圖。 97〇l2/〇516-A41820-TW/fmal 11 201021132 第4圖至第9圖顯示本發明一實施例之半導體的結 構製造方法。 【主要元件符號說明】 10〜P型基底；20〜N型井區；20A〜N型條狀掺雜區； 20A’〜N型通道區；21A〜N型源極區；21B~N型汲極區； 30A〜P型井區；30B〜P型井區；31〜P型摻雜區；50~隔離 結構。In the method for fabricating a semiconductor structure according to an embodiment of the present invention, in order to make the doping concentration of the N-type channel located between the P-type well regions small, a doping process using a mask is performed in the substrate. At the same time, a N 97012/0516-A41820-TW/fmal 201021132 type well area and a N (four) axis area 2GA are formed, followed by a re-annealing (thenna) drive-in process to make the above-mentioned N-type strip-like doping Miscellaneous Zone 2: Diffusion into a continuous (or desalinated) N-type channel 2〇A, so no additional mask or process is required to reduce process costs. In addition, the doping quality of the N-type channel can be determined according to the required electrical properties of the component, such as a pinch-off voltage, by utilizing the structure or doping concentration of the N-type strip doping region and Modulations in the process to make appropriate adjustments. In addition, since the doping concentration of the N-type channel is relatively low, the formation of the depletion region in the N-type channel is faster at the time of component operation, and the clamping voltage of the element becomes smaller. The above embodiments are merely used in the examples of the present invention. For example, when discussing an embodiment of an N-channel junction field effect transistor (JFET), another embodiment may be a P-channel junction field effect transistor. Although the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and any one skilled in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a plan view showing a semiconductor structure according to an embodiment of the present invention. Fig. 2 is a view of the semiconductor structure of Fig. 1 taken along the dashed line aa'. Fig. 3 is a cross-sectional view showing a portion of the semiconductor structure of Fig. 1 taken along the broken line bb. 97〇l2/〇516-A41820-TW/fmal 11 201021132 FIGS. 4 to 9 show a method of fabricating a structure of a semiconductor according to an embodiment of the present invention. [Main component symbol description] 10~P type substrate; 20~N type well area; 20A~N type strip doped area; 20A'~N type channel area; 21A~N type source area; 21B~N type 汲Polar zone; 30A~P type well zone; 30B~P type well zone; 31~P type doped zone; 50~ isolation structure.
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