TW201830608A - 晶片封裝結構及其製造方法 - Google Patents
晶片封裝結構及其製造方法 Download PDFInfo
- Publication number
- TW201830608A TW201830608A TW106133054A TW106133054A TW201830608A TW 201830608 A TW201830608 A TW 201830608A TW 106133054 A TW106133054 A TW 106133054A TW 106133054 A TW106133054 A TW 106133054A TW 201830608 A TW201830608 A TW 201830608A
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- Prior art keywords
- metal layer
- patterned metal
- chip package
- sealing body
- substrate
- Prior art date
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- 238000004519 manufacturing process Methods 0.000 title claims description 15
- 239000002184 metal Substances 0.000 claims abstract description 59
- 229910052751 metal Inorganic materials 0.000 claims abstract description 59
- 239000000758 substrate Substances 0.000 claims abstract description 44
- 239000010410 layer Substances 0.000 claims description 69
- 238000007789 sealing Methods 0.000 claims description 41
- 239000012790 adhesive layer Substances 0.000 claims description 24
- 238000004806 packaging method and process Methods 0.000 claims description 17
- 238000000034 method Methods 0.000 claims description 16
- 230000002093 peripheral effect Effects 0.000 claims description 6
- 229910000679 solder Inorganic materials 0.000 abstract description 20
- 239000008393 encapsulating agent Substances 0.000 abstract 5
- 238000010586 diagram Methods 0.000 description 14
- 238000005516 engineering process Methods 0.000 description 3
- 238000010295 mobile communication Methods 0.000 description 3
- 239000004642 Polyimide Substances 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 230000001788 irregular Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
Classifications
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Abstract
一種晶片封裝結構,其包括基板、晶片、密封體、多個焊球以及圖案化金屬層。基板具有彼此相對的第一表面以及第二表面。晶片配置於第一表面上且電性連接至基板。密封體密封晶片且覆蓋於第一表面。焊球位於第二表面上且與基板電性連接。圖案化金屬層位於密封體上。圖案化金屬層包括至少一凸出部以及由至少一凸出部所定義的至少一凹陷部。凸出部面向密封體。黏著層位於圖案化金屬層以及密封體之間。黏著層填充於凹陷部中。
Description
本發明是有關於一種封裝結構及其製造方法,且特別是有關於一種晶片封裝結構及其製造方法。
現今的電子元件需要小尺寸、大的存儲容量以及高性能,以作為例如行動通訊等應用。因此,用於例如行動通訊設備等現代電子設備的半導體晶片封裝,也必須具備小尺寸、大的存儲容量以及高性能。
一般而言,印刷電路板(printed circuit board;PCB)通常包括由聚醯亞胺(polyimide;PI)材料製成的絕緣基板以及由銅(Cu)製成的導電圖案。導電圖案可以位於基板的層與層之間,或者可以位於基板的一個表面之上。當晶片封裝用於電子系統時,例如:用於行動通訊設備的主機板中,封裝件可能因結合所需而須經由高熱製程。在形成焊球或於將晶片封裝連接到電路板的高熱製程中,由於晶片封裝中的不同組成之間的熱膨脹係數(coefficient of thermal expansion;CTE)不匹配(mismatch),可能導致晶片封裝的翹曲(warpage)。而翹曲可能導致晶片封裝與電路板之間的接點分離而損壞。這種翹曲在安裝期間也會導致焊球相對於主機板的高度不均勻,從而導致接觸損壞。
本發明提供一種晶片封裝結構及其製造方法,其晶片封裝結構的翹曲可以被改善,且可以提升晶片封裝結構的可靠度(reliability)。
本發明提供一種晶片封裝結構,其包括基板、晶片、密封體、多個焊球以及圖案化金屬層。基板具有彼此相對的第一表面以及第二表面。晶片配置於第一表面上且電性連接至基板。密封體密封晶片且覆蓋於第一表面。焊球位於第二表面上且與基板電性連接。圖案化金屬層位於密封體上,且圖案化金屬層包括凸向密封體的至少一凸出部。凸出部面向密封體。黏著層位於圖案化金屬層以及密封體之間。黏著層填充於凹陷部中。
在本發明的一實施例中,晶片封裝結構更包括多個焊球,位於第二表面上且與基板電性連接。
在本發明的一實施例中,基板包括重佈線路層,且重佈線路層與晶片以及多個焊球電性連接。
在本發明的一實施例中,基板包括多個圖案化線路層以及多個貫孔,多個圖案化線路層位於第一表面以及第二表面上,多個貫孔貫穿基板且電性連接多個圖案化線路層。
在本發明的一實施例中,晶片藉由覆晶接合或打線接合技術配置於基板上。
本發明提供一種晶片封裝結構的製造方法,該方法包括以下步驟。配置晶片於基板的第一表面上,其中晶片電性連接至基板。形成密封體以密封晶片並覆蓋第一表面。形成多個焊球於基板的第二表面上,其中第二表面相對於第一表面,且焊球電性連接至基板。形成圖案化金屬層,其中圖案化金屬層包括凸向密封體的至少一凸出部。形成黏著層以將圖案化金屬層黏著於密封體,其中凸出部面向密封體,且黏著層填充於凹陷部中。
在本發明的一實施例中,晶片封裝結構的製造方法更包括形成多個焊球於基板的第二表面上,其中第二表面相對於第一表面,且多個焊球電性連接至基板。
在本發明的一實施例中,其中圖案化金屬層藉由電鍍製程形成。
在本發明的一實施例中,其中凹陷部藉由蝕刻製程形成。
基於上述,在晶片封裝結構及其製造方法中,晶片封裝可能在形成焊球的高熱製程之後產生翹曲。因此,在本發明中,包括至少一個凸出部的圖案化金屬層藉由黏著層黏著於晶片封裝。圖案化金屬層的凸出部的位置對應於晶片封裝的翹曲,以將翹曲向下壓。如此一來,可以改善晶片封裝結構的翹曲,且提升了晶片封裝結構的可靠度。
為讓本發明的上述特徵和優點能更明顯易懂,下文特舉實施例,並配合所附圖式作詳細說明如下。
圖1是依據本發明一實施例的晶片封裝的示意圖。本實施例中,晶片封裝結構的製造方法可以包括以下步驟。首先,提供如圖1所示的晶片封裝105。在本實施例中,晶片120可以先配置於基板110上。基板110包括第一表面112、相對於第一表面112的第二表面114、分別設置在第一表面112與第二表面114上的多個圖案化電路層116以及貫穿基板110且電性連接至圖案化線路層116的多個通孔118。晶片120配置於基板110的第一表面112上,且藉由打線接合(wire bonding)技術電性連接至基板110。在本實施例中,晶片120可以包括主動面122以及位於主動面122上的多個接墊124。主動面122面離基板110,且晶片120的接墊124可以藉由多個導線126電性連接至圖案化線路層116。
接著,形成密封體130以密封晶片120以及導線126。密封體130覆蓋基板110的第一表面112。接著,形成多個焊球140於基板110的第二表面114上以電性連接至基板110。此時,基本上完成了如圖1所示的晶片封裝105的製造過程。在本實施例中,晶片封裝105可以為打線接合細間距球柵陣列(wire-bonding Fine-pitch Ball Grid Array;WB FBGA)封裝,但本發明不限於此。晶片封裝105可用於如圖2及圖3所繪示的一些實施例中作為說明。
請參照圖2,在本實施例中,晶片封裝105與圖1所繪示的晶片封裝結構105類似,其相同或類似的構件以相同或類似的標號表示,且具有相同或類似的功能,並省略描述。如圖2所示的晶片封裝105以及如圖1所示的晶片封裝105之間的主要差異如下所述。在本實施例中,晶片120藉由覆晶(flip-chip)接合技術配置於基板110上。在本實施例中,晶片的120的主動面122面向基板110,且晶片120的接墊124電性連接至基板110的圖案化線路層116。也就是說,圖2所示的晶片封裝105可以為覆晶晶片尺寸封裝(Flip-Chip Chip Scale Package;FCCSP),但本發明不限於此。
請參照圖3,在本實施例中,晶片封裝105與圖2所繪示的晶片封裝結構105類似,其相同或類似的構件以相同或類似的標號表示,且具有相同或類似的功能,並省略描述。如圖3所示的晶片封裝105以及如圖2所示的晶片封裝105之間的主要差異如下所述。在本實施例中,基板110可以包括重佈線路層,重佈線路層的線路層119電性連接晶片120以及焊球140。也就是說,圖3所示的晶片封裝105可以為扇出晶圓級晶片尺寸封裝(Fan-Out Wafer Level Chip Scale Package;FO WLCSP),但本發明不限於此。
本發明的晶片封裝105可藉由高熱製程以形成焊球140於基板110上及/或將晶片封裝105連接至電路板。由於晶片封裝105中的不同組成之間的熱膨脹係數不匹配,高熱處理可能導致晶片封裝105的翹曲。因此,可以形成如圖4所示的圖案化金屬層150。在本實施例中,圖案化金屬層150包括至少一個凸出部152。凸出部152的位置為依據晶片封裝105的翹曲來設計。舉例而言,在本實施方式中,晶片封裝105可能在中心區域發生翹曲,因此如圖4所示,凸出部152可以設置於圖案化金屬層150的中央區域。接著,圖案化金屬層150藉由黏著層160黏著於密封體130上。凸出部152可以面向且朝向密封體130凸出。可以向下按壓密封體130以減少晶片封裝105的翹曲。如圖5所示,黏著層160填充於圖案化金屬層150以及密封體130之間的間隙中。此時,基本上形成了晶片封裝結構100的製造方法。
在本實施例中,如圖5所示,圖案化金屬層150更包括由凸出部152所定義出的至少一個凹陷部154,且黏著層160填充於凹陷部154以及密封體130之間的間隙中。在本實施例中,凸出部152設置於圖案化金屬層150的中央區域且與密封體130接觸。因此,由凸出部152所定義的凹陷部154圍繞中央區域。因此,當圖案化金屬層150藉由黏著層160黏著於密封體130時,凸出部152凸向密封體130並與密封體130接觸,以向下擠壓密封體130以減少晶片封裝105的翹曲。在圖6所示的實施例中,凸出部152可以具有曲面。圖案化金屬層150的整個表面面向密封體130且可以具有朝向密封體130凸出的曲面。黏著層160填充於圖案化金屬層150以及密封體130之間的間隙中。
在本實施例中,可以先藉由電鍍製程(electroplating process)形成金屬層,然後藉由蝕刻製程(etching process)形成凹陷部154,但本發明對於圖案化金屬層150的製造方法並不加以限制。此外,值得注意的是,晶片封裝結構100採用如圖2所示的晶片封裝105,但本發明不限於此。圖案化金屬層150也可以黏著於其他類型的晶片封裝,例如:圖1及圖3所示的晶片封裝105,以減少其翹曲。在一些實施例中,凸出部152的至少一部分,例如:凸出部152的峰,可以與密封體130接觸。
圖7是依據本發明第三實施例的晶片封裝結構的示意圖。圖8是依據本發明第四實施例的晶片封裝結構的示意圖。請參照圖7及圖8,在本實施例中,晶片封裝結構100b、100c與圖5及圖6所繪示的晶片封裝結構100、100a類似,其相同或類似的構件以相同或類似的標號表示,且具有相同或類似的功能,並省略描述。如圖7及圖8所示的晶片封裝結構100b、100c與如圖5及圖6所示的晶片封裝結構100、100a之間的主要差異如下所述。
在本實施方式中,在形成焊球140的高熱製程之後,晶片封裝可能在周邊區域產生翹曲。也就是說,晶片封裝的周邊區域可以自焊球彎曲。因此,如圖7所示,在本實施方式中,凸出部152位於圍繞圖案化金屬層150的中央區域的周邊區域,凹陷部154位於圖案化金屬層150的中央區域。凸出部152與密封體130接觸,以向下擠壓晶片封裝的周邊區域。如此一來,可以改善晶片封裝結構100a的翹曲。在圖8所示的實施例中,凹陷部154可以具有曲面。
在本實施例中,圖案化金屬層150可以更包括至少一個通氣孔156。通氣孔156自凹陷部154的內表面延伸至圖案化金屬層150的外表面。如此一來,凹陷部154可以藉由通氣孔156與外部環境連通,以藉由通氣孔156排出空氣。此外,當圖案化金屬層150被壓在黏著層160上以黏著於密封體130上時,填充於凹陷部154中的部分黏著層160可以填充至通氣孔156中,以避免黏著層160的溢出。此外,值得注意的是,晶片封裝結構100a採用如圖2所示的晶片封裝105。然而,本發明不限於此。在本實施例中,圖案化金屬層150也可以黏著於其他類型的晶片封裝,例如:圖1及圖3所示的晶片封裝105,以減少其翹曲。
圖9是依據本發明第五實施例的晶片封裝結構的示意圖。圖10是依據本發明第六實施例的晶片封裝結構的示意圖。請參照圖9及圖10,在本實施例中,晶片封裝結構100d、100e與圖5及圖6所繪示的晶片封裝結構100、100a類似,其相同或類似的構件以相同或類似的標號表示,且具有相同或類似的功能,並省略描述。如圖9及圖10所示的晶片封裝結構100d、100e與如圖5及圖6所示的晶片封裝結構100、100a之間的主要差異如下所述。
在本實施方式中,在形成焊球140的高熱製程之後,晶片封裝可能產生具有多個凸出部以及多格凹陷部的不規則翹曲。因此,如圖9以及圖10所示,在本實施例中,圖案化金屬層150可以包括多個凸出部152以及由凸出部152所定義的多個凹陷部154。凸出部152的位置可以對應於翹曲的晶片封裝的凸出部,以將翹曲的晶片封裝向下壓。如此一來,可以改善晶片封裝結構100d的翹曲。在圖9所示的實施例中,凹陷部154可以具有曲面。
請參照圖10,在本實施例中,圖案化金屬層150可以更包括至少一個通氣孔156。通氣孔156自至少一個凹陷部154的內表面延伸至圖案化金屬層150的外表面。在本實施例中,圖案化金屬層150包括多個通氣孔156。各個通氣孔156自各個凹陷部154的內表面延伸至圖案化金屬層150的外表面。如此一來,凹陷部154可以藉由通氣孔156與外部環境連通,以藉由通氣孔156排出空氣。此外,當圖案化金屬層150被壓在黏著層160上以黏著於密封體130上時,填充於凹陷部154中的部分黏著層160可以填充至通氣孔156中,以避免黏著層160的溢出。此外,值得注意的是,晶片封裝結構100a採用如圖2所示的晶片封裝100d, 100e。然而,本發明不限於此。在本實施例中,圖案化金屬層150也可以黏著於其他類型的晶片封裝,例如:圖1及圖3所示的晶片封裝105,以減少其翹曲。在其他實施例中,於圖9及圖10中的至少一凸出部152可以與密封體130接觸。
綜上所述,在晶片封裝結構及其製造方法中,晶片封裝可能在形成焊球的高熱製程之後產生翹曲。因此,在本發明中,包括至少一個凸出部的圖案化金屬層藉由黏著層黏著於晶片封裝。圖案化金屬層的凸出部的位置對應於晶片封裝的翹曲,以將翹曲向下壓。如此一來,可以改善晶片封裝結構的翹曲,且提升了晶片封裝結構的可靠度。
雖然本發明已以實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明的精神和範圍內,當可作些許的更動與潤飾,故本發明的保護範圍當視後附的申請專利範圍所界定者為準。
100、100a、100b、100c、100d、100e‧‧‧晶片封裝結構
105‧‧‧晶片封裝
110‧‧‧基板
112‧‧‧第一表面
114‧‧‧第二表面
116‧‧‧圖案化線路層
118‧‧‧通孔
119‧‧‧線路層
120‧‧‧晶片
122‧‧‧主動面
124‧‧‧接墊
126‧‧‧導線
130‧‧‧密封體
140‧‧‧焊球
150‧‧‧圖案化金屬層
152‧‧‧凸出部
154‧‧‧凹陷部
156‧‧‧通氣孔
160‧‧‧黏著層
圖1是依據本發明一實施例的晶片封裝的示意圖。 圖2是依據本發明另一實施例的晶片封裝的示意圖。 圖3是依據本發明又一實施例的晶片封裝的示意圖。 圖4至圖5是依據本發明第一實施例的晶片封裝結構的部分製造方法的示意圖。 圖6是依據本發明第二實施例的晶片封裝結構的示意圖。 圖7是依據本發明第三實施例的晶片封裝結構的示意圖。 圖8是依據本發明第四實施例的晶片封裝結構的示意圖。 圖9是依據本發明第五實施例的晶片封裝結構的示意圖。 圖10是依據本發明第六實施例的晶片封裝結構的示意圖。
Claims (10)
- 一種晶片封裝結構,包括: 基板; 晶片,配置於所述基板上且電性連接至所述基板; 密封體,密封所述晶片且覆蓋於所述基板; 圖案化金屬層,位於所述密封體上,且所述圖案化金屬層包括凸向所述密封體的至少一凸出部;以及 黏著層,填充於所述圖案化金屬層以及所述密封體之間的間隙中。
- 如申請專利範圍第1項所述的晶片封裝結構,其中所述圖案化金屬層更包括由所述至少一凸出部所定義的至少一凹陷部,且所述黏著層填充於所述至少一凹陷部。
- 如申請專利範圍第2項所述的晶片封裝結構,其中所述至少一凸出部位於所述圖案化金屬層的中心區域並與所述密封體接觸,且所述至少一凹陷部圍繞所述中心區域。
- 如申請專利範圍第2項所述的晶片封裝結構,其中所述至少一凹陷部位於所述圖案化金屬層的中心區域,所述至少一凸出部位於所述圖案化金屬層的周邊區域,其中所述周邊區域圍繞所述中心區域,且所述至少一凸出部與所述密封體接觸。
- 如申請專利範圍第4項所述的晶片封裝結構,其中所述圖案化金屬層更包括至少一通氣孔,所述至少一通氣孔從所述至少一凹陷部的內表面延伸至所述圖案化金屬層的外表面。
- 如申請專利範圍第5項所述的晶片封裝結構,其中填充於所述至少一凹陷部中的所述黏著層被填充至部分的所述至少一通氣孔中。
- 如申請專利範圍第2項所述的晶片封裝結構,其中所述至少一凸出部或所述至少一凹陷部具有彎曲表面。
- 如申請專利範圍第2項所述的晶片封裝結構,其中所述至少一凹陷部的數量為多個,所述至少一凸出部的數量為多個,且所述圖案化金屬層更包括至少一通氣孔,所述至少一通氣孔從所述至少一凹陷部的內表面延伸至所述圖案化金屬層的外表面。
- 一種晶片封裝結構的製造方法,包括: 配置晶片於基板上,其中所述晶片電性連接至所述基板; 形成密封體,以密封所述晶片並覆蓋所述基板; 形成圖案化金屬層,其中所述圖案化金屬層包括凸向所述密封體的至少一凸出部;以及 形成黏著層,以將所述圖案化金屬層黏著於所述密封體,其中所述至少一凸出部面向且凸向所述密封體,所述黏著層填充於所述圖案化金屬層以及所述密封體之間的間隙中。
- 如申請專利範圍第9項所述的晶片封裝結構的製造方法,其中所述圖案化金屬層更包括由所述至少一凸出部所定義的至少一凹陷部,且所述黏著層填充於所述至少一凹陷部。
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- 2017-09-29 CN CN201710905860.3A patent/CN107978569B/zh active Active
- 2017-10-13 TW TW106135088A patent/TWI641086B/zh active
- 2017-10-13 US US15/782,857 patent/US10424526B2/en not_active Expired - Fee Related
- 2017-10-19 CN CN201710975918.1A patent/CN107978570B/zh active Active
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Publication number | Priority date | Publication date | Assignee | Title |
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TWI797790B (zh) * | 2021-10-21 | 2023-04-01 | 友達光電股份有限公司 | 電子裝置 |
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US20180114736A1 (en) | 2018-04-26 |
TWI646642B (zh) | 2019-01-01 |
US10424526B2 (en) | 2019-09-24 |
TW201816950A (zh) | 2018-05-01 |
CN107978570B (zh) | 2020-08-11 |
CN107978569B (zh) | 2020-03-13 |
TWI641086B (zh) | 2018-11-11 |
US20180114734A1 (en) | 2018-04-26 |
CN107978570A (zh) | 2018-05-01 |
US10177060B2 (en) | 2019-01-08 |
CN107978569A (zh) | 2018-05-01 |
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