TWI578454B - 扇出晶圓級晶片封裝結構及其製造方法 - Google Patents

扇出晶圓級晶片封裝結構及其製造方法 Download PDF

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Publication number
TWI578454B
TWI578454B TW103137864A TW103137864A TWI578454B TW I578454 B TWI578454 B TW I578454B TW 103137864 A TW103137864 A TW 103137864A TW 103137864 A TW103137864 A TW 103137864A TW I578454 B TWI578454 B TW I578454B
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Taiwan
Prior art keywords
wafer
conductive
power transistor
package structure
electrically connected
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TW103137864A
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English (en)
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TW201616618A (zh
Inventor
謝智正
許修文
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尼克森微電子股份有限公司
帥群微電子股份有限公司
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Priority to TW103137864A priority Critical patent/TWI578454B/zh
Priority to US14/791,310 priority patent/US9799563B2/en
Publication of TW201616618A publication Critical patent/TW201616618A/zh
Application granted granted Critical
Publication of TWI578454B publication Critical patent/TWI578454B/zh
Priority to US15/674,062 priority patent/US10381268B2/en

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Description

扇出晶圓級晶片封裝結構及其製造方法
本發明係有關於一種半導體封裝製程，特別是指一種扇出晶圓級晶片封裝結構及其製造方法。
隨著可攜式與穿戴式電子產品的發展，開發具有高效能、體積小、高速度、高品質及多功能性的產品成為趨勢。為了使消費型電子產品的外形尺寸朝向微型化發展，晶圓級晶片尺寸封裝(Wafer Level Chip Scale Package,WLCSP)製程成為在進行晶片封裝時經常採用的技術手段。
晶圓級晶片尺寸封裝製程與先前的技術最大的不同點在於，晶圓級晶片尺寸封裝製程是直接在晶圓上進行封裝製程，且一併對集成電路晶片(IC晶片)完成封裝，而非先切割晶圓後，再個別對IC晶片進行組裝。進行晶圓級晶片尺寸封裝製程後，成品的尺寸完全等同或稍微大於晶片尺寸。然而，晶圓級晶片尺寸封裝製程卻限制了線路佈局(layout)扇出(Fan-Out)的可變性。因此，現今業界亦發展出扇出晶圓級封裝(Fan-Out WLP)製程，以提供更多樣與彈性的佈線樣式，讓電路板表面黏著作業較簡單，提高良率。
在美國專利案US7759163中，揭示一種半導體模組製造方法。首先提供兩顆以上放置於載體上的半導體晶片，再覆蓋模塑材料以形成模封體。接著，需減薄模封體直到暴露出半導體晶片，再將半導體晶片與載體分離。然而，先成形模塑體再進行減薄， 容易在半導體晶片表面留下殘膠。並且，若半導體晶片的高度不一致，在薄化模封體時，有可能對半導體晶片表面造成損傷。另外，利用鑽孔技術在模塑體中開出通道，然後填入導電材料，將半導體晶片的背面電極引導至主動面，製程太複雜。
本發明實施例在於提供一種扇出晶圓級晶片封裝結構及其製造方法，其藉由導電蓋體來封裝倒置於承載板上的晶片，可免去後續對模塑體進行減薄的製程。此外，在本發明實施例所提供的封裝結構中，多個晶片可藉由導電蓋體配合線路連接層電性連接。
本發明其中一實施例提供一種晶片封裝結構的製造方法，包括下列步驟。首先，提供一承載板，承載板具有承載面，承載面上形成有可剝離膠層。設置多個晶片於承載面上，其中每一晶片具有一主動面及一背面，這些晶片的主動面貼附於可剝離膠層上。塗佈接合膠於晶片的背面。提供導電蓋體，導電蓋體具有底板及位於底板上的多個分隔板，這些分隔板形成多個容置區。貼附導電蓋體於承載面上以罩覆這些晶片，其中這些晶片分別位於容置區中並以分隔板相互間隔。接著，注入模封膠體於導電蓋體內，以填充分隔板與晶片之間的間隙。執行一固化製程，以形成模塑體。分離模塑體與承載板，其中各晶片的主動面位於模塑體的第一表面。形成線路連接層於模塑體的第一表面以連接這些晶片。之後，執行一切割步驟，以將模塑體分離為多個封裝結構，其中各封裝結構具有由導電蓋體切割所形成的導電架與由線路連接層切割所形成的線路層。
本發明其中一實施例提供一種封裝結構，適用於一電壓轉換電路，包括一導電架、一第一功率電晶體、一第二功率電晶體及一線路層。導電架具有底部與第一分隔板以形成第一容置區與第二容置區。第一分隔板位於第一容置區與第二容置區之間，而底部分為相互絕緣之第一導電區與第二導電區，其中第一分隔板與 第二導電區電性連接。第一功率電晶體封裝於第一容置區中，且第一功率電晶體的汲極電性連接至第一導電區。第二功率電晶體封裝於第二容置區中，且第二功率電晶體的汲極電性連接至第二導電區。線路層電性連接第一功率電晶體的第一主動面與第二功率電晶體的第二主動面，其中第一分隔板的端面、第一功率電晶體的第一主動面與第二功率電晶體的第二主動面共平面，第一功率電晶體的源極經由第一分隔板與第二導電區電性連接至第二功率電晶體的汲極。
本發明另一實施例提供一種封裝結構，除了上述的第一功率電晶體與第二功率電晶體之外，更包括封裝於第一容置區中的一控制晶片。控制晶片電性絕緣於該第一導電區，且線路層形成於控制晶片、第一功率電晶體的第一主動面與第二功率電晶體的第二主動面上，以電性連接控制晶片、第一功率電晶體與第二功率電晶體。
在本發明實施例所提供的晶片封裝結構的製造方法中，利用導電蓋體罩覆晶片後，再將模封膠體注入晶片與導電蓋體之間的間隙並進行固化，可控制封裝結構的尺寸，因此不需要再對模塑體進行減薄。另外，在對模塑體執行切割步驟時，可藉由改變切割的位置與切割深度來形成不同的封裝結構。
為使能更進一步瞭解本發明的特徵及技術內容，請參閱以下有關本發明的詳細說明與附圖，然而所附圖式僅提供參考與說明用，並非用來對本發明加以限制者。
1‧‧‧承載板
1a‧‧‧承載面
2‧‧‧可剝離膠層
3‧‧‧第一晶片
3a‧‧‧第一主動面
4a‧‧‧第二主動面
3b‧‧‧第一背面
4b‧‧‧第二背面
4、41‧‧‧第二晶片
42‧‧‧第三晶片
30‧‧‧控制晶片
5‧‧‧接合膠
6‧‧‧導電蓋體
60‧‧‧底板
600‧‧‧注膠孔
60a‧‧‧第一表面
60b‧‧‧第二表面
60c‧‧‧第一導電區
60d‧‧‧第二導電區
601‧‧‧切割記號
602‧‧‧切割槽
603‧‧‧絕緣槽
61‧‧‧分隔板
610‧‧‧端面
61a‧‧‧第一分隔板
61b‧‧‧第二分隔板
61c‧‧‧第三分隔板
620‧‧‧容置區
620a‧‧‧第一容置區
620b‧‧‧第二容置區
62‧‧‧邊框
7‧‧‧模封膠體
7a‧‧‧第一模封體
7b‧‧‧第二模封體
M1‧‧‧模塑體
M1’‧‧‧第一封裝結構
M2、M3、M4、M5‧‧‧封裝結構
8‧‧‧基板
9‧‧‧圖案化保護層
9a~9f‧‧‧開口
10a~10f‧‧‧凸塊底層金屬墊
11‧‧‧導線層
12a~12f、42a‧‧‧焊墊
20a、21a、22a‧‧‧第一切割線
20b、21b、22b‧‧‧第二切割線
S100~S109‧‧‧流程步驟
圖1為本發明實施例的扇出晶圓級晶片封裝結構的製造方法的流程圖。
圖2顯示本發明實施例的承載板的局部剖面示意圖。
圖3A顯示本發明實施例的晶片封裝結構在圖1的步驟S101中的俯視示意圖。
圖3B顯示圖3A沿H-H剖面線的剖面示意圖。
圖4顯示本發明實施例的封裝結構在圖1的步驟中的局部剖面示意圖。
圖5A顯示本發明實施例的封裝結構在圖1的步驟中的俯視示意圖。
圖5B顯示圖5A沿I-I剖面線的剖面示意圖。
圖5C顯示本發明實施例的封裝結構在圖1的步驟中的局部剖面示意圖。
圖6顯示本發明實施例的封裝結構在圖1的步驟中的局部剖面示意圖。
圖7顯示本發明實施例的封裝結構在圖1的步驟中的局部剖面示意圖。
圖8顯示本發明實施例的封裝結構在形成線路連接層前的步驟中的局部剖面示意圖。
圖9顯示本發明實施例的封裝結構在形成線路連接層前的步驟中的局部剖面示意圖。
圖10顯示本發明實施例的封裝結構在形成線路連接層的步驟中的局部剖面示意圖。
圖11顯示本發明實施例的封裝結構在形成線路連接層的步驟中的局部剖面示意圖。
圖12A顯示本發明實施例的封裝結構在圖1的步驟中的俯視示意圖。
圖12B顯示本發明實施例的晶片封裝結構在圖1的步驟S109切割前的局部剖面意圖。
圖13顯示本發明其中一實施例的封裝結構的在圖1的步驟S109切割後的剖面示意圖。
圖14A顯示本發明實施例的封裝結構應用於電路中的示意圖。
圖14B顯示本發明實施例的封裝結構的俯視示意圖。
圖15A顯示本發明另一實施例的封裝結構應用於電路中的示意圖。
圖15B顯示本發明另一實施例的封裝結構的俯視示意圖。
圖16A顯示本發明實施例的封裝結構應用於電路中的示意圖。
圖16B顯示本發明實施例的封裝結構的俯視示意圖。
圖17A顯示本發明另一實施例的封裝結構在圖1的步驟中的俯視示意圖。
圖17B顯示本發明另一實施例的封裝結構的俯視示意圖。
圖18A顯示本發明又一實施例的封裝結構在圖1的步驟中的俯視示意圖。
圖18B顯示本發明又一實施例的封裝結構的俯視示意圖。
以下是藉由特定的具體實例來說明本發明所揭露“扇出晶圓級晶片封裝結構及其製造方法”的實施方式，熟悉此技藝的相關人士可由本說明書所揭示的內容輕易瞭解本發明的優點與功效。本發明亦可藉由其他不同的具體實施例加以施行或應用，本說明書中的各項細節亦可基於不同觀點與應用，在不悖離本發明的精神下進行各種修飾與變更。另外，本發明的圖式僅為簡單說明，並非依實際尺寸描繪，亦即未反應出相關構成的實際尺寸，先予敘明。以下的實施方式將進一步詳細說明本發明的相關技術內容，但所揭示的內容並非用以限制本發明的技術範疇。
請參閱圖1，其顯示本發明一實施例的扇出晶圓級晶片封裝結構的製造方法的流程圖。本發明實施例所提供的扇出晶圓級晶片封裝結構的製造方法可應用於晶片的封裝。
在步驟S100中，提供一承載板。承載板具有一承載面，承載面上形成有可剝離膠層。在步驟S101中，設置多個晶片於可剝離膠層上，其中每一晶片具有主動面及背面，這些晶片的主動面貼 附於可剝離膠層上。在步驟S102中，塗佈接合膠於各晶片的背面。在步驟S103中，提供導電蓋體以作為模具，導電蓋體具有底板及位於底板上的多個分隔板，這些分隔板形成多個容置區。
在步驟S104中，貼附導電蓋體於承載面上以罩覆所有晶片，其中這些晶片是分別位於容置區中，並以這些分隔板相互間隔。在步驟S105中，注入模封膠體於導電蓋體內，以填充這些分隔板與晶片之間的間隙。在步驟S106中，執行固化製程，形成一模塑體。在步驟S107中，分離模塑體與承載板，其中各晶片的主動面是位於模塑體的上表面。
在步驟S108中形成線路連接層於模塑體的上表面，以連接這些晶片與外部線路。在步驟S109中，執行切割步驟，以將模塑體分離為多個封裝結構，其中各封裝結構具有由導電蓋體切割所形成的導電架與由線路連接層切割所形成的線路層。
下文中將以實例進一步說明圖1中各個步驟的細節。請配合參照圖2，其顯示本發明實施例的承載板的局部剖面示意圖。所述承載板1具有一承載面1a，所述承載面1a上形成有一可剝離膠層2。
構成承載板1的材料可以是導電的或絕緣的材質，例如金屬、金屬合金、塑膠或石英玻璃等材料。另外，可剝離膠層2可以層壓於承載板1上。在一實施例中，可剝離膠層2是雙面皆具有黏性的膠帶。在本發明實施例中，承載板1的形狀與尺寸可與晶圓一致，例如是6吋、8吋或12吋。在其他實施例中，承載板1的形狀為方形。
請配合參照圖3A，顯示本發明實施例的封裝結構在圖1的步驟S101中的俯視示意圖。在本實施例中，是預先對多種相同或不同的晶片重新配置。也就是說，這些晶片會根據實際應用的需要，而分別被固定於可剝離膠層2上的多個預定位置。
這些晶片可以是相同或者是不同的半導體元件，例如是功率 電晶體、集成電路元件或是二極體等等。功率電晶體例如是垂直式功率電晶體、絕緣閘雙極型電晶體(Insulated Gate Bipolar Transistor,IGBT)或是底部源極橫向雙擴散金氧半場效電晶體(bottom-source lateral diffusion MOSFET)。每一晶片具有主動面與背面，且這些晶片是以主動面貼附於可剝離膠層2上。
在本實施例中，以多個晶片中相鄰的一第一晶片3與一第二晶片4為例，來進行說明。請參照圖3B，顯示圖3A沿H-H剖面線的剖面示意圖。第一晶片3具有一第一主動面3a及與第一主動面3a相反的第一背面3b。由圖3B可看出，第一晶片3是以第一主動面3a朝向可剝離膠層2而設置。第二晶片4也同樣具有第二主動面4a及第二背面4b，並以主動面4a貼附於可剝離膠層2上。
在一實例中，第一晶片3與第二晶片4分別為第一功率電晶體及第二功率電晶體，且第一晶片3的閘極(未標號)與源極(未標號)是形成於第一主動面3a，而汲極(未標號)是形成第一晶片3的第一背面3b。相似地，第二晶片4的閘極(未標號)與源極(未標號)是形成於第二主動面4a，而汲極(未標號)是形成第二晶片4的第二背面4b。
請參照圖4，其顯示本發明實施例的晶片封裝結構在圖1的步驟S102中的局部剖面示意圖。在圖4中，接合膠5被塗佈於各晶片的背面。在一實施例中，是利用點膠或者是網版塗佈的方式，將適量的接合膠5放置於每一晶片的背面。接合膠5可以根據晶片的種類以及線路設計的需要選擇導電膠或者絕緣膠，其中導電膠例如是銀膠，錫膏或銅膏等具導電性的接合材料。絕緣膠可以是絕緣的高散熱膠。
在圖4的實施例中，第一晶片3與第二晶片4為垂直式功率電晶體，因此塗佈於第一晶片3的背面3b與第二晶片4的背面4b的接合膠5為導電膠。但在其他實施例中，當晶片為控制晶片時，接合膠為絕緣膠。
請參照圖5A與圖5B，其中圖5A顯示本發明實施例的封裝結構在圖1的步驟S103的俯視示意圖，圖5B顯示圖5A沿I-I剖面線的剖面示意圖。構成導電蓋體6的材質可以是銅、鐵鎳合金或其他合金。在本實施例中，構成導電蓋體6的材質為銅合金，且導電蓋體的厚度介於25至100μm。此外，導電蓋體可透過蝕刻、衝壓或壓印等技術手段來製作，本發明並不以此為限。
在圖5A實施例中，導電蓋體6具有一底板60、一邊框62及多個分隔板61，其中邊框62與底板60定義出一容置空間，而多個分隔板61用以將容置空間區隔為多個可相互連通的容置區620。
底板60的形狀可以配合承載板1的形狀或晶片配置的區域而呈圓形、方形或其他幾何形狀，本發明並不以此為限。詳細而言，底板60具有一第一表面60a及與第一表面60a相對的一第二表面60b，其中第一表面60a為導電蓋體6的背面。在一實施例中，導電蓋體6具有一形成於底板60上的注膠孔600。要特別說明的是，在本實施例中，注膠孔600的是形成於底板60上，但在其他實施例中，注膠孔600也可以開設於邊框62上，本發明實施例並不以此為限。
另外，在本實施例中，底板60的第一表面60a上可對應容置區620而預先形成多個切割記號601(圖中繪示一個為例)及多個切割槽602(圖中繪示一個為例)。多個切割記號601與多個切割槽602的位置與分隔板61的位置錯開。在本實施例中，切割記號601為一缺口，以定義出在後續的切割步驟中，將形成絕緣槽的位置。切割槽602則用以定義每一封裝結構的邊界。切割記號601與切割槽602的作用將在後文中詳細說明。在一實施例中，切割槽602的寬度大約是50μm。
邊框62凸出於底板60的第二表面60b，並環設於底板60的周邊區域。另外，邊框62與底板60所定義出的容置空間可容納 所有晶片。多個分隔板61凸出於底板60的第二表面60b，以將容置空間區隔為多個可相互連通的容置區620。這些容置區620分別用以容置多個晶片，且容置區620的大小可依據晶片的尺寸進行設計。
在一實施例中，多個分隔板61是呈陣列分布於底板60上，而兩相鄰分隔板之間的間距大小可以略大於晶片的寬度，而邊框以及每一分隔板61的高度大於晶片的厚度。
在圖5B的實施例中，是以第一分隔板61a、第二分隔板61b與第三分隔板61c為例進行說明。詳細而言，第一分隔板61a、第二分隔板61b、第三分隔板61c與底板60之間定義出一第一容置區620a以及一第二容置區620b，其中第一分隔板61a位於第一容置區620a與第二容置區620b之間。
另外，請繼續參照圖5A與圖5C，其中圖5C顯示本發明實施例的晶片封裝結構在圖1的步驟S104中的局部剖面示意圖。在步驟S104中，貼附導電蓋體6於承載面1a上以罩覆所有晶片。圖5C中顯示，當貼附導電蓋體6罩覆於承載面1a上時，第一晶片3與第二晶片4分別位於第一容置區620a與第二容置區620b內。也就是說，第一分隔板61a是位於第一晶片3與第二晶片4之間。
另外，在一實施例中，當貼附導電蓋體6於承載面1a上時，邊框62與每一分隔板61的端面610也貼附到可剝離膠層2上，從而使第一晶片3的第一主動面3a以及第二晶片4的第二主動面4a與分隔板61的端面610共平面。另外，導電蓋體6的容置空間僅通過注膠孔600和外界連通。
第一晶片3藉由第一背面3b的接合膠5貼附於導電蓋體6。在本實施例中，若第一晶片3為垂直式功率電晶體，接合膠5為導電膠，使第一晶片3的汲極可藉由接合膠5與導電蓋體6電性連接。相似地，第二晶片4的汲極也可藉由接合膠5與導電蓋體6電性連接。在其他實施例中，當晶片為控制晶片時，接合膠5是 絕緣膠，使晶片與導電蓋體6彼此電性隔絕。
接著，請參照圖6，其顯示本發明實施例的晶片封裝結構在圖1的步驟S105與S106中的局部剖面示意圖。在步驟S105中，注入一模封膠體7於導電蓋體6內，以填充這些分隔板與晶片之間的間隙。模封膠體7可以是任何合適的熱塑性或熱固性材料，例如是環氧基材料、矽膠或光阻劑等樹脂。在一實施例中，模壓模塑或注塑模塑等技術可用來使模封膠體7覆蓋每一容置區620內的晶片。
在本實施例中，於注入模封膠體7之前，先通過底板60的注膠孔600對容置空間抽真空，再通過注膠孔600注入模封膠體7。在本實施例中，模封膠體7為液態矽膠。
要特別說明的是，容置空間內部呈真空狀態，有助於將模封膠體7吸入並流動至各個容置區620內，並可減少氣孔產生。在一實施例中，在注入模封膠體7的過程中，會持續或間歇地旋轉承載板1，以帶動導電蓋體6旋轉，也有助於模封膠體7更快地填入各容置區620內。
接著，在步驟S106中，執行一固化製程，以形成一模塑體。在本發明實施例中，是藉由一加熱製程來將模封膠體7固化。在圖6的實施例中，模封膠體7填入第一容置區620a與第二容置區620b內將第一晶片3與第二晶片4完全包覆，並經過固化而分別於第一容置區620a內形成第一模封體7a與第二模封體7b。
請參照圖7，其顯示本發明實施例的晶片封裝結構在圖1的步驟S107中的局部剖面示意圖。在步驟S107中，分離模塑體M1與承載板1。
第一晶片3的第一主動面3a與第二晶片4的第二主動面4a，以及第一分隔板61a、第二分隔板61b與第三分隔板61c的端面610位於模塑體M1的第一表面(圖7導電蓋體6朝下的那一面)。另外，在本實施例中，模塑體M1的第二表面(圖7導電蓋體6朝 上的那一面)即為導電蓋體6的底板60的第一表面60a。圖7中並顯示將模塑體M1由承載板1分離。經過上述製程所形成的模塑體M1的上表面具有較平整的結構，例如第一分隔板61a與第一晶片3的第一主動面3a共平面，且模塑體M1較不容易產生翹曲問題，也無須進行減薄製程。
在步驟S108中，形成線路連接層於模塑體的第一表面以連接多個晶片。在一實施例中，在形成線路連接層之前，可先將模塑體翻轉(即如圖8所示將模塑體M1的第一表面轉呈朝上，並將模塑體M1的第二表面轉朝下)放置於基板8上，使模塑體M1的第二表面與基板8結合，並選擇性地於模塑體M1的第一表面形成保護層。請參照圖8至圖9，分別顯示本發明實施例的晶片封裝結構在形成線路連接層前的各步驟中的局部剖面示意圖。在圖8的步驟中，模塑體M1設置於基板8上，且模塑體M1的第二表面是朝向基板8設置。基板8主要是用以承載模塑體M1，可以是玻璃基板、塑膠基板或者是其他任意材質，本發明實施例並不限制。
請繼續參照圖9。在圖9中，形成圖案化保護層9覆蓋模塑體M1的第一表面。圖案化保護層9可保護晶片的主動面在後續製程中不被汙染與制定線路連接層的位置與尺寸。另外，圖案化保護層9具有多個開口9a~9f，以暴露第一晶片3與第二晶片4的閘極與源極，以及第一分隔板61a與第二分隔板61b的端面610。
形成圖案化保護層9的手段可通過任何習知的技術手段，例如通過沉積、微影及蝕刻等製程來形成圖案化保護層。在一實施例中，圖案化保護層9為介電層，可以是磷矽玻璃(phosphosilicate glass)、聚醯亞胺(polyimide)或者是氮化物(nitride)。然而，在其他實施例中，若是晶片的主動面已經具有鈍化層或保護層，則可省略圖9的步驟。
在一實施例中，線路連接層可包括多個凸塊底層金屬墊，導線層以及多個焊墊。請參照圖10至圖11，分別顯示本發明實施例 的晶片封裝結構在形成線路連接層的各步驟中的局部剖面示意圖。
請參照圖10，形成多個凸塊底層金屬墊10a~10f於各個開口9a~9f中。這些凸塊底層金屬墊10a~10f分別接觸第二分隔板61b的端面610、第一晶片3的閘極與源極、第一分隔板61a的端面610以及第二晶片4的閘極與源極。另外，在圖案化保護層9上形成一導線層11，連接凸塊底層金屬墊10c以及凸塊底層金屬墊10d。
要特別說明的是，凸塊底層金屬墊10c是電性連接於第一晶片3的源極，而另一凸塊底層金屬墊10d是電性連接第二晶片4的汲極。也就是說，在形成導線層11連接於凸塊底層金屬墊10c與10d之間時，可使第一晶片3的源極與第二晶片4的汲極電性連接。
接著，請參照圖11，於每一凸塊底層金屬墊10a~10f上分別形成一焊墊12a~12f，以作為連接外部線路的接點。詳細而言，在圖11的實施例中，位於第二分隔板61b的端面610上的焊墊12a藉由第二分隔板61b以及底板60可電性連接至第一晶片3的汲極。因此，焊墊12a可做為電壓輸入(VIN)焊墊。另外，分別位於第一晶片3的閘極上的焊墊12b以及位於第二晶片4的閘極上的焊墊12e，可分別做為上閘極焊墊與下閘極焊墊。
如前所述，第一晶片3的源極與第二晶片4的汲極透過導線層11、第一分隔板61a以及底板60電性連接。因此，位於第一晶片3的源極上的焊墊12c以及在第一分隔板61a的端面610上的焊墊12d皆可做為切換節點焊墊。
另外，位於第二晶片4的源極上的焊墊12f可做為接地焊墊。在本實施例中，第二晶片4具有多個源極。在這種情況下，第二晶片4的多個源極會分別形成多個焊墊12f，且這些焊墊12f皆做為接地焊墊。
在上述的實施例中，是假設第一晶片3與第二晶片4為垂直式功率電晶體進行說明。當晶片為其他半導體元件時，可根據應用電路的需要改變佈線的方式，而在主動面上形成不同的線路連接層。因此，在本發明中，並不限制線路連接層的實施態樣。
在完成線路連接層的製作後，將基板8由模塑體M1第二表面移除。此時，可以對晶片進行測試，並以雷射標號等製程。
接著，請參照圖12A與圖12B，其中圖12A顯示本發明實施例的晶片封裝結構在圖1的步驟S109中的俯視示意圖，圖12B顯示本發明實施例的晶片封裝結構在圖1的步驟S109切割前的局部剖面意圖。請參照圖13，顯示本發明其中一實施例的封裝結構的在圖1的步驟S109切割後的剖面示意圖。
在步驟S109中，執行一切割步驟，以將模塑體M1分離為多個封裝結構。各封裝結構具有由導電蓋體6切割所形成的一導電架與由線路連接層切割所形成的一線路層。在執行切割步驟時，是由模塑體M1的第二表面進行切割。在執行切割步驟時，可以藉由機械式刀具(如：鑽石刀)或是利用濕蝕刻來完成。
在本發明實施例中，可以根據晶片將在電路中的運作方式，來改變切割的位置以及深度，以形成不同的封裝結構。在圖12A的實施例中，模塑體M1被切割之後，第一晶片3與第二晶片4共同被封裝在一第一封裝結構M1’內，如圖13所示。
如前所述，在本發明實施例中，如圖12所示在導電蓋體6的底板60上已形成切割記號601與切割槽602兩種不同切割深度的記號，以便在切割步驟中，可沿著切割記號601對模塑體M1進行淺切割步驟(如圖12A的第一切割線20a)，並沿著切割槽602進行切穿步驟(如圖12A的第二切割線20b)。
詳細而言，請參照圖12A，執行切割步驟時，可依據切割記號601的位置，沿著第一切割線20a由模塑體M1的第二表面執行淺切割步驟。在淺切割步驟中，僅是將連接第一晶片3與第二晶 片4之間的導電蓋體6的底板60切開，以使第一晶片3的汲極與第二晶片4的汲極電性隔離，並不切開第一模封體7a。並且，執行淺切割步驟後，將在第一封裝結構M1’的背面形成至少一絕緣槽603，如圖13所示。
另外，在切割步驟中，更包括依據切割槽602的位置，沿著第二切割線20b執行一切穿步驟，以形成多個相互分離的封裝結構。切穿步驟包括在X方向沿著第二切割線20b與在X方向沿第二切割線20b進行切割。
本實施例中，圖13的第一封裝結構M1’可適用於電壓轉換電路，包括第一導電架、第一晶片3、第二晶片4與第一線路層。
詳細而言，第一導電架至少具有底部與第一分隔板61a，其中底板60係經過上述的切割步驟後，底板60被切割而形成底部。在圖13的底部包括第一導電區60c與第二導電區60d。第二導電區60d與第一分隔板61a共同形成第一容置區620a(圖13右邊部分，參考第5B圖對應位置)，且第一導電區60c與第二分隔板61b共同形成第一容置區620a(圖13左邊部分，參考第5B圖對應位置)。換言之，第一分隔板61a是位於第一容置區620a與第二容置區620b之間。
經過上述的淺切割步驟後，底板60被切割而形成底部，且底部被絕緣槽603區隔為相互絕緣的第一導電區60c與第二導電區60d。也就是說，絕緣槽603是位於第一導電區60c與一第二導電區60d之間。然而，上述的第一分隔板61a仍與第二導電區60d電性連接。
第一晶片3被第一模封體7a封裝於第一容置區620a內，且第一晶片3的汲極是藉由導電膠電性連接於第一導電區60c。第二晶片4則被第二模封體7b封裝於第二容置區620b內，且第二晶片4的汲極藉由導電膠電性連接至第二導電區60d。本發明實施例的第一封裝結構M1’中，更包括一第二分隔板61b。第二分隔板 61b形成於第一導電架的一側，並和第一分隔板61a共同形成第一容置區620a。
第一線路層形成於第一晶片3的主動面3a與第二晶片4的主動面4a上，以電性連接第一晶片3與第二晶片4。詳細而言，如上所述，第一線路層可包括在圖10至圖11中形成的多個凸塊底層金屬墊10a~10f、導線層11以及多個焊墊12a~12f。第一線路層即針對第一晶片3的第一主動面3a與第二晶片4的第二主動面4a上面的線路連接層切割所形成的一線路層。如圖12B，沿第二切割線20b進行切穿後，線路連接層形成圖13上面線路層。
另外，這些焊墊12a~12f中至少具有一電壓輸入焊墊、一上閘極焊墊、一下閘極焊墊、至少一切換節點焊墊與至少一接地焊墊。電壓輸入焊墊透過第二分隔板61b與第一導電區60c電性連接於第一晶片3的汲極，如焊墊12a。上閘極焊墊電性連接至該第一晶片3的閘極，如焊墊12b。下閘極焊墊電性連接至第二晶片4的閘極，如焊墊12e。切換節點焊墊電性連接至第一晶片3的源極與第二晶片4的汲極，如焊墊12c與12d。接地焊墊則電性連接第二晶片4的源極，如焊墊12f。在本實施例中，第二晶片4是具有兩個接地焊墊。
在上述的實施例中，第一晶片3與第二晶片4是共同配合在同一電路，例如在電壓轉換電路中運作，因此，第一晶片3與第二晶片4是共同被封裝在第一封裝結構M1’內。在其他實施例中，兩相鄰的第一晶片3與第二晶片4也可以單獨運作於電路中。在這種情況下，可在切割步驟中，將第一晶片3與第二晶片4切割開以形成各自獨立的封裝結構。
請參照圖14A與圖14B。圖14A顯示本發明實施例的封裝結構應用於電路中的示意圖。圖14B顯示本發明實施例的封裝結構的俯視示意圖。由圖14A與圖14B可看出，圖14B中的第一封裝結構M1’的各個焊墊可直接作為外部電路的接點。舉例而言，控 制元件(未標號)的VIN接腳可電性連接至焊墊12a，GH接腳可電性連接至焊墊12b、SW接腳可電性連接至焊墊12c，GL接腳可電性連接至焊墊12d而GND接腳可電性連接至焊墊12f。
也就是說，應用本發明實施例的扇出晶圓級晶片封裝結構的製造方法所製作的封裝結構，已藉由導電架與線路層建立了晶片之間的電性連接。因此，本發明實施例的封裝結構實際上為電路元件的半成品，而可直接應用於電路中。
請參照圖15A與圖15B。圖15A顯示本發明另一實施例的封裝結構應用於電路中的示意圖。圖15B顯示本發明另一實施例的封裝結構的俯視示意圖。
圖15A顯示另一種電壓轉換電路。相較於圖14A的電壓轉換電路，在圖15A的電路圖中，運用了三個功率電晶體，其中一個為高側的功率電晶體(high-side MOSFET)，而另外兩個為低側的功率電晶體(low-side MOSFET)。
在本實施例中，藉由適當的設計切割位置與切割深度可形成應用於圖15A中的封裝結構M2。封裝結構M2具有一個第一晶片3與兩個第二晶片41，其中兩個第二晶片41皆位於第二容置區620b中(參考圖5B對應位置)，且兩個第二晶片41的汲極皆與第二導電區60d電性連接(參考圖13)。在本實施例中，執行切割步驟以形成封裝結構M2的切割方式和前一實施例相同。
另外，封裝結構中除了第一晶片3與第二晶片41之外，可更包括一第三晶片42，其中第一晶片3與第二晶片41為主動元件，第三晶片42為被動元件，例如二極體，顯示如下圖16A與圖16B。
詳細而言，請參照圖16A與圖16B。圖16A顯示本發明另一實施例的封裝結構應用於電路中的示意圖。圖16B顯示本發明另一實施例的封裝結構的俯視示意圖。在圖16A所示的電壓轉換電路中，除了應用高側功率電晶體與低側功率電晶體之外，低側的功率電晶體並聯一二極體。
圖16B所示的封裝結構M3中除了第一晶片3與第二晶片41之外，更包括一第三晶片42，其中第一晶片3被封裝於第一容置區620a中，而第二晶片41與第三晶片42被封裝於第二容置區620b中。在本實施例中，第一晶片3與第二晶片41皆為功率電晶體，而第三晶片42為二極體。此外，第一晶片3、第二晶片4與第三晶片42可透過導線架與線路層依據圖16A所示的電路圖進行電性連接。在本實施例中，執行切割步驟以形成封裝結構M2的切割方式和前一實施例相同。
在其他實施例中，藉由改變切割位置與切割深度可形成另一封裝結構。請參照圖17A與圖17B。圖17A示本發明另一實施例的封裝結構在切割步驟中的俯視示意圖。圖17B顯示本發明另一實施例的封裝結構的俯視示意圖。
在圖12A的實施例中，只有在Y方向上沿第一切割線20a執行淺切割步驟。在圖17A的實施例中，執行切割步驟時，除了在Y方向上沿第一切割線21a執行淺切割步驟之外，也在X方上沿第一切割線21a執行淺切割步驟。另外，在X方向與Y方向上皆沿第二切割線21b執行切穿步驟以形成多個封裝結構M4。請參照圖17B，切割後的封裝結構M4包括兩個相鄰但位於不同容置區的第一晶片3，以及兩個相鄰但位於不同容置區的第二晶片4。
在本發明另一實施例中，可將電壓轉換電路中的控制晶片、高側功率電晶體與低側功率電晶體共同封裝在一個封裝結構中。請參照圖18A與圖18B。圖18A示本發明又一實施例的封裝結構在切割步驟中的俯視示意圖。圖18B顯示本發明又一實施例的封裝結構的俯視示意圖。
封裝結構M5包括控制晶片30、第一晶片3與第二晶片4。其中控制晶片30藉由導線架與線路層可電性連接至第一晶片3與第二晶片4的控制端。在本實施例中，控制晶片30與第一晶片3上下相鄰但放置於不同的容置區內，而第二晶片4則對應放置於兩 個容置區中。
如圖18A所示，在執行切割步驟時，只在Y方向上沿第一切割線22a執行淺切割步驟，以電性隔絕第一晶片3與第二晶片4的汲極。另外，在X方向與Y方向上皆沿第二切割線21b執行切穿步驟以形成多個封裝結構M5。
〔實施例的可能功效〕
綜上所述，本發明的有益效果可以在於，在本發明實施例所提供的晶片封裝結構的製造方法中，利用導電蓋體罩覆晶片後，再將模封膠體注入晶片與導電蓋體之間的間隙並進行固化，可使封裝結構的尺寸薄化，並且不需要對模塑體進行研磨。另外，在對模塑體執行切割步驟時，可藉由改變切割的位置與切割深度來形成不同的封裝結構。
另外，本發明實施例所提供的封裝結構，直接在電極上形成可直接連接於電路板的焊墊，可減少寄生電阻與寄生電感。當本實施例的封裝模組應用於電路元件中時，可提升元件運作的效率。本發明實施例的封裝結構並具有導電架，可提供較佳的散熱效果。
以上所述僅為本發明的較佳可行實施例，非因此侷限本發明的專利範圍，故舉凡運用本發明說明書及圖式內容所做的等效技術變化，均包含於本發明的保護範圍內。
S100~S109‧‧‧流程步驟

Claims (15)

  1. 一種扇出晶圓級晶片封裝結構的製造方法，其包括：提供一承載板，具有一承載面，該承載面上形成有一可剝離膠層；設置多個晶片於該可剝離膠層上，其中每一該些晶片具有一主動面及一背面，該些晶片的該些主動面貼附於該可剝離膠層上；塗佈接合膠於該些晶片的背面；提供一導電蓋體以作為模具，該導電蓋體具有一底板及位於該底板上的多個分隔板，該些分隔板形成多個容置區；貼附該導電蓋體於該承載面上以罩覆該些晶片，其中該些晶片分別位於該些容置區中並以該些分隔板相互間隔，且該導電蓋體通過該接合膠連接於該些晶片的背面；在貼附該導電蓋體於該承載面上的步驟之後，注入一模封膠體於該導電蓋體內，以填充該些分隔板與該些晶片之間的間隙；執行一固化製程，以形成一模塑體；分離該模塑體與該承載板，其中各該晶片的主動面位於該模塑體的一第一表面；形成一線路連接層於該模塑體的該第一表面以連接該些晶片；以及執行一切割步驟，以將該模塑體分離為多個封裝結構，其中各該封裝結構具有由該導電蓋體切割所形成的一導電架與由該線路連接層切割所形成的一線路層。
  2. 如請求項1所述的扇出晶圓級晶片封裝結構的製造方法，其中該些封裝結構的一第一封裝結構包括一第一晶片與一第二晶片、一第一導電架與一第一線路層，該第一導電架具有一第一 分隔板，位於該第一晶片與該第二晶片之間，該第一晶片與該第二晶片透過該第一導電架與該第一線路層電性連接。
  3. 如請求項2所述的扇出晶圓級晶片封裝結構的製造方法，其中該第一晶片為一第一功率電晶體，該第二晶片為一第二功率電晶體，該第一線路層具有一上閘極焊墊、一下閘極焊墊、一切換節點焊墊與至少一接地焊墊，其中該上閘極焊墊電性連接至該第一功率電晶體的閘極，該下閘極焊墊電性連接至該第二功率電晶體的閘極，該切換節點焊墊通過該第一導電架電性連接至該第一功率電晶體的源極與該第二功率電晶體的汲極。
  4. 如請求項1所述的扇出晶圓級晶片封裝結構的製造方法，其中該導電蓋體具有一邊框，該些分隔板與該邊框的高度大於該些晶片的厚度，且在貼附該導電蓋體至該承載面之步驟中，該邊框與該分隔板的端面貼附至該可剝離膠層上。
  5. 如請求項1所述的扇出晶圓級晶片封裝結構的製造方法，其中該導電蓋體的背面具有多個切割槽以定義該些封裝結構的邊界。
  6. 如請求項1所述的扇出晶圓級晶片封裝結構的製造方法，其中該導電蓋體的背面包括多個切割記號，且該切割步驟更包括：依據該切割記號切割該導電蓋體的該底板以於各該封裝結構的背面形成至少一絕緣槽，該至少一絕緣槽使該導電架被分割為至少兩個導電區。
  7. 如請求項2所述的扇出晶圓級晶片封裝結構的製造方法，其中該第一封裝結構更包括一第三晶片，其中該第一晶片與該第二晶片為主動元件，該第三晶片為被動元件，該第一晶片、該第二晶片與該第三晶片透過該第一導電架與該第一線路層相互電性連接。
  8. 如請求項7所述的扇出晶圓級晶片封裝結構的製造方法，其中該第一晶片與該第二晶片為功率電晶體，該第三晶片為二極體。
  9. 如請求項2所述的扇出晶圓級晶片封裝結構的製造方法，該第一封裝結構更包括一控制晶片，透過該第一導電架與該第一線路層電性連接至該第一晶片與該第二晶片的控制端。
  10. 如請求項9所述的扇出晶圓級晶片封裝結構的製造方法，其中黏接該控制晶片的背面與該第一導電架的接合膠為絕緣膠。
  11. 一種封裝結構，適用於一電壓轉換電路，包括：一導電架，具有一底部與一第一分隔板以形成一第一容置區與一第二容置區，該第一分隔板位於該第一容置區與該第二容置區之間，該底部分為相互絕緣之一第一導電區與一第二導電區，其中該第一分隔板與該第二導電區電性連接；一第一功率電晶體，封裝於該第一容置區中，該第一功率電晶體的汲極電性連接至該第一導電區，其中，該第一導電區經由一導電膠連接至該第一功率電晶體的背面；一第二功率電晶體，封裝於該第二容置區中，該第二功率電晶體的汲極電性連接至該第二導電區，該第二導電區經由另一導電膠連接至該第二功率電晶體的背面；以及一線路層，電性連接該第一功率電晶體的第一主動面與該第二功率電晶體的第二主動面；其中，該第一分隔板的端面、該第一功率電晶體的第一主動面與該第二功率電晶體的第二主動面共平面，該第一功率電晶體的源極經由該第一分隔板與該第二導電區電性連接至該第二功率電晶體的汲極。
  12. 如請求項11所述的封裝結構，其中該線路層具有一上閘極焊墊、一下閘極焊墊、一切換節點焊墊與至少一接地焊墊，其中該上閘極焊墊電性連接至該第一功率電晶體的閘極，該下閘極焊墊電性連接至該第二功率電晶體的閘極，該切換節點焊墊通過該第一分隔板與該第二導電區電性連接至該第一功率電晶體的源極與該第二功率電晶體的汲極。
  13. 如請求項11所述的封裝結構，其中該底部形成有一絕緣槽，位於第一導電區與一第二導電區之間。
  14. 如請求項11所述的封裝結構，更包括一第二分隔板，位於該導電架的一側，其中該第二分隔板與該第一分隔板形成該第一容置區。
  15. 一種封裝結構，適用於一電壓轉換電路，包括：一導電架，具有一底部與一第一分隔板以形成一第一容置區與一第二容置區，該第一分隔板位於該第一容置區與該第二容置區之間，該底部分為相互絕緣之一第一導電區與一第二導電區，其中該第一分隔板與該第二導電區電性連接；一第一功率電晶體，封裝於該第一容置區中，該第一功率電晶體的汲極電性連接至該第一導電區；一控制晶片，封裝於該第一容置區中，該控制晶片電性絕緣於該第一導電區；一第二功率電晶體，封裝於該第二容置區中，該第一功率電晶體的汲極電性連接至該第二導電區；以及一線路層，形成於該控制晶片、該第一功率電晶體的一第一主動面與該第二功率電晶體的一第二主動面上以電性連接該控制晶片、該第一功率電晶體與該第二功率電晶體；其中，該第一分隔板的端面、該第一功率電晶體的第一主動面與該第二功率電晶體的第二主動面共平面，該第一分隔板位於該第一功率電晶體與該第二功率電晶體之間，該第一功率電晶體的源極經由該第一分隔板與該第二導電區電性連接至該第二功率電晶體的汲極。
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