TW201816950A - 晶片封裝結構及其製造方法 - Google Patents
晶片封裝結構及其製造方法 Download PDFInfo
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- TW201816950A TW201816950A TW106135088A TW106135088A TW201816950A TW 201816950 A TW201816950 A TW 201816950A TW 106135088 A TW106135088 A TW 106135088A TW 106135088 A TW106135088 A TW 106135088A TW 201816950 A TW201816950 A TW 201816950A
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- reinforcing frame
- channel
- chip
- wafer
- disposed
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- 238000004519 manufacturing process Methods 0.000 title claims description 14
- 230000003014 reinforcing effect Effects 0.000 claims abstract description 62
- 229910000679 solder Inorganic materials 0.000 claims abstract description 22
- 239000010410 layer Substances 0.000 claims description 37
- 235000012431 wafers Nutrition 0.000 claims description 33
- 238000007789 sealing Methods 0.000 claims description 25
- 238000004806 packaging method and process Methods 0.000 claims description 22
- 238000000034 method Methods 0.000 claims description 17
- 239000012790 adhesive layer Substances 0.000 claims description 13
- 238000005192 partition Methods 0.000 claims description 11
- 230000002787 reinforcement Effects 0.000 claims description 10
- 239000000853 adhesive Substances 0.000 claims 1
- 230000001070 adhesive effect Effects 0.000 claims 1
- 239000008393 encapsulating agent Substances 0.000 abstract 2
- 230000002708 enhancing effect Effects 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 239000010949 copper Substances 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
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Abstract
晶片封裝結構包括重佈線路層、至少一晶片、補強框、密封體以及多個焊球。重佈線路層包括彼此相對的第一表面以及第二表面。晶片配置在第一表面上且與重佈線路層電性連接。補強框配置在第一表面上且包括至少一貫穿槽。晶片配置於貫穿槽中,且補強框剛性大於重佈線路層的剛性。密封體密封晶片以及補強框且覆蓋第一表面。焊球配置在第二表面上且與重佈線路層電性連接。
Description
本發明是有關於一種封裝結構及其製造方法,且特別是有關於一種晶片封裝結構及其製造方法。
現代電子裝置為了其應用(例如行動應用)而要求小尺寸、大記憶容量以及高效能。因此,納入於現代電子裝置(例如行動電子裝置)中的半導體晶片封裝亦必須具有小尺寸、大記憶容量以及高效能。
一般來說,印刷電路板(printed circuit board,PCB)包括通常由聚醯亞胺(polyimide)材料製成的絕緣基板以及通常由銅(Cu)製成的導電圖案。導電圖案可安置於基板的層之間或安置於基板的一表面上。在晶片封裝用於電子系統(例如行動電子裝置中的主板)中時,為達成接合目的,封裝可能會經受高溫製程。形成焊球或是將晶片封裝接合至電路板的高溫製程可能會因晶片封裝中各種構件之間的熱膨脹係數(coefficient of thermal expansion;CTE)的不匹配(mismatch)而導致封裝翹曲(warpage)。此種翹曲可能會造成晶片封裝與電路板之間的連接失敗(open connection failure)。除此之外,此種翹曲也會導致在安裝時抵靠在主板的焊球的高度不均勻,而造成接觸不良(contact failure)。
本發明提供一種晶片封裝結構及其製造方法,其能減少晶片封裝結構的翹曲,以提高晶片封裝結構的信賴度以及結構強度。
本發明提供一種晶片封裝結構,其包括重佈線路層、至少一晶片、補強框以及密封體。重佈線路層包括彼此相對的第一表面以及第二表面。晶片配置在第一表面上且與重佈線路層電性連接。補強框配置在第一表面上且包括至少一貫穿槽(through cavity)。晶片配置於貫穿槽中,且補強框的剛性(stiffness)大於重佈線路層的剛性。密封體密封晶片以及補強框且覆蓋第一表面。
在本發明的一實施例中,晶片包括主動表面以及配置在主動表面上的多個接墊,主動表面面向重佈線路層,且接墊安裝在重佈線路層上。
在本發明的一實施例中,黏著層包括焊膏(solder paste)或是晶粒貼合膜(die attach film;DAF)。
在本發明的一實施例中,補強框的材料包括金屬。
本發明提供一種晶片封裝結構的製造方法,其包括以下步驟。在載板上配置至少一晶片。在載板上配置補強框。補強框包括至少一貫穿槽,且晶片配置於貫穿槽中。形成密封體以密封晶片以及補強框並覆蓋載板。移除載板以暴露出密封體、晶片以及補強框的底表面。在密封體、晶片以及補強框的底表面上形成重佈線路層。補強框的剛性大於重佈線路層的剛性。
在本發明一實施例中,晶片藉由覆晶(flip-chip)接著技術安裝在載板上。
基於上述,本揭露的晶片封裝結構會經受高溫製程(例如在重佈線路層上形成焊球),而造成晶片封裝結構的翹曲。因此,在形成重佈線路層以及焊球之前,補強框被配置為環繞晶片。補強框的剛性大於重佈線路層的剛性,從而增強晶片封裝結構的剛性以及結構強度。除此之外,還能夠減少晶片封裝結構的翹曲,進而改善晶片封裝結構的信賴度。
為讓本發明的上述特徵和優點能更明顯易懂,下文特舉實施例,並配合所附圖式作詳細說明如下。
圖1至圖7繪示依照本發明一實施例的一種晶片封裝結構的製造方法。在本實施例中,一種晶片封裝結構的製造方法包括以下步驟。請參照圖1,在載板105上配置至少一晶片110(此處繪示一個晶片)。晶片110包括面向載板105的主動表面112以及配置在主動表面112上的多個接墊114。在本實施例中,晶片110藉由覆晶(flip-chip)接著技術安裝在載板105上,但本發明不限於此。
接著,請參照圖2以及圖3,在載板105上配置如圖3所示的補強框120。補強框120包括至少一貫穿槽(through cavity)122。如圖2所示,晶片110配置在貫穿槽122中。在本實施例中,補強框120可以更包括底表面S1以及至少一通道124。底表面S1與載板105接觸。通道124配置於補強框120的側壁128上。如圖3所示,通道124與貫穿槽122相通(communicate)。在本實施例中,補強框120的材料包括金屬,但本發明不限於此。
除此之外,在補強框120配置在黏著層160上之前,可以在載板105上配置黏著層160。亦即,黏著層160配置在載板105以及補強框120之間,以使得補強框120藉由黏著層160貼附在載板105上。黏著層160可包括焊膏(solder paste)或是晶粒貼合膜(die attach film;DAF)。
接著,請參照圖4,形成密封體130以密封晶片110以及補強框120並覆蓋載板105。在本實施例中,密封體130填入貫穿槽122以密封晶片,且密封體130可以由通道124從貫穿槽122中流出,以均勻的覆蓋載板105的頂表面。藉此,密封體130填入貫穿槽122以及通道124兩者。
接著,請參照圖5以及圖6,移除載板105以暴露出底表面S1(包括密封體130、晶片110以及補強框120被暴露出的表面)。在其他的實施例中,黏著層160可以被形成為覆蓋載板105的整個頂表面,以固定補強框120以及晶片110。如此一來,當載板105被移除時,底表面S1可以是平坦的表面(planar surface)。接著,圖5所示的結構可以被翻過來,以在底表面S1上形成重佈線路層140。在本實施例中,補強框120的剛性(stiffness)大於重佈線路層140的剛性。亦即,相較於重佈線路層140,補強框120較硬,以提供晶片封裝結構100的結構強度。
接著,請參照圖7,在重佈線路層140上形成多個焊球150。焊球150與重佈線路層140電性連接。在此時,晶片封裝結構100的製造過程已實質上完成。
在本實施例中,晶片封裝結構100會經受在重佈線路層140上形成焊球150及/或是將晶片封裝結構100接合至電路板的高溫製程。此高溫製程可能會因晶片封裝結構100中各種構件之間的熱膨脹係數(coefficient of thermal expansion;CTE)的不匹配(mismatch)而導致晶片封裝結構100的翹曲(warpage)。因此,在形成焊球150之前,補強框120被配置為環繞晶片100,從而增強晶片封裝結構100的剛性以及減少由高溫製程所造成的翹曲。
從結構的角度來看,請參照圖7,由以上所揭露的方法所製造的晶片封裝結構100包括重佈線路層140、晶片110、補強框120、密封體130以及多個焊球150。重佈線路層140包括彼此相對的第一表面142以及第二表面144。晶片110配置在第一表面142上且與重佈線路層140電性連接。補強框120配置在第一表面142上且包括貫穿槽122。晶片110配置在貫穿槽122中,且補強框120的剛性大於重佈線路層140的剛性。密封體130密封晶片以及補強框120且覆蓋第一表面142。焊球150配置在第二表面144上且與重佈線路層140電性連接。
在本實施例中,補強框120可以更包括通道124。通道124形成於補強框120的側壁。通道124與貫穿槽122相通。底表面S1為面向重佈線路層140的表面。補強框120的底表面可更包括黏著層160,以使得補強框120可以藉由黏著層160黏著至載板105。黏著層160可包括焊膏或是晶粒貼合膜。在其他實施例中,補強框120的底表面、晶片110的主動表面以及密封體130可以彼此相互共面(coplanar)。因此,重佈線路層140可以直接形成在補強框120的底表面、晶片110的主動表面以及密封體130上。
圖8繪示依照本發明一實施例的補強框。圖9繪示依照本發明一實施例的晶片封裝結構。值得注意的是,圖9所示的晶片封裝結構100a包括與圖7所示的晶片封裝結構100相同或相似的多個特徵。為了清楚以及簡單起見,將會省略關於相同或相似的特徵的詳細描述,且相同或相似的構件由相同或相似的標號表示。以下將描述圖9所示的晶片封裝結構100a與圖7所示的晶片封裝結構100的主要差異點。
在本實施例中,晶片封裝結構100a可以包括多個晶片110,且補強框120可以對應地包括多個貫穿槽122。晶片110分別配置於貫穿槽122中。除此之外,補強框120可以更包括多個通道124以及至少一分隔壁(division wall)126。分隔壁126配置於任兩相鄰的貫穿槽122之間以定義貫穿槽122。通道124配置於補強框120的側壁128及/或分隔壁126上。通道124與貫穿槽122相通。在本實施例中,至少一個通道124配置於分隔壁126上,以使得貫穿槽122能夠藉由在分隔壁126上的通道124而彼此相通。藉此,當形成密封體130以密封晶片110時,密封體130可以藉由在分隔壁126上的通道124而流入貫穿槽122以密封每一晶片110。並且,密封體130可以由通道124從貫穿槽122中流出,以均勻的覆蓋載板105的頂表面。除此之外,由於密封體130藉由通道124包裹著(wrap around)補強框120,補強框120能夠被堅固地且安全地鎖在密封體130中,以改善晶片封裝結構100、100a的信賴度。
綜上所述,本揭露的晶片封裝結構會經受高溫製程(例如在重佈線路層上形成焊球)。此高溫製程可能會造成晶片封裝結構的翹曲。因此,在形成焊球之前,補強框被配置為環繞晶片。補強框的剛性大於重佈線路層的剛性,從而增強晶片封裝結構的剛性以及結構強度。據此,晶片封裝結構的翹曲能夠被減少且晶片封裝結構的信賴度能夠被改善。
雖然本發明已以實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明的精神和範圍內,當可作些許的更動與潤飾,故本發明的保護範圍當視後附的申請專利範圍所界定者為準。
100、100a‧‧‧晶片封裝結構
105‧‧‧載板
110‧‧‧晶片
112‧‧‧主動表面
114‧‧‧接墊
120‧‧‧補強框
122‧‧‧貫穿槽
124‧‧‧通道
126‧‧‧分隔壁
128‧‧‧側壁
130‧‧‧密封體
140‧‧‧重佈線路層
142‧‧‧第一表面
144‧‧‧第二表面
150‧‧‧焊球
160‧‧‧黏著層
S1‧‧‧底表面
圖1至圖7繪示依照本發明一實施例的一種晶片封裝結構的製造方法。 圖8繪示依照本發明一實施例的補強框。 圖9繪示依照本發明一實施例的晶片封裝結構。
Claims (10)
- 一種晶片封裝結構,包括: 重佈線路層,包括彼此相對的第一表面以及第二表面; 至少一晶片,配置在所述第一表面上且與所述重佈線路層電性連接; 補強框,配置在所述第一表面上且包括至少一貫穿槽(through cavity),其中所述晶片配置於所述貫穿槽中,且所述補強框的剛性(stiffness)大於所述重佈線路層的剛性;以及 密封體,密封所述晶片以及所述補強框且覆蓋所述第一表面。
- 如申請專利範圍第1項所述的晶片封裝結構,更包括多個焊球配置在所述第二表面上,且所述焊球與所述重佈線路層電性連接。
- 如申請專利範圍第1項所述的晶片封裝結構,其中所述補強框包括至少一通道,所述通道形成於所述補強框的至少一側壁上,所述通道與所述貫穿槽相通(communicate),且所述密封體填入所述貫穿槽以及所述通道。
- 如申請專利範圍第1項所述的晶片封裝結構,其中所述補強框的底表面更包括黏著層。
- 如申請專利範圍第1項所述的晶片封裝結構,其中所述至少一晶片的數量為多個晶片,所述至少一貫穿槽的數量為多個貫穿槽,所述多個晶片分別配置於所述多個貫穿槽中,所述補強框更包括多個通道以及至少一分隔壁(division wall),所述多個通道配置在所述補強框的多個側壁上,所述多個通道與所述多個貫穿槽相通,所述分隔壁配置於任兩相鄰的所述貫穿槽之間以定義所述貫穿槽,且所述至少一通道配置於所述分隔壁上。
- 一種晶片封裝結構的製造方法,包括: 在載板上配置至少一晶片; 在所述載板上配置補強框,其中所述補強框包括至少一貫穿槽,且所述晶片配置於所述貫穿槽中; 形成密封體以密封所述晶片以及所述補強框並覆蓋所述載板; 移除所述載板以暴露出所述密封體、所述晶片以及所述補強框的底表面;以及 在所述密封體、所述晶片以及所述補強框的所述底表面上形成重佈線路層,其中所述補強框的剛性大於所述重佈線路層的剛性。
- 如申請專利範圍第6項所述的晶片封裝結構的製造方法,更包括: 在所述重佈線層上形成多個焊球,所述焊球與所述重佈線路層電性連接。
- 如申請專利範圍第6項所述的晶片封裝結構的製造方法,其中所述補強框包括至少一通道,所述通道形成於所述補強框的至少一側壁上,所述通道與所述貫穿槽相通,且所述密封體填入所述貫穿槽以及所述通道。
- 如申請專利範圍第6項所述的晶片封裝結構的製造方法,其中在所述載板上配置所述補強框的所述步驟包括: 在所述載板上配置黏著層;以及 在所述黏著層上配置所述補強框,以使得所述補強框貼附在所述載板上。
- 如申請專利範圍第6項所述的晶片封裝結構的製造方法,其中所述至少一晶片的數量為多個晶片,所述至少一貫穿槽的數量為多個貫穿槽,所述多個晶片分別配置於所述多個貫穿槽中,所述補強框更包括多個通道以及至少一分隔壁,所述多個通道配置在所述補強框的多個側壁上,所述多個通道與所述多個貫穿槽相通,所述分隔壁配置於任兩相鄰的所述貫穿槽之間以定義所述貫穿槽,且所述至少一通道配置於所述分隔壁上。
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