TW201604941A - 半導體裝置與其形成方法及鰭狀場效電晶體裝置 - Google Patents

半導體裝置與其形成方法及鰭狀場效電晶體裝置 Download PDF

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TW201604941A
TW201604941A TW104123052A TW104123052A TW201604941A TW 201604941 A TW201604941 A TW 201604941A TW 104123052 A TW104123052 A TW 104123052A TW 104123052 A TW104123052 A TW 104123052A TW 201604941 A TW201604941 A TW 201604941A
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gate
isolation
height
gates
fins
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TW104123052A
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TWI570785B (zh
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廖忠志
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台灣積體電路製造股份有限公司
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  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

本發明提供之半導體結構包括：一或多個鰭狀物，形成於基板上並沿著第一方向延伸；一或多個閘極，形成於鰭狀物上並沿著第二方向延伸，且第一方向實質上垂直於第二方向，其中閘極包含第一隔離閘極與至少一功能閘極；多個源極/汲極結構，形成於每一閘極的兩側上；以及層間介電(ILD)層，形成於源極/汲極結構上，且層間介電層與第一隔離閘極具有共平面的上表面。第一隔離閘極的第一高度大於功能閘極的第二高度。

Description

半導體裝置與其形成方法及鰭狀場效電晶體裝置
本發明關於鰭狀場效電晶體的佈局設計，更特別關於分隔相鄰電路區之隔離閘極與其形成方法。
半導體積體電路(IC)產業呈指數成長。IC材料與設計的技術進步，使每一代的IC比前一代的IC更小且其電路更複雜。新一代的IC具有較大的功能密度(比如固定晶片面積中的內連線元件數目)，與較小的尺寸(比如製程形成的最小構件或連線)。製程尺寸縮小往往有利於增加製程效率並降低相關成本。
製程尺寸縮小會增加製程複雜度，但製程尺寸縮小的優點顯而易見，因此需要更小的IC製程。舉例來說，三維電晶體可用以取代平面電晶體。雖然現有的半導體裝置與其形成方法適用於特定目的，但仍無法適用於所有領域。舉例來說，將三維奈米結構導入閘極通道對半導體裝置製程發展仍屬挑戰。此領域仍需改良。
本發明一實施例提供之半導體裝置，包括：一或多個鰭狀物，形成於基板上並沿著第一方向延伸；一或多個閘極，形成於鰭狀物上並沿著第二方向延伸，且第一方向實質上 垂直於第二方向，其中閘極包含第一隔離閘極與至少一功能閘極；多個源極/汲極結構，形成於每一閘極的兩側上；以及層間介電層，形成於源極/汲極結構上，且層間介電層與第一隔離閘極具有共平面的上表面，其中第一隔離閘極的第一高度大於功能閘極的第二高度。
本發明一實施例提供之鰭狀場效電晶體裝置，包括：基板，包括第一主動區與第二主動區在第一方向彼此相隔；第一組鰭狀物設置於第一主動區中，以及第二組鰭狀物設置於第二主動區中，第一組鰭狀物與第二組鰭狀物各自沿著第二方向延伸，且第一方向實質上垂直於第二方向；一或多個閘極，沿著第一方向延伸於第一主動區與第二主動區上，閘極包括第一隔離閘極與至少一功能閘極；多個側壁間隔物，形成於閘極的側壁上；多個源極/汲極結構，形成於側壁間隔物的側壁上；以及層間介電層，形成於源極/汲極結構上，且層間介電層與閘極具有共平面的上表面，其中第一隔離閘極具有第一高度，形成於第一隔離閘極之側壁上的側壁間隔物具有第二高度，且第一高度實質上大於第二高度。
本發明一實施例提供之半導體裝置的形成方法，包括：提供裝置前驅結構，裝置前驅結構包括：基板，包括第一主動區與第二主動區在第一方向彼此相隔；第一組鰭狀物設置於第一主動區中，以及第二組鰭狀物設置於第二主動區中，第一組鰭狀物與第二組鰭狀物各自沿著第二方向延伸，且第一方向實質上垂直於第二方向；以及一或多個閘極，各自沿著第一方向延伸於第一主動區與第二主動區上，閘極包括多晶閘 極，其中多晶閘極設置以分隔第一電路與第二電路；沉積層間介電層於基板上；移除多晶閘極以形成溝槽；以層間介電層作為蝕刻遮罩單元，使溝槽凹陷至基板中；以及沉積一或多個材料層於凹陷的溝槽中，以形成隔離閘極於第一電路與第二電路之間。
A-A、B-B‧‧‧切線
d1、d2‧‧‧深度
h1、h2、h3、h4、hf‧‧‧高度
100、400‧‧‧設計佈局
102‧‧‧PMOS
104‧‧‧NMOS
106‧‧‧第一主動區
106-1、106-2、106-3、108-1、108-2、108-3‧‧‧鰭狀線路
108‧‧‧第二主動區
110、111、112、113、114、115‧‧‧閘極
120、121、123、124、126、127‧‧‧接點
122、125‧‧‧長接點
128、129、130‧‧‧閘極接點
131‧‧‧第一電路
132‧‧‧第二電路
192‧‧‧第一方向
194‧‧‧第二方向
200、650‧‧‧FinFET裝置
202‧‧‧基板
204‧‧‧掺雜區
206‧‧‧隔離區
208‧‧‧源極/汲極結構
212‧‧‧介電層
216、216a、216b‧‧‧側壁間隔物
218‧‧‧ILD層
220、222‧‧‧溝槽
224、226、228‧‧‧隔離閘極
300‧‧‧重點結構
302、304、306‧‧‧暴露區
500‧‧‧方法
502、504、506、508、510‧‧‧步驟
第1A、3A、4A、與5A圖係本發明某些實施例中，FinFET裝置於不同製程階段中的設計佈局上視圖。
第1B、5B、與6B圖係本發明某些實施例中，分別對應第1A、5A、與6A圖中FinFET裝置沿著切線A-A的剖視圖。
第1C、2A、3B、4B、與5C圖係本發明某些實施例中，第1A、3A、4A、與5A圖中的FinFET裝置之重點結構的放大上視圖。
第1D、2B、3C、4C、與5D圖係本發明某些實施例中，分別對應第1C、2A、3B、4B、與5C圖中的FinFET裝置之重點結構沿著切線A-A的剖視圖。
第1E、2C、3D、4D、與5E圖係本發明某些實施例中，分別對應第1C、2A、3B、4B、與5C圖中的FinFET裝置之重點結構沿著切線B-B的剖視圖。
第6A圖係本發明某些實施例中，FinFET裝置之設計佈局的上視圖。
第6B圖係本發明某些實施例中，對應第6A圖中的FinFET裝置沿著切線A-A的剖視圖。
第7圖係本發明多種實施例中，製作FinFET裝置的方法之流程圖。
下述內容提供的不同實施例可實施本發明的不同結構。特定構件與排列的實施例係用以簡化本發明而非侷限本發明。舉例來說，形成第一構件於第二構件上的敘述包含兩者直接接觸，或兩者之間隔有其他額外構件而非直接接觸。此外，本發明之多種實例將重複標號及/或符號以簡化並清楚說明。不同實施例中具有相同標號的元件並不必然具有相同的對應關係及/或排列。
此外，空間性的相對用語如「下方」、「其下」、「較下方」、「上方」、「較上方」、或類似用語可用於簡化說明某一元件與另一元件在圖示中的相對關係。空間性的相對用語可延伸至以其他方向使用之元件，而非侷限於圖示方向。元件亦可轉動90°或其他角度，因此方向性用語僅用以說明圖示中的方向。
本發明關於但不限於金氧半場效電晶體(MOSFET)，比如鰭狀場效電晶體(FinFET)裝置。舉例來說，FinFET裝置可為互補式金氧半(CMOS)裝置，其包含p型金氧半(PMOS)FinFET裝置與n型金氧半(NMOS)FinFET裝置。後續內容將繼續說明本發明多種實施例之FinFET裝置。然而應理解的是，本發明並不限於特定型態的裝置，除非特別記載於申請專利範圍中。
第1A圖係本發明某些實施例中，FinFET裝置之設 計佈局100的上視圖。如第1A圖所示，設計佈局100包含PMOS 102與NMOS 104。PMOS係形成於n型井區中，而NMOS 104係形成於p型井區中。PMOS 102可設置於第一主動區106上，而NMOS 104可設置於第二主動區108上。如第1A圖所示，第一主動區106可包含一或多個主動鰭狀線路，比如鰭狀線路106-1、106-2、與106-3。同樣地，第二主動區108亦可包含一或多個主動鰭狀線路，比如鰭狀線路108-1、108-2、與108-3。一或多個鰭狀線路設置以沿著第一方向192延伸。
如第1A圖所示，一或多個閘極110至115係設置以沿著第二方向194延伸，且形成於第一主動區106與第二主動區108上。一或多個閘極110至115可設置以互相平行。第二方向194可實質上垂直於第二方向192。在某些實施例中，一或多個閘極可與主動區一同設置，以形成單元中的一或多個對應的上拉(PU)裝置、下拉(PD)裝置、與通閘(PG)裝置。如第1A圖所示，每一閘極的掺雜區(如源極區與汲極區)可電性與物理地連接至相鄰閘極的掺雜區。舉例來說，藉由共用閘極111與閘極112之間的主動區中的共同源極區，閘極111之源極可電性與物理地連接至閘極112之源極。
如第1A圖所示，多種接點120、121、123、124、126、與127可形成於掺雜區上以電性連接掺雜區。舉例來說，接點120可用以使第一主動區106中，閘極110其掺雜汲極區電性連接至閘極111其掺雜汲極區。接點121可用以使第二主動區108中，閘極110其掺雜汲極區電性連接至閘極111其掺雜汲極區。接點123可用以使第一主動區106中，閘極112其掺雜汲極 區電性連接至閘極113其掺雜汲極區。接點124可用以使第一主動區106中，閘極112其掺雜汲極區電性連接至閘極113其掺雜汲極區。接點126可用以使第一主動區106中，閘極114其掺雜汲極區電性連接至閘極115其掺雜汲極區。接點127可用以使第二主動區108中，閘極114其掺雜汲極區電性連接至閘極115其掺雜汲極區。
一或多個長接點可設置以沿著第二方向194延伸，並延伸出第一主動區106與第二主動區108。長接點沿著第一方向192的尺寸為第一尺寸，沿著第二方向194的尺寸為第二尺寸，且第一尺寸實質上短於第二尺寸。一或多個長接點可用以電性連接第一主動區106及第二主動區108上相鄰閘極之掺雜區。舉例來說，長接點122可用以使延伸於第一主動區106與第二主動區108上的閘極111其掺雜源極區電性連接至閘極112其掺雜源極區。長接點125可用以使延伸於第一主動區106與第二主動區108上的閘極113其掺雜源極區電性連接至閘極114其掺雜源極區。
一或多個閘極接點128至130亦可形成於對應的閘極上，用以使閘極佈線至對應的金屬佈線(未圖示)。金屬佈線可形成於閘極上的一或多個金屬層(未圖示)中。
如第1A圖所示，設計佈局100可包含超過一個電路，比如第一電路131與第二電路132。在某些實施例中，隔離結構(如虛置的閘極113)可形成於第一電路131與第二電路132之間。
第1B圖係本發明某些實施例中，沿著第1A圖中切 線A-A的FinFET裝置200之剖視圖。如第1B圖所示，FinFET裝置200包含基板202。基板202可包含基體矽。在其他實施例中，半導體元素如結晶結構的矽或鍺亦可包含於基板202中。基板202亦可包含半導體化合物如矽鍺(SiGe)、碳化矽(SiC)、砷化鎵(GaAs)、磷化鎵(GaP)、磷化銦(InP)、砷化銦(InAs)、及/或銻化銦(InSb)、或上述之組合。可能的基板202亦可包含絕緣層上半導體基板如絕緣層上矽(SOI)、絕緣層上矽鍺(SGOI)、或絕緣層上鍺(GOI)等基板。舉例來說，SOI基板的形成方法可採用佈植氧隔離(SIMOX)、晶圓接合、及/或其他合適方法。
如第1B圖所示，多種掺雜區204亦可包含於基板202中，端視設計需求為何。掺雜區可掺雜p型掺質如硼(B)或氟化硼(BF3)。掺雜區亦可掺雜n型掺質如磷(P)或砷(As)。掺雜區亦可掺雜p型掺質與n型掺質的組合。掺雜區可直接形成於基板202上如p型井結構、n型井結構、或雙井結構，或採用隆起結構。
如第1B圖所示，FinFET裝置200可包含一或多個隔離區206。一或多個隔離區206係形成於基板202上，以隔離主動區。舉例來說，每一隔離區206使基板202中相鄰的掺雜區204互相隔離。一或多個隔離區206之形成方法可採用習知的隔離技術(如淺溝槽隔離(STI))以定義並電性隔離一或多個主動鰭狀線路。在某些實例中，隔離區206可包含氧化矽、氮化矽、氮氧化矽、氣隙、其他合適材料、或上述之組合。隔離區206可由任何合適製程形成。在某些實例中，STI的形成方法包括光微影製程、蝕刻溝槽(比如乾蝕刻及/或濕蝕刻)於基板202 中，以及將一或多種介電材料填入溝槽中(比如化學氣相沉積製程)以形成隔離區206。填滿的溝槽可具有多層結構如熱氧化襯墊層上填有氮化矽或氧化矽。接著可進行化學機械研磨(CMP)製程，以移除多餘的介電材料並平坦化隔離區206的上表面。
如第1B圖所示，一或多個閘極110至115可形成於第一主動區106、第二主動區108、與掺雜區204上。一或多個閘極110至115可包含功能閘極及/或虛置多晶閘極。舉例來說，閘極113可為虛置多晶閘極，設置以隔離第一電路131與第二電路132。虛置之多晶的閘極113可包含多晶矽。閘極110至112與114至115可為功能閘極。一或多個閘極110至115之形成方法可包含沉積、微影圖案化、及/或蝕刻製程。沉積製程可包含化學氣相沉積(CVD)、物理氣相沉積(PVD)、原子層沉積(ALD)、其他合適方法、及/或上述之組合。
如第1B圖所示，側壁間隔物216可沿著每一閘極110至115形成。側壁間隔物216可包含介電材料如氧化矽、氮化矽、碳化矽、氮氧化矽、或上述之組合。側壁間隔物216亦可包含多個層狀物。用以形成側壁間隔物216的方法通常包含沉積介電材料於每一閘極110至115上。接著可非等向回蝕刻介電材料。回蝕刻製程包含多重蝕刻步驟以達蝕刻選擇性、製程彈性、及所需的過蝕刻控制。在某些實施例中，一或多個材料層(未圖示)如界面層，亦可形成於閘極與對應的側壁間隔物之間。一或多個材料層可包含界面層及/或高介電常數之介電層。
如第1B圖所示，一或多個源極/汲極結構208可形 成於基板202上。在某些實施例中，一或多個源極/汲極結構208之形成製程可包含凹陷步驟以形成源極/汲極溝槽，再沉積形成一或多個源極/汲極結構208於源極/汲極溝槽中。在某些實施例中，一或多個源極/汲極結構208的形成方法可為磊晶成長半導體材料層於凹陷的源極/汲極溝槽中。在磊晶成長一或多個源極/汲極結構208時可臨場佈植。舉例來說，磊晶成長的SiGe源極/汲極結構可掺雜硼。磊晶成長的矽源極/汲極結構可掺雜碳以形成矽：碳(Si：C)的源極/汲極結構，掺雜磷以形成矽：磷(Si：P)的源極/汲極結構，或掺雜碳與磷以形成矽碳磷(SiCP)的源極/汲極結構。在某些實施例中，可進行佈植製程(如接面佈植製程)以掺雜源極/汲極結構。一或多個回火製程可用以活化源極/汲極磊晶結構。回火製程可包含快速熱回火(RTA)及/或雷射回火製程。在某些實施例中，一源極/汲極結構為源極區，而其他源極/汲極結構為汲極區。相鄰的源極/汲極結構208之間隔有閘極，比如第1A至1B圖所示之閘極110至115的對應閘極。如第1B圖所示，一或多個接點120至126係形成於一或多個源極/汲極結構208上。
為了進一步清楚說明，第1C圖為本發明某些實施例中，第1A至1B圖中的FinFET裝置之重點結構300其放大上視圖。如第1C圖所示，虛置之多晶的閘極113係形成於主動的鰭狀線路106-3上。第1D圖係本發明某些實施例中，第1C圖之重點結構300沿著切線A-A的剖視圖。第1E圖係本發明某些實施例中，第1C圖之重點結構300沿著切線B-B的剖視圖。
在本發明某些實施例中，ILD(層間介電)層218可 形成於源極/汲極結構208上，如第2A至2C圖所示。ILD層218可包含氧化矽、氮氧化矽、或其他合適的介電材料。ILD層218可包含單層或多層。ILD層218的形成方法可為合適技術如CVD、ALD、旋轉塗佈介電層如旋轉塗佈玻璃(SOG)。在形成ILD層218後，可進行化學機械研磨(CMP)製程以移除多餘的ILD層218，並平坦化ILD層218的上表面。
如第3A至3D圖所示，用於隔離第一電路131與第二電路132之間的虛置之多晶的閘極113移除後，即形成溝槽220。虛置之多晶的閘極113其移除方法可採用任何合適的微影與蝕刻製程。蝕刻製程可包含選擇性濕蝕刻或選擇性乾蝕刻，使虛置之多晶的閘極113與掺雜區204之間具有合適的蝕刻選擇性。在移除虛置之多晶的閘極113後，將露出第一主動區106與第二主動區108中的一或多個主動鰭狀線路。在某些實施例中，微影製程可包含形成光阻層、曝光光阻層至一圖案、進行曝光後烘烤製程、以及顯影光阻以形成包含光阻的遮罩單元。如第3A圖所示，遮罩單元可搭配任何合適的乾蝕刻及/或濕蝕刻方法，以露出包含虛置之多晶的閘極113之暴露區302。
如第4A至4D圖所示，在使暴露區302中的溝槽220進一步凹陷以形成溝槽222之製程中，ILD層218可作為遮罩單元。在某些實施例中，在使溝槽220凹陷之製程中，保留的側壁間隔物216亦可作為遮罩單元。上述凹陷步驟可視作自我對準的蝕刻製程。在某些實施例中，自我對準的蝕刻製程所形成的溝槽為V型的溝槽222，如第4C圖所示。溝槽220所露出的部份主動之鰭狀線路106-3將被移除，如第4A至4B圖所示。如地 4C圖所示，源極/汲極結構208之上表面與凹陷之V型的溝槽222之下表面之間的深度d1，可介於約50nm至約200nm之間。在此實施例中，遮罩單元的暴露區面積實質上大於虛置多晶閘極的面積，且遮罩單元可用於蝕刻基板以形成溝槽的步驟中。舉例來說，第1A、3A、及/或4A圖之暴露區302之面積，實質上大於虛置之多晶的閘極113及/或溝槽220之面積。這可使微影具有較寬鬆的製程條件。
如第5A至5D圖所示，一或多個材料層可沉積於溝槽222中，以形成隔離閘極224。隔離閘極224之V型底部順應性地位於V型的溝槽222上，如第5B與5D圖所示。如第5B圖所示，源極/汲極結構208之頂部與隔離閘極224之底部之間的深度d2可介於約50nm至約200nm之間。此外，隔離結構224具有高度。在第5B與5D圖所示的某些實施例中，沉積於溝槽222中的一或多個材料層可包含介電層212與隔離閘極224。在某些實施例中，介電層212可包含界面層(IL)及/或高介電常數(HK)介電層，其形成於溝槽中並順應性地位於溝槽222之下表面上。界面層的沉積方法可為任何合適方法如ALD、CVD、及/或PVD。界面層可包含氧化矽或氮氧化矽。HK介電層可沉積於界面層上，其沉積方法可為任何合適技術如ALD、CVD、有機金屬CVD、PVD、或上述之組合。HK介電層可包含下列材料中的一或多者：氧化鉿、氧化鉭、與氧化鋁，及/或其他合適材料。
如第5A至5E圖所示，隔離閘極224可包含一或多個金屬閘極(MG)層，比如功函數金屬層、低電阻金屬層、襯墊層、濕潤層、及/或黏著層。在某些實施例中，功函數金屬層可包 含下列材料中的一或多者：錫、氮化鉭、鈦鋁、鉭鋁、含鈦材料、含鉭材料、含鋁材料、含鎢材料、鈦矽、鎳矽、與鉑矽。在某些實施例中，低電阻金屬層可包含下列材料中的一或多者：具有矽化物的多晶矽、含鋁材料、含銅材料、含鎢材料、含鈦材料、含鉭材料、氮化鈦、氮化鉭、鈦鎢、與鈦鋁。MG層的形成方法可為ALD、PVD、CVD、或其他合適製程。可進行CMP製程以移除多餘的MG層，並使ILD層218與隔離閘極224具有實質上平坦的上表面。裝置的功函數取決於功函數金屬層，其可介於約4eV至約5eV之間。介電層212可讓填入溝槽222中的隔離閘極具有足夠的絕緣性質。在形成介電層212與隔離閘極224於溝槽222中後，可使第一電路131與第二電路132彼此充份的電性隔離。
在某些實施例中，介電層212及/或隔離閘極224的材料、形成方法、與佈局，亦可設計以施加控制偏壓至隔離閘極224，以有效的隔離第一電路131與第二電路132。
在某些實施例中，亦可將介電層填入溝槽222中。介電層的形成方法及/或材料可與前述之介電層212類似。舉例來說，介電層可包含下列材料中的一或多者：氧化鑭、氧化鋁、氧化鋯、氧化鈦、氧化鉭、氧化釔、氧化鍶鈦(STO)、氧化鉿、氧化鋇鈦(BTO)、氧化鋇鋯、氧化鉿鋯、氧化鉿鑭、氧化鉿矽、氧化鑭矽、氧化鋁矽、氧化鉿鉭、氧化鉿鈦、氧化(鋇，鍶)鈦(BST)、氧化鋁、氮化矽、與氮氧化矽(SiON)。用以填入溝槽222的介電層可包含任何合適材料如氧化矽、氮化矽、碳化矽、及/或氮氧化矽。在某些實例中，介電層可沉積以完全填滿溝 槽222，以提供足夠的電性隔離性質。在某些實施例中，當隔離閘極224包含填入溝槽222中的介電材料時，用以填入溝槽222之介電材料不同於沿著隔離閘極224形成之側壁間隔物216。在某些實施例中，介電層可部份填入溝槽222中。舉例來說，溝槽222的較下部份可填有介電層，而溝槽222的較上部份可填有介電層212與隔離閘極224。填入溝槽222之較下部份的介電層，其功能與分隔第一電路131與第二電路132之隔離區(STI)類似。介電層的形成方法可為ALD、PVD、CVD、或其他合適製程。
如第5A圖所示，在形成隔離閘極224後，FinFET裝置200包含隔離閘極224以分隔第一電路131與第二電路132。閘極110、111、112、114、與115為功能閘極，並包含功能金屬閘極。在某些實施例中，功能閘極可包含與隔離閘極不同的材料。如第5B與5D圖所示，隔離閘極224的高度h1實質上大於沿著隔離閘極224形成之每一側壁間隔物216的高度h2。隔離閘極224的高度h1亦實質上大於功能閘極的高度hf。此外，隔離閘極224延伸至掺雜區204中，且隔離閘極224的下表面低於功能閘極如閘極110、111、112、114、與115的下表面。隔離閘極224的材料可與功能閘極的材料相同或不同。舉例來說，隔離閘極224中的材料包含純介電材料如氧化矽、氮氧化矽、氮化矽、高介電常數介電物、或上述之組合。在此實例中，製程可為：1.移除隔離閘極多晶矽及蝕刻溝槽；2.沉積介電層(再填入隔離閘極)；以及 3.形成功能閘極(可進一步包含移除多晶閘極，與形成高介電常數閘極介電物、功函數金屬、與低電阻金屬)。
第6A圖係本發明某些實施例中，FinFET裝置之設計佈局400的上視圖。第6B圖係本發明某些實施例中，沿著第6A圖中切線A-A的FinFET裝置650之剖視圖。在某些實施例中，亦可移除位於主動鰭狀線路邊緣的一或多個閘極(比如第1A圖之閘極110及/或閘極115)以形成對應的一或多個溝槽，且上述步驟可採用ILD層及/或閘極側壁上的側壁間隔物作為遮罩單元。介電材料(或介電材料與金屬材料)可用以填入一或多個溝槽，以形成隔離閘極如位於主動鰭狀線路邊緣的隔離閘極226及/或228。隔離閘極226及/或228的形成製程及/或材料，可與前述之隔離閘極224的形程製程及/或材料實質上類似。如第6A圖所示，位於主動鰭狀線路邊緣之隔離閘極226的形成製程，可包含採用暴露區304之面積實質上大於閘極110之面積的遮罩。同樣地，位於主動鰭狀線路邊緣之隔離閘極228的形成製程，可包含採用暴露區306之面積實質上大於閘極115之面積的遮罩。
如第6A至6B圖所示，FinFET裝置650包含隔離閘極224以分隔第一電路131與第二電路132，以及隔離閘極226與228位於主動鰭狀線路的邊緣。閘極111、112、與114為功能閘極，其包含功能金屬閘極。在第6B圖所示的某些實施例中，隔離閘極224的高度h1實質上大於沿著隔離閘極224形成的每一側壁間隔物216的高度h2。側壁間隔物216與位於主動鰭狀線路邊緣之隔離閘極226及228，可具有不對稱的結構如第6B圖所 示。舉例來說，形成於隔離閘極226或228外側之側壁間隔物216a與隔離結構226或228之外側部份可具有高度h3，形成於隔離結構226或228內側之側壁間隔物216b與隔離結構或228之內側部份可具有高度h4，而高度h3實質上大於高度h4。此外，隔離閘極226或228之底部可低於功能閘極如閘極111與114的底部，並高於隔離閘極224的底部。
第7圖係本發明多種實施例中，用以製作FinFET裝置的方法500其流程圖。方法500包含：步驟502提供MOSFET裝置的前驅結構，步驟504沉積ILD層於源極/汲極結構上，步驟506移除相鄰電路之間的虛置多晶閘極以形成溝槽，步驟508採用ILD層作為遮罩單元進行使溝槽凹陷的製程，以及步驟510沉積一或多個材料層以形成隔離閘極。應理解的是，在第7圖之方法500之前、之中、與之後可進行額外製程，且某些其他製程可簡述如下。
在步驟502中，提供MOSFET裝置前驅結構如FinFET裝置200的前驅結構。在某些實施例中，MOSFET裝置前驅結構包含基板，以及一或多個鰭狀物形成於基板上的第一主動區與第二主動區中。一或多個鰭狀物之間可隔有一或多個隔離區。一或多個閘極可形成於一或多個鰭狀物上，並延伸於第一主動區與第二主動區上。一或多個閘極可沿著第一方向沿伸，而一或多個鰭狀物可沿著第二方向延伸，且第一方向垂直於第二方向。源極/汲極結構可形成於MOSFET裝置前驅結構的源極/汲極區中。
在步驟504中，ILD層係沉積於鰭狀物的表面上。 ILD層可包含氧化矽、氮氧化矽、或其他合適的介電材料。ILD層可包含單層或多層。ILD層之形成方法可為合適技術如CVD、ALD、或旋轉塗佈介電層如SOG。可進行CMP製程使ILD層具有平坦的上表面。
在步驟506中，可移除虛置多晶閘極以形成溝槽於兩個相鄰的電路之間。移除虛置多晶閘極的方法可為任何合適微影與蝕刻製程。蝕刻製程可包含選擇性濕蝕刻或選擇性乾蝕刻。在移除虛置多晶閘極後，可露出主動區中的一或多個主動鰭狀線路。在某些實施例中，微影製程可包含形成光阻層、曝光光阻層至一圖案、進行曝光後烘烤製程、以及顯影光阻以形成包含光阻的遮罩單元。如第3A圖所示，遮罩單元可搭配任何合適的乾蝕刻及/或濕蝕刻方法，以露出包含虛置之多晶的閘極113之暴露區302。遮罩單元的面積可實質上大於虛置多晶閘極的面積。
在步驟508中，ILD層218可作為使溝槽進一步凹陷的蝕刻遮罩單元。在使溝槽凹陷之製程中，保留的側壁間隔物亦可作為遮罩單元。以第4A至4B圖為例，溝槽220中露出的部份主動之鰭狀線路106-3將被移除。在此實施例中，遮罩單元的暴露區面積實質上大於虛置多晶閘極的面積，且遮罩單元可用於蝕刻基板以形成溝槽的步驟中。
在步驟510中，可沉積一或多個材料層於凹陷的溝槽中以形成隔離結構於兩個相鄰的電路之間。在某些實施例中，隔離閘極可包含界面層/高介電常數介電層/金屬閘極(IL/HK/MG)的多層結構。在某些實施例中，隔離閘極可包含介 電層完全填入凹陷的溝槽。在某些實施例中，隔離閘極可包含介電材料填入凹陷的溝槽其較下部份，以及IL/HK/MG結構填入凹陷的溝槽其較上部份。隔離閘極可形成以電性隔離兩個相鄰的電路。一或多個材料層的形成方法可為ALD、PVD、CVD、或其他合適製程。
然而應理解的是，本發明並不限於特定種類的裝置，除非特別記載於申請專利範圍中。舉例來說，本發明亦可用於其他MOSFET裝置。亦應理解的是，在上述方法之前、之中、或之後可進行額外步驟。在本發明其他實施例中，上述某些步驟可取代為其他步驟甚至省略。
上述實施例描述MOSFET裝置的結構與其形成方法，並採用自我對準蝕刻製程以形成隔離結構。上述隔離結構可提供足夠的電性隔離於相鄰的電晶體之間。上述機制關於採用保留的ILD層及側壁間隔物作為蝕刻遮罩單元，以形成MOSFET裝置中的溝槽。接著可沉積一或多個材料層填入溝槽中，以提供足夠的電性隔離於相鄰的電路之間。上述機制提供製程條件較寬鬆的微影圖案化製程，其具有改良的層疊控制且不需採用進階的微影工具。如此一來，上述實施例不需額外成本或損失面積。上述機制亦可提供完全平衡的源極/汲極磊晶成長環境，其可改善裝置穩定性、晶片速度、單元匹配效能、並減少備用規格。本發明多種實施例在源極/汲極區上可達改良的一致性控制，與完全一致的鰭狀物末端配置，以同時改良可靠性與製程容忍度。
本發明提供之半導體裝置，包括一或多個鰭狀 物，形成於基板上並沿著第一方向延伸；一或多個閘極，形成於鰭狀物上並沿著第二方向延伸，且第一方向實質上垂直於第二方向，其中閘極包含第一隔離閘極與至少一功能閘極；多個源極/汲極結構，形成於每一閘極的兩側上；以及層間介電(ILD)層，形成於源極/汲極結構上，且層間介電層與第一隔離閘極具有共平面的上表面。第一隔離閘極的第一高度大於功能閘極的第二高度。
本發明提供鰭狀場效電晶體(FinFET)裝置，包括：基板，包括第一主動區與第二主動區在第一方向彼此相隔；第一組鰭狀物設置於第一主動區中，以及第二組鰭狀物設置於第二主動區中，第一組鰭狀物與第二組鰭狀物各自沿著第二方向延伸，且第一方向實質上垂直於第二方向；一或多個閘極，沿著第一方向延伸於第一主動區與第二主動區上，閘極包括一第隔離閘極與至少一功能閘極；多個側壁間隔物，形成於閘極的側壁上；多個源極/汲極結構，形成於側壁間隔物的側壁上；以及層間介電(ILD)層，形成於源極/汲極結構上，且層間介電層與閘極具有共平面的上表面。第一隔離閘極具有第一高度，形成於第一隔離閘極之側壁上的側壁間隔物具有第二高度，且第一高度實質上大於第二高度。
本發明提供半導體裝置的形成方法，包括：提供裝置前驅結構，裝置前驅結構包括：基板，包括第一主動區與第二主動區在第一方向彼此相隔；第一組鰭狀物設置於第一主動區中，以及第二組鰭狀物設置於第二主動區中，第一組鰭狀物與第二組鰭狀物各自沿著第二方向延伸，且第一方向實質上 垂直於第二方向；以及一或多個閘極，各自沿著第一方向延伸於第一主動區與第二主動區上，閘極包括多晶閘極。多晶閘極設置以分隔第一電路與第二電路。上述方法更包括沉積層間介電(ILD)層於基板上；移除多晶閘極以形成溝槽；以ILD層作為蝕刻遮罩單元，使溝槽凹陷至基板中；以及沉積一或多個材料層於凹陷的溝槽中，以形成隔離閘極於第一電路與第二電路之間。
本發明提供半導體裝置的形成方法，包括形成第一組鰭狀物於基板上的n型井區中，以及第二組鰭狀物於基板上的p型井區中；形成一或多個隔離結構以分隔第一組鰭狀物與第二組鰭狀物中相鄰的鰭狀物；形成一或多個閘極於第一組鰭狀物與第二組鰭狀物上，閘極包括多晶閘極，且多晶閘極設置以分隔第一電路與第二電路；沿著多晶閘極形成側壁間隔物、形成源極/汲極結構於基板上及多晶閘極的兩側上；沉積層間介電(ILD)層於源極/汲極結構上；移除多晶閘極以形成溝槽於第一電路與第二電路之間；以ILD層作為蝕刻遮罩單元，使溝槽凹陷至低於源極/汲極結構之底部的深度，以形成一V型溝槽；以及沉積一或多個材料層於V型溝槽中，以形成隔離閘極於第一電路與第二電路之間。
在某些實施例中，使溝槽凹陷的步驟更包括：採用ILD層與沿著多晶閘極的側壁間隔物作為蝕刻遮罩單元。
在某些實施例中，沉積一或多個材料層之步驟包括：沉積界面層(IL)、高介電常數(HK)介電層、與金屬閘極(MG)於V型溝槽中。
在某些實施例中，沉積一或多個材料層之步驟包括沉積介電層於V型溝槽中。
上述實施例之特徵有利於本技術領域中具有通常知識者理解本發明。本技術領域中具有通常知識者應理解可採用本申請案作為基礎，設計並變化其他製程與結構以完成上述實施例之相同目的及/或相同優點。本技術領域中具有通常知識者亦應理解，這些等效置換並未脫離本發明之精神與範疇，並可在未脫離本發明之精神與範疇的前提下進行改變、替換、或更動。
500‧‧‧方法
502、504、506、508、510‧‧‧步驟

Claims (11)

  1. 一種半導體裝置，包括：一或多個鰭狀物，形成於一基板上並沿著一第一方向延伸；一或多個閘極，形成於該或該些鰭狀物上並沿著一第二方向延伸，且該第一方向實質上垂直於該第二方向，其中該或該些閘極包含一第一隔離閘極與至少一功能閘極；多個源極/汲極結構，形成於每一該或該些閘極的兩側上；以及一層間介電層，形成於該些源極/汲極結構上，且該些層間介電層與該第一隔離閘極具有共平面的上表面；其中該第一隔離閘極的一第一高度大於該功能閘極的一第二高度。
  2. 如申請專利範圍第1項所述之半導體裝置，其中該第一隔離閘極包括一界面層、高介電常數介電層、與金屬閘極；其中該高介電常數介電層包括下列材料中的一或多者：氧化鉿、氧化鉭、與氧化鋁；其中該金屬閘極包括下列材料中的一或多者：鈦、銀、鋁、氮化鈦鋁、碳化鉭、氮化鉭碳、氮化鉭矽、錳、鋯、氮化鈦、氮化鉭、釕、鉬、鋁、氮化鎢、銅、與鎢。
  3. 如申請專利範圍第1項所述之半導體裝置，更包括：多個側壁間隔物沿著每一該或該些的閘極形成；其中該第一隔離閘極的該第一高度，大於沿著該第一隔離閘極形成之每一該些側壁間隔物的一第三高度，其中沿著該第一隔離閘極形成的該些側壁間隔物包括一第一材料， 該第一隔離閘極中包括一第二材料，且該第一材料不同於該第二材料。
  4. 如申請專利範圍第1項所述之半導體裝置，更包括：一第二隔離閘極形成於該或該些鰭狀物的一邊緣中；一第一側壁間隔物形成於該第二隔離閘極的外側上；以及一第二側壁間隔物形成於該第二隔離閘極的內側上；其中該第一側壁間隔物的一第四高度，實質上大於該第二側壁間隔物的一第五高度。
  5. 一種鰭狀場效電晶體裝置，包括：一基板，包括一第一主動區與一第二主動區在一第一方向彼此相隔；第一組鰭狀物設置於一第一主動區中，以及第二組鰭狀物設置於一第二主動區中，第一組鰭狀物與第二組鰭狀物各自沿著一第二方向延伸，且該第一方向實質上垂直於該第二方向；一或多個閘極，沿著該第一方向延伸於該第一主動區與該第二主動區上，該或該些閘極包括一第一隔離閘極與至少一功能閘極；多個側壁間隔物，形成於該或該些閘極的側壁上；多個源極/汲極結構，形成於該些側壁間隔物的側壁上；以及一層間介電層，形成於該些源極/汲極結構上，且該層間介電層與該或該些閘極具有共平面的上表面；其中該第一隔離閘極具有一第一高度，形成於該第一隔離 閘極之側壁上的該側壁間隔物具有一第二高度，且該第一高度實質上大於該第二高度。
  6. 如申請專利範圍第5項所述之鰭狀場效電晶體裝置，其中該第一隔離閘極的該第一高度大於該功能閘極的一第三高度。
  7. 如申請專利範圍第5項所述之鰭狀場效電晶體裝置，更包括：一第二隔離閘極，形成於該或該些鰭狀物的一邊緣中；一第一側壁間隔物，形成於該第二隔離閘極的外側上；以及一第二側壁間隔物，形成於該第二隔離閘極的內側上；其中該第二隔離閘極的外側與該第一側壁間隔物具有一第四高度；其中該第二隔離閘極的內側與該第二側壁間隔物具有壹第五高度；其中該第四高度實質上大於該第五高度。
  8. 一種半導體裝置的形成方法，包括：提供一裝置前驅結構，該裝置前驅結構包括：一基板，包括一第一主動區與一第二主動區在一第一方向彼此相隔；第一組鰭狀物設置於一第一主動區中，以及第二組鰭狀物設置於一第二主動區中，第一組鰭狀物與第二組鰭狀物各自沿著一第二方向延伸，且該第一方向實質上垂直於該第二方向；以及 一或多個閘極，各自沿著該第一方向延伸於該第一主動區與該第二主動區上，該或該些閘極包括多晶閘極；其中該多晶閘極設置以分隔一第一電路與一第二電路；沉積一層間介電層於該基板上；移除該多晶閘極以形成一溝槽；以該層間介電層作為一蝕刻遮罩單元，使該溝槽凹陷至該基板中；以及沉積一或多個材料層於凹陷的溝槽中，以形成一隔離閘極於該第一電路與該第二電路之間。
  9. 如申請專利範圍第8項所述之半導體裝置的形成方法，其中沉積該或該些材料層之步驟包括：沉積界面層、高介電常數介電層、與該金屬閘極於凹陷的溝槽中。
  10. 如申請專利範圍第8項所述之半導體裝置的形成方法，其中沉積該或該些材料層之步驟包括沉積一介電層於凹陷的溝槽中。
  11. 如申請專利範圍第8項所述之半導體裝置的形成方法，其中沉積該或該些材料層之步驟包括沉積一介電層於凹陷的溝槽之較下部份中，以及沉積界面層、高介電常數介電層、與金屬閘極於凹陷的溝槽之較上部份中。
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