TWI638441B - 積體電路及其製造方法 - Google Patents

積體電路及其製造方法 Download PDF

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Publication number
TWI638441B
TWI638441B TW106136023A TW106136023A TWI638441B TW I638441 B TWI638441 B TW I638441B TW 106136023 A TW106136023 A TW 106136023A TW 106136023 A TW106136023 A TW 106136023A TW I638441 B TWI638441 B TW I638441B
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Taiwan
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source
integrated circuit
gate electrode
transistor
dielectric
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TW106136023A
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TW201913938A (zh
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王柏鈞
江庭瑋
賴志明
莊惠中
楊榮展
劉如淦
張世明
周雅琪
林義雄
黃禹軒
張玉容
吳國暉
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台灣積體電路製造股份有限公司
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    • H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
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Abstract

一種積體電路包括：半導體基底；隔離區，延伸至所述半導體基底中並上覆所述半導體基底的主體部分；嵌入式導電線路，包括位於所述隔離區中的一部分；以及電晶體，包括源極/汲極區及閘電極。所述源極/汲極區或所述閘電極連接至所述嵌入式導電線路。

Description

積體電路及其製造方法
本發明實施例是有關於一種積體電路及其製造方法。
現代積體電路由形成於半導體基底上的電晶體、電容器及其他裝置構成。在基底上，該些裝置最初彼此隔離，但隨後被內連於一起，以形成功能性電路。典型的內連結構包括橫向內連線(例如金屬線(佈線))及垂直內連線(例如通孔及觸點)。內連結構的品質影響所製作電路的效能及可靠性。逐漸地，內連線決定現代積體電路的效能及密度的極限。
內連結構可包括鎢插塞及鋁線。在較新的幾代積體電路中，亦使用雙重鑲嵌結構(其包括使用雙重鑲嵌製程而形成的銅線及通孔)來形成內連結構。
本發明一些實施例的積體電路包括半導體基底、隔離區、嵌入式導電線路以及電晶體。所述隔離區延伸至所述半導體 基底中並上覆所述半導體基底的主體部分。所述嵌入式導電線路包括位於所述隔離區中的一部分。所述電晶體包括源極/汲極區及閘電極，其中所述源極/汲極區或所述閘電極連接至所述嵌入式導電線路。
本發明另一些實施例的積體電路包括半導體基底、介電層、嵌入式金屬線路以及介電蓋。所述半導體基底包括主體部分。所述介電層包括底部部分以及側壁部分。所述底部部分具有與所述半導體基底的所述主體部分的頂表面接觸的底表面。所述側壁部分位於所述底部部分之上，其中所述側壁部分連接至所述底部部分的相對兩端。所述嵌入式金屬線路位於所述底部部分之上以及所述介電層的所述側壁部分之間。所述介電蓋上覆並接觸所述嵌入式金屬線路的頂表面。
本發明一些實施例的積體電路的製造方法，包括：蝕刻半導體基底，以形成第一溝渠；將金屬線路填充至所述第一溝渠中；形成覆蓋所述金屬線路的介電蓋；以及形成電晶體，其中所述電晶體鄰近於所述金屬線路，且所述電晶體包括源極/汲極區、源極/汲極接觸插塞以及閘電極，其中所述金屬線路包括與所述源極/汲極接觸插塞及所述閘電極中的一者交疊的一部分。
20‧‧‧基底
21、30‧‧‧溝渠
22‧‧‧介電層
26、62‧‧‧凹槽
27‧‧‧介電材料
28‧‧‧介電蓋
29‧‧‧傾斜蝕刻
32‧‧‧半導體條帶
36‧‧‧介電區
38‧‧‧虛擬閘極介電質
40‧‧‧虛擬閘電極
42、64‧‧‧硬遮罩
44‧‧‧虛擬閘極堆疊
46‧‧‧源極/汲極區
50‧‧‧接觸蝕刻停止層
52‧‧‧層間電介質
54‧‧‧凹槽
56‧‧‧閘極介電層
58‧‧‧蝕刻遮罩
60‧‧‧閘電極
60A‧‧‧擴散阻障層
61‧‧‧水平高度
66、70‧‧‧光阻
68‧‧‧開口
71‧‧‧源極/汲極接觸插塞
76‧‧‧源極/汲極矽化物區
80‧‧‧鰭狀場效電晶體
82A、82B‧‧‧接觸插塞
84‧‧‧介電層
86、114、114A、114B‧‧‧金屬線
88‧‧‧金屬間電介質
100‧‧‧積體電路
102、102A、102B‧‧‧主動區
104‧‧‧閘極堆疊
106‧‧‧閘極間隙壁
108‧‧‧閘極結構
110‧‧‧區
112‧‧‧導電線路
115‧‧‧電晶體
116‧‧‧半導體區
118‧‧‧導電特徵
120、122‧‧‧導通孔
202、204、206、208、210、212、214、216、218、220、222、224、226‧‧‧步驟
A-A、B-B、C-C、D-D‧‧‧線
D1‧‧‧深度
D2‧‧‧凹陷深度
H1‧‧‧高度
L1‧‧‧長度
T1、T2‧‧‧厚度
W1、Wcell‧‧‧寬度
結合附圖閱讀以下詳細說明，會最佳地理解本發明的各態樣。應注意，根據本行業中的標準慣例，各種特徵並非按比例 繪製。事實上，為使論述清晰起見，可任意增大或減小各種特徵的尺寸。
圖1根據一些實施例繪示包括嵌入式金屬線路的積體電路的一部分的俯視圖。
圖2A至圖23C根據一些實施例繪示在形成晶粒堆疊時的中間階段的剖視圖。
圖24根據一些實施例繪示用於形成包括嵌入式金屬線路的積體電路的製程流程圖。
以下揭露內容提供用於實作本發明的不同特徵的諸多不同的實施例或實例。以下闡述組件及構造的具體實例以簡化本發明。當然，該些僅為實例且不旨在進行限制。例如，以下說明中將第一特徵形成於第二特徵之上或第二特徵上可包括其中第一特徵與第二特徵被形成為直接接觸的實施例，且亦可包括其中第一特徵與第二特徵之間可形成有附加特徵、進而使得所述第一特徵與所述第二特徵可能不直接接觸的實施例。另外，本發明可能在各種實例中重複使用參考編號及/或字母。此種重複使用是出於簡潔及清晰的目的，而不是自身表示所論述的各種實施例及/或配置之間的關係。
此外，為易於說明，本文中可能使用例如「在...之下(underlying)」、「在...下面(below)」、「下部的(lower)」、「上覆 (overlying)」、「上部的(upper)」等空間相對性用語來闡述圖中所說明的一個元件或特徵與另一(些)元件或特徵的關係。所述空間相對性用語旨在除圖中所繪示的定向外亦囊括裝置在使用或操作中的不同定向。設備可具有其他定向(旋轉90度或其他定向)，且本文中所用的空間相對性描述語可同樣相應地進行解釋。
根據各種示例性實施例，提供一種嵌入式導電線路(其可為金屬線路)及其形成方法。根據一些實施例，說明在形成嵌入式金屬線路時的中間階段。論述一些實施例的某些變化形式。在所有各視圖及說明性實施例中，使用相似參考編號來標示相似元件。
圖1繪示積體電路100的一部分的俯視圖。根據本發明的一些實施例，積體電路100的所說明部分是被預先設計並保存於資料庫中的標準單元的一部分。在設計電路時，預先設計的標準單元被複製以形成更大電路的一部分。然後，在製造所述更大電路時，所述標準單元作為更大設計的一部分被製造於實體晶圓上。虛線示意性地說明標準單元的邊界。根據本發明的替代實施例，積體電路100並非是標準單元且並不被複製，而是在設計時進行佈局。
根據本發明的一些實施例，積體電路100包括一或多個主動區102A及主動區102B，所述一或多個主動區102A及主動區102B被共同地及單獨地稱為主動區102。主動區102可為半導體鰭，或可為平坦主動區。在半導體鰭(主動區102)上形成多個閘 極結構108，以形成多個電晶體115。當主動區102是半導體鰭時，基於所述半導體鰭而形成的所得電晶體是鰭狀場效電晶體(Fin Field-Effect Transistor，FinFET)。當主動區是平坦主動區時，所述電晶體亦可為平坦式電晶體(planar transistor)。在本說明通篇中，以鰭狀場效電晶體為例來進行論述。應瞭解，本發明的概念(例如金屬線路及其使用)亦可與平坦式電晶體一起使用。導電線路112可形成於各半導體鰭(主動區102)之間，且可具有與半導體鰭(主動區102)的長度方向平行的長度方向。導電線路112可為金屬線路，且因此在本說明通篇中被替代地稱為金屬線路，但其亦可由其他導電材料(例如經摻雜的多晶矽)形成。
閘極結構108包括閘極堆疊104、以及位於相應閘極堆疊104的相對兩側上的閘極間隙壁106。閘極堆疊104亦包括閘極介電質及閘電極(圖中未單獨示出)，所述閘極介電質及閘電極將在後面的段落中加以論述。
根據本發明的一些實施例，半導體鰭(主動區102)是長鰭，其中多個閘極結構108跨越所述長鰭而形成多個電晶體。所述電晶體中的某些可共用共同的源極區及/或共同的汲極區，且所述電晶體被組合地用作單一電晶體。舉例而言，在所說明的示例性電路中，四個閘極結構108可跨越半導體鰭(主動區102A)以形成四個電晶體，所述四個電晶體可被並聯連接(共用共同的源極/汲極區)以形成一個電晶體。根據替代實施例，長鰭可被分割成短鰭，且基於短鰭而形成的所說明電晶體中的某些或全部是分 離的電晶體。舉例而言，當鰭(主動區102，例如是主動區102A及/或主動區102B)在區110處被分割時，將存在各自用於形成一或多個電晶體的兩個半導體鰭(主動區102A)及兩個半導體鰭(主動區102B)。
各半導體鰭(主動區102)之間可形成有金屬線路(導電線路112)。積體電路100亦可包括形成於位於電晶體之上的金屬層中的金屬線114(包括金屬線114A及金屬線114B)。金屬線路(導電線路112)與金屬線組合地執行將各積體電路內連的功能。雖然圖中未示出，但根據一些實施例，在與金屬線114A及金屬線114B相同的層處可存在附加金屬線，且所述附加金屬線可與金屬線路(導電線路112)交疊。根據一些實施例，金屬線路(導電線路112)具有與金屬線114A及金屬線114B的長度方向平行的長度方向。
根據本發明的一些實施例，積體電路100包括基於半導體鰭(主動區102)以磊晶方式生長的磊晶半導體區116以及用於連接至磊晶半導體區116的源極/汲極接觸插塞71。導通孔120用於將源極/汲極接觸插塞71中的一者連接至嵌入式金屬線路(導電線路112)。導通孔122用於將閘極堆疊104中的一者的閘電極連接至嵌入式金屬線路(導電線路112)。根據其中鰭(主動區102A)在區110中被分割的一些實施例中，鰭(主動區102A)的位於區110左側上的部分將用於形成第一電晶體，且鰭(主動區102A)的位於區110右側上的部分將用於形成與第一電晶體分離的第二 電晶體。因此，所說明的金屬線路(導電線路112)用於將第一電晶體的源極/汲極區連接至第二電晶體的閘極。根據其中鰭(主動區102A及/或主動區102B)是長鰭而未被分割的其他實施例，基於多個閘極結構108而形成的多個電晶體被連接成單一電晶體，且金屬線路(導電線路112)執行與用於將電晶體的閘極與源極/汲極內連的對接觸點相同的功能。
圖2A至圖23C說明根據本發明一些實施例在形成包括嵌入式導電(金屬)線路的積體電路的一部分時的中間階段的剖視圖。圖2A至圖23C所示的步驟亦示意性地反映於圖24所示的製程流程中。圖2A至圖23C中的圖號中的每一者可包含字母「A」、「B」或「C」。字母「A」表明相應圖是自與含有圖1所示線A-A的垂直平面相同的平面獲得。字母「B」表明相應圖是自與含有圖1所示線B-B的垂直平面相同的平面獲得。字母「C」表明相應圖是自與含有圖1所示線C-C的垂直平面相同的平面獲得。因此，編號包含字母「A」的圖示出自電晶體的源極/汲極區獲得的剖視圖，且編號包含字母「B」的圖示出自閘極堆疊104中的一者獲得的剖視圖，此將在後面的段落中予以詳細論述。
圖2A及圖2B說明基底20的剖視圖，基底20是晶圓的一部分。基底20可為半導體基底，例如矽基底、矽碳基底、矽鍺基底、絕緣層上矽基底、或由其他半導體材料形成的基底。基底20亦可由例如III-V族化合物半導體材料等的其他半導體材料形成。基底20可經輕摻雜有p型或n型雜質。
藉由蝕刻在半導體基底20中形成溝渠21。在圖24所示製程流程中，相應步驟被說明為步驟202。應瞭解，圖2A所示溝渠21與圖2B所示溝渠21是同一溝渠的不同部分，所述溝渠可為具有實質上均勻寬度的細長溝渠。舉例而言，溝渠21的俯視圖形狀與如圖1所示被金屬線路(導電線路112)及介電層22組合地佔據的區的俯視圖形狀相同。
返回參照圖2A及圖2B，根據一些實施例，溝渠21的深度D1可處於約60奈米(nm)與約80奈米之間的範圍中。溝渠21的寬度W1可處於約20奈米與約50奈米之間的範圍中。應瞭解，在本說明通篇中所述的值均為實例，且可使用不同的值。溝渠21的長度(其接近圖1所示嵌入式金屬線路(導電線路112)的長度L1)可大於約10微米(μm)，且可處於約500奈米與約10微米之間的範圍中。
接下來，形成延伸至溝渠21中的介電層22，如圖3A及圖3B中所示。在圖24所示製程流程中，相應步驟被說明為步驟204。介電層22可由氮化矽、氧化矽、氮氧化矽、碳化矽、氮碳化矽等形成。根據一些實施例，藉由沉積來形成介電層22，且形成方法可包括原子層沉積(Atomic Layer Deposition，ALD)、化學氣相沉積(Chemical Vapor Deposition，CVD)、低壓力化學氣相沉積(Low-Pressure Chemical Vapor Deposition，LPCVD)等。根據替代實施例，藉由使基底20的表面層反應以產生介電層22來形成介電層22。當藉由反應而形成時，可將基底20的表面層氧化 及/或氮化以形成氧化矽、氮化矽或氮氧化矽。介電層22可為水平部分與垂直部分具有彼此接近的厚度的保形層。舉例而言，水平部分的厚度T1(圖3A)與垂直部分的厚度T2之差可小於厚度T1及厚度T2兩者的約20%。厚度T1及厚度T2可處於約3奈米與約10奈米之間的範圍中。
然後，用導電材料(其可為含金屬材料)填充溝渠21，以形成圖4A及圖4B中所示的導電線路112。在圖24所示製程流程中，相應步驟被說明為步驟206。在本說明通篇中，導電線路112被替代地稱為金屬線路。根據一些實施例，藉由以下操作來達成導電材料的填充：藉由物理氣相沉積(Physical Vapor Deposition，PVD)沉積晶種層，且然後執行鍍覆製程以在所述晶種層上沉積金屬材料。亦可藉由化學氣相沉積來填充導電材料。根據本發明的一些實施例，所述導電材料由選自Cu、Co、W、Ru、Al、Ni、或其合金的金屬形成。根據本發明的其他實施例，所述導電材料由例如AlCu、W-TiN、TiSi、NiSi、TiN、TaN等的金屬化合物形成。根據本發明的其他實施例，所述導電材料包括可經摻雜有p型摻雜劑(例如硼)或n型摻雜劑(例如磷或砷)的多晶矽。在填充導電材料之後，執行例如化學機械研磨(Chemical Mechanical Polish，CMP)或機械研磨等的平坦化步驟，以移除介電層22及導電材料的位於基底20的頂表面之上的部分。
圖5A及圖5B說明使介電層22及金屬線路(導電線路112)凹陷以形成凹槽26。在圖24所示製程流程中，相應步驟被 說明為步驟208。可藉由濕式蝕刻或乾式蝕刻來執行所述凹陷。凹陷深度D2可處於約30奈米與約50奈米之間的範圍中。剩餘金屬線路可具有介於約20奈米與約40奈米之間的高度H1。根據一些實施例，介電層22的頂表面是傾斜的，其中所述頂表面距基底20越近的外部愈高於所述頂表面距金屬線路(導電線路112)越近的相應內部。此可藉由控制例如製程氣體流量比、分壓、溫度等的蝕刻製程條件來達成。
圖6A及圖6B以及圖7A及圖7B說明形成用於覆蓋金屬線路(導電線路112)的介電蓋28。在圖24所示製程流程中，相應步驟被說明為步驟210。參照圖6A及圖6B，沉積介電材料27。介電材料27可由選自用於形成介電層22的相同候選材料群組的介電材料形成。此外，介電材料27及介電層22可由相同介電材料或不同介電材料形成。介電材料27可完全填充凹槽26(圖5A及圖5B)或局部填充凹槽26。介電層可被平坦化。
如圖7A及圖7B所示，接著對介電材料27進行回蝕，且介電材料27的剩餘部分被稱為介電蓋28。介電蓋28與介電層22可在其之間具有或不具有可辨別開的介面。因此，使用虛線來說明介電蓋28與介電層22之間的介面，以表明所述介面可存在或可不存在。根據一些實施例，所述回蝕包括進行兩次傾斜乾式蝕刻製程，以幫助形成傾斜頂表面。傾斜蝕刻由箭頭29示出。在每一次的傾斜蝕刻中，施加偏壓電壓以使自蝕刻氣體形成的離子沿相對於相應晶圓的主頂表面傾斜的方向移動。
在圖7A及圖7B所示的剖視圖中，金屬線路(導電線路112)被包括介電層22及介電蓋28的介電材料包圍並內嵌於所述介電材料中。因此，在本說明通篇中，金屬線路(導電線路112)被稱為嵌入式金屬線路。
圖8A、圖8B、圖9A、及圖9B說明形成隔離區及半導體鰭。在圖24所示製程流程中，相應步驟被說明為步驟212。參照圖8A及圖8B，蝕刻基底20以形成溝渠30。剩餘結構包括半導體條帶32，即剩餘基底20的條帶部分。半導體條帶32位於基底20的主體部分之上。在蝕刻時，介電蓋28及介電層22未被蝕刻，且因此介電層22的某些部分高於基底20的主體部分的頂表面。介電層22的底部部分可延伸至基底20中。嵌入式金屬線路(導電線路112)的底表面可高於、齊平於或低於基底20的主體部分的頂表面。
在下一步驟中，如圖9A及圖9B中所示，形成介電區(材料)36以填充圖8A及圖8B中所示的溝渠30。所說明的介電區亦被稱為隔離區或淺溝渠隔離(Shallow Trench Isolation，STI)區。根據本發明的一些實施例，淺溝渠隔離區(介電區36)包括襯裏氧化物(圖中未單獨示出)及位於所述襯裏氧化物之上的填充介電材料(圖中未單獨示出)。襯裏氧化物可被形成為水平部分與垂直部分具有彼此接近的厚度的保形層。根據本發明的一些實施例，藉由在含氧環境中例如藉由矽局部氧化(Local Oxidation of Silicon，LOCOS)將基底20及半導體條帶32的被暴露出的表面 層氧化來形成襯裏氧化物，其中可將氧氣(O2)包含於相應製程氣體中。形成填充介電材料以填充溝渠30的剩餘部分。所述填充介電材料可由氧化矽、碳化矽、氮化矽、或上述各者的多層體形成。填充介電材料的形成方法可選自可流動化學氣相沉積(Flowable Chemical Vapor Deposition，FCVD)、旋轉塗佈(spin-on coating)、化學氣相沉積、原子層沉積、高密度電漿化學氣相沉積(High-Density Plasma Chemical Vapor Deposition，HDPCVD)、及低壓力化學氣相沉積。在沉積所述填充介電材料之後，執行平坦化步驟，以移除襯裏氧化物及填充介電材料的多餘部分。因此，淺溝渠隔離區(介電區36)可具有較半導體條帶32的頂表面略高的頂表面。然後，執行凹陷步驟，以移除淺溝渠隔離區的覆蓋介電蓋28的部分，且所得結構示出於圖9A及圖9B中。
在所得結構中，如圖9A及圖9B中所示，半導體條帶32的頂部部分高於淺溝渠隔離區(介電區36)的頂表面且被稱為半導體鰭(主動區102，亦示出於圖1中)。介電蓋28可在傾斜頂表面的頂端處具有尖端，且頂尖端亦可突出高於淺溝渠隔離區(介電區36)的頂表面。
接下來，形成虛擬閘極堆疊，其中圖10B說明各虛擬閘極堆疊44中的一者。在圖24所示製程流程中，相應步驟被說明為步驟214。根據本發明的一些實施例，每一虛擬閘極堆疊44包括虛擬閘極介電質38、虛擬閘電極40及硬遮罩42。根據本發明的一些實施例，虛擬閘極介電質38可由氧化矽形成，虛擬閘電極 40可由多晶矽形成，且硬遮罩42可由氮化矽形成。形成虛擬閘極介電質38、虛擬閘電極40及硬遮罩42可包括將該些層沉積為毯覆層，並在蝕刻步驟中將該等毯覆層圖案化。所得虛擬閘極堆疊44與圖1所示閘極堆疊104位於相同位置處且具有相同形狀及大小。虛擬閘極堆疊44跨越半導體鰭(主動區102)，如圖10B中所示(亦參照圖1)。在形成虛擬閘極堆疊44之後，在虛擬閘極堆疊44的側壁上形成閘極間隙壁106(其示出於圖1中)。由於圖10A所示剖視圖及圖10B所示剖視圖是分別自含有圖1所示線A-A的垂直平面及含有圖1所示線B-B的垂直平面獲得，因而虛擬閘極堆疊44示出於圖10B中且不存在於圖10A所示剖視圖中。
圖11A說明形成磊晶半導體區116(亦參照圖1)，根據一些實施例，磊晶半導體區116選擇性地生長於半導體鰭(主動區102)上。在圖24所示製程流程中，相應步驟被說明為步驟216。由於生長是選擇性的，因而如圖11B中所示，在虛擬閘極堆疊44上未生長半導體區116。根據一些示例性實施例，半導體區116包含矽鍺或矽。視所得鰭狀場效電晶體是p型鰭狀場效電晶體還是n型鰭狀場效電晶體而定，可在繼續進行磊晶的過程中原位(in-situ)摻雜p型或n型雜質。舉例而言，當所得鰭狀場效電晶體是p型鰭狀場效電晶體時，可生長矽鍺硼(silicon germanium boron，SiGeB)。反之，當所得鰭狀場效電晶體是n型鰭狀場效電晶體時，可生長矽磷(silicon phosphorous，SiP)或矽碳磷(silicon carbon phosphorous，SiCP)。根據本發明的替代實施例，半導體區116是 由III-V族化合物半導體(例如GaAs、InP、GaN、InGaAs、InAlAs、GaSb、AlSb、AlAs、AlP、GaP、其組合、或其多層體)形成。
在磊晶步驟之後，可進一步為半導體區116及鰭(主動區102)植入p型或n型雜質以增加其雜質濃度。根據本發明的替代實施例，當半導體區116在磊晶期間被原位摻雜有p型或n型雜質時，跳過植入步驟。因此，形成包括磊晶半導體區116及鰭(主動區102)的源極/汲極區46。
根據替代實施例，並非直接自鰭(主動區102)生長半導體區116，而是執行蝕刻步驟(在下文中被稱為源極/汲極凹陷)以蝕刻鰭(主動區102)。自凹槽生長半導體區116。
如圖11A中所示，半導體區116是橫向地及垂直地生長。介電蓋28的尖端可在相鄰的半導體區116發生過度生長時阻礙此過度生長，且可有助於為形成圖23A所示導通孔120留下足夠的空間。
參照圖12A，形成接觸蝕刻停止層(Contact Etch Stop Layer，CESL)50及層間電介質(Inter-Layer Dielectric，ILD)52。在圖24所示製程流程中，相應步驟亦被說明為步驟216。根據本發明的一些實施例，亦可在形成接觸蝕刻停止層50之前在源極/汲極區46上形成緩衝氧化物層(圖中未示出)。緩衝氧化物層可由氧化矽形成，且接觸蝕刻停止層50可由氮化矽、氮碳化矽等形成。舉例而言，可使用例如原子層沉積等的保形沉積方法來形成緩衝氧化物層及接觸蝕刻停止層50。層間電介質52可包含例如使 用可流動化學氣相沉積(FCVD)、旋轉塗佈、化學氣相沉積或另一種適用的沉積方法而形成的介電材料。層間電介質52可由原矽酸四乙基酯(Tetra Ethyl Ortho Silicate，TEOS)氧化物、電漿增強化學氣相沉積(Plasma Enhanced Chemical Vapor Deposition，PECVD)氧化物(SiO2)、磷矽酸鹽玻璃(Phospho-Silicate Glass，PSG)、硼矽酸鹽玻璃(Boro-Silicate Glass，BSG)、摻硼的磷矽酸鹽玻璃(Boron-Doped Phospho-Silicate Glass，BPSG)等形成。可執行例如化學機械研磨或機械研磨等的平坦化步驟，以使層間電介質52(圖12A)的頂表面、虛擬閘極堆疊44(圖12B)的頂表面及閘極間隙壁106(圖1)的頂表面彼此齊平。
然後，移除圖12B中所示的虛擬閘極堆疊44。因此，形成凹槽54(圖13B)。在圖24所示製程流程中，相應步驟被說明為步驟218。參照圖1，凹槽54(圖中未示出)將位於閘極堆疊104被示出的相同位置處。同時，層間電介質52(圖13A)及閘極間隙壁106(圖1)將留存，且將包圍凹槽54。如圖13B中所示，半導體鰭(主動區102)的某些部分顯露出，且被暴露於凹槽54中。介電蓋28亦可顯露出。
接下來，如圖14A及圖14B中所示，形成(替換)閘極介電層56，其延伸至凹槽54(圖14B)中且如圖14A中所示可具有在層間電介質52之上延伸的一部分。在圖24所示製程流程中，相應步驟被說明為步驟220。根據本發明的一些實施例，閘極介電層56包括介面層(Interfacial Layer，IL；圖中未單獨示出)作為 其下部部分。所述介面層形成於半導體鰭(主動區102)的被暴露出的表面上，且可或可不在淺溝渠隔離區(介電區36)及介電蓋28上延伸。所述介面層可包括藉由對半導體鰭(主動區102)進行熱氧化、化學氧化製程或沉積製程而形成的氧化物層(例如氧化矽層)。閘極介電層56亦可包括在所述介面層之上形成的高介電常數(high-k)介電層。高介電常數介電層被形成為保形層，且包含例如氧化鉿、氧化鑭、氧化鋁、氧化鋯等的高介電常數介電材料。高介電常數介電材料的介電常數(介電常數值)高於3.9，且可高於約7.0。根據本發明的一些實施例，閘極介電層56中的高介電常數介電層是使用原子層沉積或化學氣相沉積而形成。
圖15A、圖15B、圖16A、及圖16B說明將嵌入式金屬線路(導電線路112)暴露出。在圖24所示製程流程中，相應步驟亦被說明為步驟220。圖15B說明形成蝕刻遮罩58，其可為光阻。在圖15B中，將蝕刻遮罩58圖案化，以顯露出閘極介電層56的位於嵌入式金屬線路(導電線路112)正上方的部分，同時覆蓋閘極介電層56的上覆鰭(主動區102)的部分。閘極介電層56的如圖15A中所示的部分亦被暴露出。
接下來，蝕刻閘極介電層56的被暴露出的部分。此外，亦蝕刻介電蓋28，且嵌入式金屬線路(導電線路112)被暴露出。在蝕刻閘極介電層56之後，移除蝕刻遮罩58，且所得結構示出於圖16A及圖16B中。
在下一步驟中，如圖17B中所示，在閘極介電層56之上 形成填充圖16B所示溝渠(凹槽54)的閘電極60。在圖24所示製程流程中，相應步驟被說明為步驟222。形成閘電極60可包括進行多個沉積製程以沉積多個導電層，以及執行平坦化步驟以移除所述導電層的位於層間電介質52(圖17A)之上的多餘部分。因此，所得閘電極60將具有處於以虛線61示出的水平高度的頂表面。可使用例如原子層沉積或化學氣相沉積等的保形沉積方法來執行沉積導電層。
閘電極60可包括擴散阻障層60A及位於所述擴散阻障層之上的一個(或多個)功函數層。擴散阻障層60A可由氮化鈦(titanium nitride，TiN)形成，其可(或可不)摻雜有矽以形成TiSiN。所述功函數層決定閘極的功函數，且包括至少一個層或由不同材料形成的多個層。功函數層的具體材料是根據相應鰭狀場效電晶體是n型鰭狀場效電晶體還是p型鰭狀場效電晶體來加以選擇。舉例而言，當鰭狀場效電晶體是n型鰭狀場效電晶體時，功函數層可包括TaN層及位於所述TaN層之上的鈦鋁(titanium aluminum，TiAl)層。當鰭狀場效電晶體是p型鰭狀場效電晶體時，功函數層可包括TaN層、位於所述TaN層之上的TiN層及位於所述TiN層之上的TiAl層。在沉積功函數層之後，形成另一阻障層，其可為另一TiN層。閘電極60亦可包含填充金屬，所述填充金屬可例如由鎢或鈷形成。所述填充金屬完全填充剩餘凹槽54(圖16B)。
如圖17B中所示，導電材料的一部分形成位於閘電極60 之下的導通孔122，且將閘電極60連接至嵌入式金屬線路(導電線路112)。導通孔122亦示出於圖1中。嵌入式金屬線路(導電線路112)及導通孔122具有與在電晶體之上形成的內連結構中的金屬線及通孔類似的功能。接下來，蝕刻閘電極60以形成凹槽62，如圖17B中所示。
參照圖18B，在閘極堆疊104之上形成硬遮罩64。硬遮罩64填充圖17B中所示的凹槽62。硬遮罩64由介電材料形成，所述介電材料可為氧化矽、氮化矽、氧化鋁、碳化矽等。閘極介電層56、閘電極60及硬遮罩64被組合地稱為閘極堆疊104，其亦說明於圖1中。亦如圖1中所示，閘極堆疊104形成彼此平行的多個條帶，且閘極堆疊104的長度方向可垂直於嵌入式金屬線路(導電線路112)的長度方向。
圖19A至圖22B說明形成源極/汲極接觸插塞。參照圖19A，形成光阻66並將其圖案化。如圖19B中所示，光阻66覆蓋閘極堆疊104。然後，使用經圖案化光阻66作為蝕刻遮罩來蝕刻層間電介質52，進而形成延伸至層間電介質52中的開口68。在圖24所示製程流程中，相應步驟被說明為步驟224。蝕刻劑被選擇成使得半導體區116未被蝕刻且可在某些區中用作蝕刻停止層。在蝕刻層間電介質52之後，移除光阻66。
接下來，參照圖20A及圖20B，形成光阻70並將其圖案化，因此覆蓋閘極堆疊104並使層間電介質52的一部分被暴露出。進一步蝕刻層間電介質52，使得開口68進一步向下延伸至層 間電介質52中，直至介電蓋28(圖19A)被暴露出為止。然後，蝕刻被暴露出的介電蓋28，且嵌入式金屬線路(導電線路112)被暴露出。在蝕刻之後，移除光阻70。
圖21A說明形成導電特徵118。在圖24所示製程流程中，相應步驟被說明為步驟226。此外，在半導體區116的表面上形成源極/汲極矽化物區76。根據一些實施例，形成導電特徵118包括形成延伸至開口68(圖20A)中的金屬層及金屬氮化物層(圖中未單獨示出)。所述金屬層可由鈦形成，且所述金屬氮化物層可由氮化鈦形成。所述金屬層及所述金屬氮化物層可為延伸至源極/汲極區46的側壁以及朝上小面及朝下小面上的保形層。接下來，執行退火，且在源極/汲極區46的表面上形成源極/汲極矽化物區76。然後，沉積金屬材料以填充剩餘開口68，隨後進行平坦化步驟。因此，在層間電介質52中形成導電特徵118。導電特徵118包括同時形成的源極/汲極接觸插塞71及導通孔120。因此，形成鰭狀場效電晶體80，其中鰭狀場效電晶體80中的每一者包括源極/汲極區46(圖21A)、鰭(主動區102)以及位於鰭(主動區102)之上的閘極堆疊104(圖21B，亦參照圖1)。
如圖1及圖21A中所示，源極/汲極接觸插塞71經由導通孔120電性連接至嵌入式金屬線路。因此，如圖21A及圖21B中所示，嵌入式金屬線路(導電線路112)能夠連接至閘電極及源極/汲極接觸插塞(及因此源極/汲極區)兩者，且可用作內連結構的一部分。
圖22說明根據一些實施例而形成的源極/汲極接觸插塞71的剖視圖。所說明的源極/汲極接觸插塞71未連接至嵌入式金屬線路(導電線路112)。圖22所示剖視圖亦可自含有圖1所示線D-D的垂直平面獲得。
圖23A及圖23B說明形成介電層84(其亦可被稱為層間電介質)以及層間電介質(介電層84)中的接觸插塞82A及接觸插塞82B。接觸插塞82A及接觸插塞82B分別連接至源極/汲極接觸插塞71及閘電極60。然後，形成金屬間電介質(Inter-Metal Dielectric，IMD)88及金屬線86，其中金屬線86連接至接觸插塞82A及接觸插塞82B。舉例而言，金屬間電介質88可由低介電常數介電層形成。
圖23C說明自含有圖1所示線C-C的垂直平面獲得的剖視圖。根據一些實施例，如圖23C中所示，相應閘電極60未連接至嵌入式金屬線路(導電線路112)。而是，閘極介電層56及介電蓋28用於將對應閘電極60與嵌入式金屬線路(導電線路112)電性絕緣。
本發明的實施例具有某些有利特徵。在例如標準單元等積體電路的佈局中，對於減小積體電路大小(具體而言，寬度(例如圖1所示寬度Wcell))而言，所需的金屬線數目成為瓶頸。藉由將金屬線中的某些內嵌於淺溝渠隔離區中而非將所有金屬線形成於金屬層中，可形成更多金屬線，且可減小標準單元的寬度Wcell。寬度Wcell可受分配所需數目的金屬線所需的寬度而被限 制。舉例而言，標準單元的寬度Wcell的減小量可介於約10%與約50%之間。電晶體的閘極密度亦可因電晶體可被更緻密地佈設而增加，而不受金屬線佈線能力限制。
根據本發明的一些實施例，一種積體電路包括：半導體基底；隔離區，延伸至所述半導體基底中並上覆所述半導體基底的主體部分；嵌入式導電線路，包括位於所述隔離區中的一部分；以及電晶體，具有源極/汲極區及閘電極。所述源極/汲極區或所述閘電極連接至所述嵌入式導電線路。在一些實施例中，所述嵌入式導電線路包括低於所述電晶體而延伸的一部分。在一些實施例中，所述嵌入式導電線路連接至所述閘電極，且所述積體電路更包括位於所述閘電極之下且連接至所述閘電極的通孔。在一些實施例中，所述閘電極連續地連接至所述通孔，在所述閘電極與所述通孔之間未形成介面。在一些實施例中，所述積體電路更包括連接至所述嵌入式導電線路的源極/汲極接觸插塞。在一些實施例中，所述積體電路更包括位於所述源極/汲極接觸插塞與所述嵌入式導電線路之間且連接至所述源極/汲極接觸插塞及所述嵌入式導電線路的附加通孔。在一些實施例中，所述積體電路更包括介電層，所述介電層包括：側壁部分，位於所述嵌入式導電線路的相對兩側，且所述側壁部分具有傾斜頂表面；以及底部部分，與所述嵌入式導電線路交疊。
根據本發明的一些實施例，一種積體電路包括：半導體基底，具有主體部分；以及介電層。所述介電層具有：底部部分， 具有與所述半導體基底的所述主體部分的頂表面接觸的底表面；以及側壁部分，位於所述底部部分之上，其中所述側壁部分連接至所述底部部分的相對兩端。所述積體電路更包括：嵌入式金屬線路，位於所述底部部分之上以及所述介電層的所述側壁部分之間；以及介電蓋，上覆並接觸所述嵌入式金屬線路的頂表面。在一些實施例中，所述介電層的所述底部部分延伸至所述半導體基底的所述主體部分中。在一些實施例中，所述積體電路更包括淺溝渠隔離區，所述淺溝渠隔離區具有位於組合區的相對兩側的部分，所述組合區包括所述嵌入式金屬線路及所述介電層。在一些實施例中，所述積體電路更包括：半導體條帶，上覆所述半導體基底的所述主體部分；以及半導體鰭，與所述半導體條帶交疊，並且所述半導體鰭高於所述淺溝渠隔離區，且所述嵌入式金屬線路具有與所述半導體鰭的長度方向平行的長度方向。在一些實施例中，所述積體電路更包括電晶體，所述電晶體包括：源極/汲極區；以及源極/汲極接觸插塞，具有與所述源極/汲極區交疊的第一部分及與所述源極/汲極區處於相同水平高度的第二部分，且所述嵌入式金屬線路的一部分與所述源極/汲極接觸插塞的所述第二部分交疊並電性連接。在一些實施例中，所述積體電路更包括電晶體，所述電晶體具有閘電極，且所述嵌入式金屬線路與所述閘電極交疊並電性連接。在一些實施例中，所述電晶體更包括閘極介電質，且所述嵌入式金屬線路經由所述閘極介電質中的開口連接至所述閘電極。
根據本發明的一些實施例，一種積體電路的製造方法包括：蝕刻半導體基底，以形成第一溝渠；將金屬線路填充至所述第一溝渠中；形成覆蓋所述金屬線路的介電蓋；以及形成電晶體，其中所述電晶體鄰近於所述金屬線路。所述電晶體包括：源極/汲極區；源極/汲極接觸插塞；以及閘電極，且所述金屬線路具有與所述源極/汲極接觸插塞及所述閘電極中的一者交疊的一部分。在一些實施例中，所述金屬線路的所述部分位於所述源極/汲極接觸插塞之下且經由通孔連接至所述源極/汲極接觸插塞。在一些實施例中，所述通孔與所述源極/汲極接觸插塞是在共同製程中形成。在一些實施例中，所述金屬線路的所述部分位於所述閘電極之下且經由通孔連接至所述閘電極。在一些實施例中，所述通孔與所述閘電極是在共同製程中形成。在一些實施例中，所述方法更包括形成淺溝渠隔離區，所述淺溝渠隔離區包括位於所述金屬線路的相對兩側的部分。
根據本發明的一些實施例，一種積體電路包括：隔離區；彼此平行的第一半導體條帶及第二半導體條帶，且所述第一半導體條帶及所述第二半導體條帶位於所述隔離區中；嵌入式金屬線路，位於所述第一半導體條帶與所述第二半導體條帶之間；以及第一半導體鰭及第二半導體鰭，分別與所述第一半導體條帶及所述第二半導體條帶交疊。在一些實施例中，所述積體電路更包括閘電極，所述閘電極跨越所述嵌入式金屬線路、所述第一半導體鰭及所述第二半導體鰭。在一些實施例中，所述嵌入式金屬線路 電性連接至所述閘電極。
根據本發明的一些實施例，一種積體電路的製造方法包括：形成延伸至半導體基底中的金屬線路，且所述金屬線路被包括介電層及介電蓋的介電特徵包圍；蝕刻所述半導體基底，以形成半導體條帶；沉積介電材料，以將所述金屬線路及所述半導體條帶嵌入所述介電材料中；使所述介電材料凹陷以形成淺溝渠隔離區，且所述介電蓋被暴露出，並且所述半導體條帶的頂部部分突出高於所述淺溝渠隔離區的頂表面以形成半導體鰭；在所述半導體鰭的第一部分之上形成金屬閘極；在所述半導體鰭的第二部分上生長磊晶半導體區；以及將所述金屬線路電性耦合至所述金屬閘極及所述磊晶半導體區中的一者。在一些實施例中，所述金屬閘極與所述金屬線路的一部分交疊，且所述金屬線路經由位於所述金屬閘極之下的通孔連接至所述金屬閘極。在一些實施例中，所述通孔與所述金屬閘極是在共同製程中形成。在一些實施例中，所述方法更包括形成源極/汲極接觸插塞，所述源極/汲極接觸插塞與所述磊晶半導體區的一部分及所述金屬線路的一部分兩者交疊，且所述金屬線路經由位於所述源極/汲極接觸插塞之下的通孔連接至所述源極/汲極接觸插塞。在一些實施例中，所述通孔與所述源極/汲極接觸插塞是在共同製程中形成。
根據本發明的一些實施例，一種積體電路的製造方法包括：形成電晶體，所述電晶體包括一部分較隔離區的頂表面高的源極/汲極區；形成一部分較所述隔離區的所述頂表面低的嵌入式 金屬線路；以及將所述電晶體連接至所述嵌入式金屬線路。在一些實施例中，所述方法更包括形成介電層，在所述嵌入式金屬線路的剖視圖中，所述介電層環繞所述嵌入式金屬線路。
以上內容概述了若干實施例的特徵以使熟習此項技術者可更好地理解本發明的各態樣。熟習此項技術者應瞭解，他們可易於使用本發明作為基礎來設計或修改其他製程及結構以實施本文所介紹實施例的相同目的及/或達成本文所介紹實施例的相同優點。熟習此項技術者亦應認識到，此種等效構造並不背離本發明的精神及範圍，且在不背離本發明的精神及範圍的條件下，他們可對本文作出各種改變、替代、及變更。

Claims (10)

  1. 一種積體電路，包括：半導體基底；隔離區，延伸至所述半導體基底中並上覆所述半導體基底的主體部分；嵌入式導電線路，包括位於所述隔離區中的一部分；以及電晶體，包括源極/汲極區及閘電極，其中所述源極/汲極區或所述閘電極連接至所述嵌入式導電線路。
  2. 如申請專利範圍第1項所述的積體電路，其中所述嵌入式導電線路包括低於所述電晶體而延伸的一部分；或其中所述嵌入式導電線路連接至所述閘電極，且所述積體電路更包括位於所述閘電極之下且連接至所述閘電極的通孔。
  3. 如申請專利範圍第2項所述的積體電路，其中所述閘電極連續地連接至所述通孔，在所述閘電極與所述通孔之間未形成介面。
  4. 如申請專利範圍第1項所述的積體電路，更包括介電層，所述介電層包括：側壁部分，位於所述嵌入式導電線路的相對兩側，其中所述側壁部分具有傾斜頂表面；以及底部部分，與所述嵌入式導電線路交疊。
  5. 一種積體電路，包括：半導體基底，包括主體部分；介電層，包括：底部部分，具有與所述半導體基底的所述主體部分的頂表面接觸的底表面；以及側壁部分，位於所述底部部分之上，其中所述側壁部分連接至所述底部部分的相對兩端；嵌入式金屬線路，位於所述底部部分之上以及所述介電層的所述側壁部分之間；以及介電蓋，上覆並接觸所述嵌入式金屬線路的頂表面。
  6. 如申請專利範圍第5項所述的積體電路，其中所述介電層的所述底部部分延伸至所述半導體基底的所述主體部分中。
  7. 如申請專利範圍第5項所述的積體電路，更包括：淺溝渠隔離區，包括位於組合區的相對兩側的部分，所述組合區包括所述嵌入式金屬線路及所述介電層。
  8. 如申請專利範圍第5項所述的積體電路，更包括電晶體，所述電晶體包括：源極/汲極區；以及源極/汲極接觸插塞，具有與所述源極/汲極區交疊的第一部分及與所述源極/汲極區處於相同水平高度的第二部分，其中所述嵌入式金屬線路的一部分與所述源極/汲極接觸插塞的所述第二部分交疊並電性連接。
  9. 如申請專利範圍第5項所述的積體電路，更包括電晶體，所述電晶體包括：閘電極，其中所述嵌入式金屬線路與所述閘電極交疊並電性連接。
  10. 一種積體電路的製造方法，包括：蝕刻半導體基底，以形成第一溝渠；將金屬線路填充至所述第一溝渠中；形成覆蓋所述金屬線路的介電蓋；以及形成電晶體，其中所述電晶體鄰近於所述金屬線路，且所述電晶體包括：源極/汲極區；源極/汲極接觸插塞；以及閘電極，其中所述金屬線路包括與所述源極/汲極接觸插塞及所述閘電極中的一者交疊的一部分。
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