CN111106059A - 集成电路结构和形成集成电路结构的方法 - Google Patents
集成电路结构和形成集成电路结构的方法 Download PDFInfo
- Publication number
- CN111106059A CN111106059A CN201911015432.9A CN201911015432A CN111106059A CN 111106059 A CN111106059 A CN 111106059A CN 201911015432 A CN201911015432 A CN 201911015432A CN 111106059 A CN111106059 A CN 111106059A
- Authority
- CN
- China
- Prior art keywords
- semiconductor
- buried
- layer
- forming
- power rail
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 158
- 239000004065 semiconductor Substances 0.000 claims abstract description 219
- 239000000758 substrate Substances 0.000 claims abstract description 85
- 238000005530 etching Methods 0.000 claims abstract description 67
- 238000002955 isolation Methods 0.000 claims abstract description 18
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 36
- 239000004020 conductor Substances 0.000 claims description 17
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 13
- 229910003460 diamond Inorganic materials 0.000 claims description 12
- 239000010432 diamond Substances 0.000 claims description 12
- 238000011049 filling Methods 0.000 claims description 9
- 238000007747 plating Methods 0.000 claims description 4
- 239000010410 layer Substances 0.000 description 197
- 230000008569 process Effects 0.000 description 128
- 230000015572 biosynthetic process Effects 0.000 description 46
- 239000000463 material Substances 0.000 description 34
- 229910052751 metal Inorganic materials 0.000 description 33
- 239000002184 metal Substances 0.000 description 33
- 239000003989 dielectric material Substances 0.000 description 17
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 14
- 238000005229 chemical vapour deposition Methods 0.000 description 14
- 238000000151 deposition Methods 0.000 description 14
- 229910052710 silicon Inorganic materials 0.000 description 14
- 239000010703 silicon Substances 0.000 description 14
- 229910052814 silicon oxide Inorganic materials 0.000 description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 11
- 238000000231 atomic layer deposition Methods 0.000 description 11
- 229910021332 silicide Inorganic materials 0.000 description 11
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical group [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 11
- 229920002120 photoresistant polymer Polymers 0.000 description 10
- 229910052581 Si3N4 Inorganic materials 0.000 description 9
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 9
- OQNXPQOQCWVVHP-UHFFFAOYSA-N [Si].O=[Ge] Chemical compound [Si].O=[Ge] OQNXPQOQCWVVHP-UHFFFAOYSA-N 0.000 description 7
- 230000003647 oxidation Effects 0.000 description 7
- 238000007254 oxidation reaction Methods 0.000 description 7
- 230000008021 deposition Effects 0.000 description 5
- 150000004767 nitrides Chemical class 0.000 description 4
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 4
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 description 4
- 239000010936 titanium Substances 0.000 description 4
- 230000004888 barrier function Effects 0.000 description 3
- 229910017052 cobalt Inorganic materials 0.000 description 3
- 239000010941 cobalt Substances 0.000 description 3
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 3
- 150000001875 compounds Chemical class 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- 239000005360 phosphosilicate glass Substances 0.000 description 3
- 229910052719 titanium Inorganic materials 0.000 description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- 239000010937 tungsten Substances 0.000 description 3
- QTBSBXVTEAMEQO-UHFFFAOYSA-N Acetic acid Chemical compound CC(O)=O QTBSBXVTEAMEQO-UHFFFAOYSA-N 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- HMDDXIMCDZRSNE-UHFFFAOYSA-N [C].[Si] Chemical compound [C].[Si] HMDDXIMCDZRSNE-UHFFFAOYSA-N 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 239000005388 borosilicate glass Substances 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 238000000407 epitaxy Methods 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 238000000227 grinding Methods 0.000 description 2
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 238000004528 spin coating Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 229910052715 tantalum Inorganic materials 0.000 description 2
- 229910052718 tin Inorganic materials 0.000 description 2
- KFZMGEQAYNKOFK-UHFFFAOYSA-N 2-propanol Substances CC(C)O KFZMGEQAYNKOFK-UHFFFAOYSA-N 0.000 description 1
- 229910017115 AlSb Inorganic materials 0.000 description 1
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 description 1
- 229910005542 GaSb Inorganic materials 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 1
- -1 InAlAs Inorganic materials 0.000 description 1
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 description 1
- 229910004166 TaN Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- CFOAUMXQOCBWNJ-UHFFFAOYSA-N [B].[Si] Chemical compound [B].[Si] CFOAUMXQOCBWNJ-UHFFFAOYSA-N 0.000 description 1
- CHYRFIXHTWWYOX-UHFFFAOYSA-N [B].[Si].[Ge] Chemical compound [B].[Si].[Ge] CHYRFIXHTWWYOX-UHFFFAOYSA-N 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 229910052788 barium Inorganic materials 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 239000002178 crystalline material Substances 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 230000009969 flowable effect Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- YBMRDBCBODYGJE-UHFFFAOYSA-N germanium oxide Inorganic materials O=[Ge]=O YBMRDBCBODYGJE-UHFFFAOYSA-N 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 229910052746 lanthanum Inorganic materials 0.000 description 1
- 229910052745 lead Inorganic materials 0.000 description 1
- 229910052749 magnesium Inorganic materials 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- PVADDRMAFCOOPC-UHFFFAOYSA-N oxogermanium Chemical group [Ge]=O PVADDRMAFCOOPC-UHFFFAOYSA-N 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
- 229910052726 zirconium Inorganic materials 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
- H01L21/743—Making of internal connections, substrate contacts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
- H01L23/5286—Arrangements of power or ground buses
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/4175—Source or drain electrodes for field effect devices for lateral devices where the connection to the source or drain region is done through at least one part of the semiconductor substrate thickness, e.g. with connecting sink or with via-hole
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41791—Source or drain electrodes for field effect devices for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
- H01L29/66333—Vertical insulated gate bipolar transistors
- H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
- H01L29/66704—Lateral DMOS transistors, i.e. LDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
- H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76865—Selective removal of parts of the layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76883—Post-treatment or after-treatment of the conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys
- H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Geometry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
Abstract
方法包括蚀刻半导体衬底以形成两个半导体带。两个半导体带均位于半导体衬底的主体部分上方。该方法还包括蚀刻主体部分以在半导体衬底的主体部分中形成沟槽,形成内衬沟槽的衬垫介电层,在沟槽中形成掩埋接触件,在掩埋接触件上方形成连接至掩埋接触件的掩埋电源轨,其中,掩埋电源轨位于两个半导体带之间,以及在两个半导体带的相对侧上形成隔离区域。掩埋电源轨位于隔离区域的部分下面。本发明的实施例还涉及集成电路结构和形成集成电路结构的方法。
Description
技术领域
本发明的实施例涉及集成电路结构和形成集成电路结构的方法。
背景技术
现代集成电路由形成在半导体衬底上的晶体管、电容器和其它器件构成。在衬底上,这些器件最初彼此隔离,但随后互连在一起以形成功能电路。典型的互连结构包括横向互连,诸如金属线(布线),以及垂直互连,诸如通孔和接触件。
通过位于集成电路的金属层中的电源轨向集成电路供电。例如,底金属层(M0或M1)可以包括多条金属线,诸如VDD电源轨和VSS电源轨。
发明内容
本发明的实施例提供了一种形成集成电路结构的方法,所述方法包括:蚀刻半导体衬底以形成两个半导体带,其中,所述两个半导体带均位于所述半导体衬底的主体部分上方;蚀刻所述主体部分以在所述半导体衬底的主体部分中形成沟槽;形成内衬所述沟槽的衬垫介电层;在所述沟槽中形成掩埋接触件;在所述掩埋接触件上方形成连接至所述掩埋接触件的掩埋电源轨,其中,所述掩埋电源轨位于所述两个半导体带之间;以及在所述两个半导体带的相对侧上形成隔离区域,其中,所述掩埋电源轨位于所述隔离区域的部分下面。
本发明的另一实施例提供了一种形成集成电路结构的方法,所述方法包括:在半导体衬底的主体部分上方形成第一半导体带和第二半导体带;在所述第一半导体带和所述第二半导体带之间形成掩埋电源轨,其中,所述掩埋电源轨与所述第一半导体带的第一部分处于相同的层级;基于所述第一半导体带的第二部分形成源极/漏极区域,其中,所述第二部分高于所述第一部分;形成延伸至所述半导体衬底的主体部分中的掩埋接触件;蚀刻所述半导体衬底的主体部分以形成接触开口,其中,所述掩埋接触件暴露于所述接触开口;以及填充所述接触开口以形成通孔,其中,所述通孔通过所述掩埋接触件电连接至所述掩埋电源轨。
本发明的又一实施例提供了一种集成电路结构,包括:块状半导体衬底;第一半导体带和第二半导体带,位于所述块状半导体衬底上方并且连接至所述块状半导体衬底;掩埋电源轨,位于所述第一半导体带和所述第二半导体带之间,其中,所述掩埋电源轨与所述第一半导体带的第一部分处于相同的层级;掩埋接触件,延伸至所述块状半导体衬底中并且电连接至所述掩埋电源轨;以及通孔,从所述块状半导体衬底的背面延伸至所述掩埋接触件。
附图说明
当结合附图进行阅读时,从以下详细描述可最佳理解本发明的各个方面。应该指出,根据工业中的标准实践,各个部件未按比例绘制。实际上,为了清楚的讨论,各个部件的尺寸可以任意地增大或减小。
图1至图16、图17A、图17B和图18至图24示出了根据一些实施例的掩埋电源轨和菱形掩埋接触件的形成中的中间阶段的截面图。
图25至图30示出了根据一些实施例的通孔型通孔的形成中的中间阶段的截面图。
图31至图36示出了根据一些实施例的沟槽型通孔的形成中的中间阶段的截面图。
图37示出了根据一些实施例的掩埋电源轨、半导体鳍和接触插塞的顶视图。
图38示出了根据一些实施例的掩埋电源轨和掩埋接触件的底视图。
图39和图40示出了根据一些实施例的图38所示的结构的截面图。
图41示出了根据一些实施例的掩埋电源轨和掩埋接触件的底视图。
图42和图43示出了根据一些实施例的图41所示的结构的截面图。
图44至图63、图64A、图64B和图65至图67示出了根据一些实施例的掩埋电源轨和圆化掩埋接触件的形成中的中间阶段的截面图。
图68至图73示出了根据一些实施例的沟槽型通孔的形成中的中间阶段的截面图。
图74示出了根据一些实施例的掩埋电源轨和掩埋接触件的底视图。
图75和图76示出了根据一些实施例的图74所示的结构的截面图。
图77示出了根据一些实施例的用于形成掩埋电源轨和掩埋接触件的工艺流程。
具体实施方式
以下公开内容提供了许多用于实现本发明的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然,这些仅仅是实例,而不旨在限制本发明。例如,以下描述中,在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例,并且也可以包括在第一部件和第二部件之间可以形成额外的部件,从而使得第一部件和第二部件可以不直接接触的实施例。此外,本发明可在各个实施例中重复参考标号和/或字符。该重复是为了简单和清楚的目的,并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且,为便于描述,在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等空间相对术语,以描述如图所示的一个元件或部件与另一个(或另一些)原件或部件的关系。除了图中所示的方位外,空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其它方式定向(旋转90度或在其它方位上),而本文使用的空间相对描述符可以同样地作出相应的解释。
根据各个实施例提供了掩埋电源轨、掩埋接触件及其形成方法。根据一些实施例示出了形成掩埋电源轨和掩埋接触件的中间阶段。讨论了一些实施例的一些变型。贯穿各个视图和示例性实施例,相同的参考标号用于表示相同的元件。根据本发明的一些实施例,掩埋电源轨形成在半导体衬底中,并且掩埋接触件也形成在半导体衬底中以具有比掩埋电源轨更宽的宽度,使得半导体衬底中的通孔可以位于掩埋接触件上而没有未对准。
图1至图16、图17A、图17B和图18至图24示出了根据本发明的一些实施例的掩埋电源轨和菱形掩埋接触件的形成中的中间阶段的截面图。相应的工艺也示意性地反映在图77所示的工艺流程中。
图1示出了初始结构的截面图。初始结构包括晶圆10,晶圆10还包括半导体衬底20。半导体衬底20可以是硅衬底、硅锗衬底或由诸如III-V族化合物半导体材料的其它半导体材料形成的衬底。半导体衬底20可以掺杂有p型或n型杂质。半导体衬底20可以具有(100)或(001)表面平面。
蚀刻半导体衬底20以形成半导体带30。相应的工艺示出为图77所示的工艺流程200中的工艺202。为了蚀刻半导体衬底20,在半导体衬底20上形成垫氧化物层26和硬掩模层28,并且然后将其图案化。垫氧化物层26可以是由氧化硅形成的薄膜。根据本发明的一些实施例,垫氧化物层26在热氧化工艺中形成,其中,半导体衬底20的顶面层被氧化以形成垫氧化物层26。垫氧化物层26用作半导体衬底20和硬掩模层28之间的粘合层。垫氧化物层26也可以用作蚀刻硬掩模层28的蚀刻停止层。根据本发明的一些实施例,硬掩模层28由氮化硅形成,例如,使用低压化学汽相沉积(LPCVD)。根据本发明的其它实施例,通过硅的热氮化或等离子体增强化学汽相沉积(PECVD)形成硬掩模层28。在硬掩模层28上形成光刻胶(未示出),并且然后图案化光刻胶。然后使用图案化的光刻胶作为蚀刻掩模来蚀刻硬掩模层28,以形成如图2所示的图案化的硬掩模层28。
接下来,将图案化的硬掩模层28用作蚀刻掩模以蚀刻垫氧化物层26和衬底20,从而形成沟槽24。半导体衬底20的位于沟槽24之间的部分是半导体带30,当从顶部观察时,半导体带30可以具有细长的带状。半导体带30位于半导体衬底20的主体部分上方并且接触半导体衬底20的主体部分,半导体衬底20也称为块状半导体衬底20。接下来,形成介电层32,其可以是形成在先前的工艺中形成的结构的侧壁和顶面上的共形层。可以使用例如原子层沉积(ALD)、化学汽相沉积(CVD)等来沉积介电层32,使得介电层32形成为共形层。
接下来,参照图2,形成并且图案化蚀刻掩模34(其可以由光刻胶形成),从而暴露两个相邻半导体带30之间的间隔。首先,例如,在各向异性蚀刻工艺中去除介电层32的部分,从而暴露下面的半导体衬底20的顶面。接下来,蚀刻块状半导体衬底20以形成沟槽36,沟槽36可以具有菱形形状。相应的工艺示出为图77所示的工艺流程200中的工艺204。菱形形状延伸低于半导体带30的底部,并且延伸至半导体衬底20的主体部分中。根据本发明的一些实施例,蚀刻包括各向异性蚀刻工艺(干蚀刻工艺),以及随后的各向同性蚀刻工艺,诸如湿蚀刻工艺或干蚀刻工艺。例如,在各向异性蚀刻工艺中,沟槽36首先形成为延伸至由虚线38标记的位置,并且然后实施各向同性蚀刻工艺。干各向同性蚀刻工艺可以使用C2F6、CF4、SO2、HBr、Cl2和O2的混合物或HBr、Cl2、O2和CF2的混合物等实施。湿各向同性蚀刻工艺可以使用KOH、四甲基氢氧化铵(TMAH)、CH3COOH、NH4OH、H2O2、异丙醇(IPA)或HF、HNO3和H2O的溶液实施。
各向异性蚀刻将沟槽36向下延伸至块状半导体衬底20中,使得在随后的各向同性蚀刻工艺中,沟槽36不会侵入半导体带30。由于各向同性蚀刻工艺,半导体衬底20的面向沟槽36的表面位于(111)表面平面上。沟槽36水平扩展以具有大于相邻半导体带30之间的距离的水平尺寸。此外,沟槽36与半导体带30之间的间隔自对准。再者,参照图38和图41,沟槽36的中心的位置(其填充为形成掩埋接触件48)将与直线(在Y方向上延伸)对准,并且沟槽36的中心是图38或图41中的菱形的中心。可以在各向异性蚀刻工艺之后(但在各向同性蚀刻工艺之前)或在各向同性蚀刻工艺之后去除蚀刻掩模34(图2)。
然后,例如,在各向同性蚀刻工艺中去除介电层32。接下来,如图3所示,形成保护半导体带30的侧壁的介电层40(其是衬垫层)。相应的工艺示出为图77所示的工艺流程200中的工艺206。介电层40是共形的,并且形成保护半导体衬底20的面向沟槽36的暴露表面(包括(111)表面)的衬垫。使用诸如ALD、CVD等的共形沉积方法形成介电层40。介电层40可以由氧化硅、氮化硅等形成。
图4示出了导电晶种层42的形成,导电晶种层42可以由诸如TiN、TaN等的含金属导电材料形成。相应的工艺示出为图77所示的工艺流程200中的工艺208。形成方法可以包括共形沉积方法,诸如ALD、CVD等。接下来,分配牺牲材料44以填充沟槽36。相应的工艺也示出为图77所示的工艺流程200中的工艺208。牺牲材料44可以由光刻胶、聚合物或可以填充沟槽36的其它类型的材料形成。形成方法可以包括旋涂,而其它自下而上的沉积方法也可以使用,只要它可以至少基本完全填充沟槽36。如果使用沉积形成牺牲材料44,则可以实施诸如化学机械抛光(CMP)工艺或机械研磨工艺的平坦化工艺以使牺牲材料44的顶面齐平。
接下来,如图5所示,回蚀刻牺牲材料44,直至剩余的牺牲材料44的顶面低于半导体带30的底端。相应的工艺示出为图77所示的工艺流程200中的工艺210。剩余的牺牲材料44的顶面可以接近沟槽36的侧尖端36A,并且可以高于沟槽36的侧尖端36A,与沟槽36的侧尖端36A齐平或低于沟槽36的侧尖端36A。剩余的牺牲材料44的顶面层级选择为使得随后形成的掩埋接触件48(图7)可以填充沟槽36,其中,沟槽36中具有小的空隙或没有空隙。然后,例如,在各向同性蚀刻工艺中蚀刻导电晶种层42,使得导电晶种层42的上部高于蚀刻的剩余牺牲材料44的顶面,而导电晶种层42的底部由牺牲材料44保护。相应的工艺也示出为图77所示的工艺流程200中的工艺210。在蚀刻工艺之后,去除牺牲材料44,从而产生如图6所示的结构。相应的工艺示出为图77所示的工艺流程200中的工艺212。
图7示出了导电材料46的沉积。相应的工艺示出为图77所示的工艺流程200中的工艺214。例如,沉积工艺可以包括镀。导电材料46的顶面可以高于半导体带30的底部。可选地,导电材料46的顶面可以与半导体带30的底部齐平。在整个说明书中,根据一些实施例,导电材料46和剩余的导电晶种层42统称为掩埋接触件48,其是掩埋菱形接触件。
返回参照图7,虽然示出了单个掩埋接触件48,但是在示出的掩埋接触件48的左侧和连接处可以存在掩埋接触件48,并且在示出的掩埋接触件48的右侧和连接处可以存在掩埋接触件48。图25和图31示出了相邻掩埋接触件48的连接。图38和图41示出了多个掩埋接触件48的顶视图,多个掩埋接触件48与在Y方向上延伸的多条直线对准。如图38和图41所示,与同一直线对准的多个掩埋接触件48(图38和图41)的顶部48A(图7)彼此分隔开,而与同一直线对准的多个掩埋接触件48(图38和图41)的中间部分48B(图7)互连以形成细长的掩埋接触件。
图8示出了掩埋电源轨50的形成。相应的工艺示出为图77所示的工艺流程200中的工艺216。形成工艺可以包括例如,使用CVD沉积诸如钨、钴等的导电材料,实施平坦化工艺以使沉积的导电材料的顶面齐平,并且回蚀刻导电材料。导电材料的剩余部分包括掩埋电源轨50和导电带51。掩埋电源轨50位于与半导体带30的一些部分相同的层级处。
掩埋电源轨50可以是细长的带,并且多个掩埋电源轨50可以形成为彼此平行,如图38和图41(顶视图)所示,其中,掩埋电源轨50的纵长向方向处于X方向。另一方面,同样如图38和图41所示,当从顶部观察时,掩埋接触件48也可以具有菱形形状。如图38和图41所示,掩埋电源轨50的纵长向方向垂直于互连掩埋接触件48的纵长向方向。
接下来,如图9所示,形成介电层52,随后是蚀刻掩模54的形成。根据本发明的一些实施例,介电层52由氧化硅、氮化硅、氮氧化硅等形成。蚀刻掩模54可以由光刻胶或其它类似材料形成。将蚀刻掩模54图案化为覆盖掩埋电源轨50,并且在半导体带30的一些部分正上方延伸。然后使用蚀刻掩模54蚀刻介电层52和介电层40以限定图案。也蚀刻了导电带51。产生的结构如图10所示。
图11至图15示出了隔离区域的形成,该隔离区域有时称为浅沟槽隔离区域。相应的工艺示出为图77所示的工艺流程200中的工艺218。图11示出了填充区域56的形成,以填充半导体带30之间的剩余沟槽24(图10)。填充区域56可以由沉积的SiN、SiON等形成。然后实施图案化工艺以去除沉积的介电材料的未位于掩埋电源轨50正上方的一些部分。
图12示出了介电层58和60的形成,介电层58和60由彼此不同的介电材料形成。例如,介电层58和60可以分别由氧化硅和氮化硅形成,并且也可以使用其它介电材料。形成方法可以包括诸如ALD或CVD的共形沉积方法。
图13示出了介电材料的沉积,从而形成介电区域62。根据本发明的一些实施例,使用可流动CVD(FCVD)、旋涂、原子层沉积(ALD)、高密度等离子体化学汽相沉积(HDPCVD)、化学汽相沉积(CVD)等来形成介电区域62。介电区域62可以包括含硅氧化物或其它类型的介电材料。介电区域62可以由低k介电材料形成,低k介电材料具有低于约3.5或低于约3.0的介电常数。
参照图14,回蚀刻介电区域62,并且沉积介电层64,并且然后回蚀刻介电层64。介电层64可以由与介电区域60的材料不同的介电材料形成,并且可以具有高于介电区域62的密度的密度。例如,介电层64可以由高k介电材料形成,高k介电材料诸如Hf、Al、Zr、La、Mg、Ba、Ti、Pb的氧化物或硅酸盐以及它们的组合。
图15示出了诸如CMP工艺或机械研磨工艺的平坦化工艺之后的结构。介电层64可以用作平坦化工艺的CMP停止层。介电层58和60的剩余部分以及介电区域62和64统称为STI区域65。同样,半导体带30之间的介电层52和填充区域56的部分也统称为STI区域65。
接下来,参照图16,使介电层40、52、58和60凹进,从而形成凹槽66。因此暴露半导体带30的侧壁。根据本发明的一些实施例,凹槽66的底部高于掩埋电源轨50的顶面。半导体带30的高于凹槽66的底部的部分在下文称为半导体鳍68或突出鳍68。相应的工艺示出为图77所示的工艺流程200中的工艺220。
进一步参照图16,形成伪栅极介电层70。根据本发明的一些实施例,伪栅极电介质70由诸如氧化硅的氧化物形成,并且可以采用诸如氮化硅的其它介电材料/结构。
图17A示出了伪栅电极层72的形成。伪栅电极层72可以例如使用多晶硅形成,并且也可以使用其它材料。然后图案化伪栅电极层72和伪栅极介电层70以形成伪栅极堆叠件74。相应的工艺示出为图77所示的工艺流程200中的工艺222。伪栅极堆叠件74包括伪栅电极层72和伪栅极介电层70,并且形成横跨多个半导体鳍68的细长带。在图案化工艺中,介电层64保护下面的介电区域62免受蚀刻(如图17B所示)。当在图17A所示结构的顶视图中观察时,栅极堆叠件74的纵长向方向垂直于半导体鳍68的纵长向方向。在伪栅电极72和伪栅极介电层70的图案化之后,在伪栅极堆叠件74的侧壁上形成栅极间隔件(未示出,不在示出的平面中)。根据本发明的一些实施例,栅极间隔件由诸如氮化硅、氧化硅、碳氮化硅、氮氧化硅、碳氮氧化硅等的介电材料形成,并且可以具有单层结构或包括多个介电层的多层结构。
图17B示出了与图17A相同的结构,除了图17B是从其中去除伪栅电极72和伪栅极介电层70的平面获得,而图17A是从保留伪栅电极72和伪栅极介电层70的平面获得之外。获得图17A和图17B的平面彼此平行。
图18至图24示出了随后的工艺,并且图18至图24所示的截面图是与图17B所示的参考截面相同的参考截面。因此,如图17A所示的伪栅极堆叠件74不在图18至图24所示的平面中。在蚀刻工艺中去除如图17B所示的硬掩模层28和垫氧化物26,从而形成图18所示的结构。相应的工艺示出为图77所示的工艺流程200中的工艺224。暴露半导体鳍68的顶面和侧壁。然后去除介电层64。
接下来,如图19所示,形成源极/漏极区域76A和76B(统称为源极/漏极区域76)。相应的工艺示出为图77所示的工艺流程200中的工艺226。形成工艺可以包括使半导体鳍68的未由伪栅极堆叠件74(图17A)覆盖的部分凹进以形成凹槽,并且从凹槽外延生长源极/漏极区域。根据本发明的一些实施例,外延区域76包括硅锗、硅或硅碳。取决于产生的FinFET是p型FinFET还是n型FinFET,可以随着外延的进行原位掺杂p型或n型杂质。例如,当产生的FinFET是p型FinFET时,可以生长硅硼(SiB)、硅锗硼(SiGeB)、GeB等。相反地,当产生的FinFET是n型FinFET时,可以生长硅磷(SiP)、硅碳磷(SiCP)、硅等。根据本发明的可选实施例,外延区域76由III-V族化合物半导体形成,III-V族化合物半导体诸如GaAs、InP、GaN、InGaAs、InAlAs、GaSb、AlSb、AlAs、AlP、GaP、它们的组合或它们的多层。源极/漏极区域76水平扩展,并且可以形成小平面。源极/漏极区域76A和76B可以具有相同的导电类型或可以具有相反的导电类型。
图19也示出了接触蚀刻停止层(CESL)78和层间电介质(ILD)80的形成。相应的工艺示出为图77所示的工艺流程200中的工艺228。CESL78可以由氧化硅、氮化硅、碳氮化硅等形成。可以使用例如诸如ALD或CVD的共形沉积方法形成CESL 78。ILD 80可以包括使用例如FCVD、旋涂、CVD或其它沉积方法形成的介电材料。ILD 80也可以由含氧介电材料形成,含氧介电材料可以是基于氧化硅的电介质,诸如正硅酸乙酯(TEOS)氧化物、等离子体增强CVD(PECVD)氧化物(包括SiO2)、磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BSG)、硼掺杂的磷硅酸盐玻璃(BPSG)等。实施诸如化学机械抛光(CMP)工艺或机械研磨工艺的平坦化工艺以使ILD80和伪栅极堆叠件74(图17A)的顶面彼此齐平。
在ILD 80的形成之后,可以用替换栅极堆叠件替换如图17A所示的伪栅极堆叠件74,替换栅极堆叠件示出为图37中的栅极堆叠件130。相应的工艺可以包括蚀刻伪栅极堆叠件74,以在ILD 80中形成凹槽,形成延伸至凹槽中的替换栅极介电层,在栅极介电层上方形成含金属层,以及实施平坦化工艺以去除栅极介电层和含金属层的过量部分,其中,栅极介电层和含金属层的剩余部分分别形成替换栅极电介质和替换栅电极。
在替换栅极堆叠件的形成之后,参照图20,形成接触开口82。相应的工艺示出为图77所示的工艺流程200中的工艺230。接触开口82的形成包括蚀刻CESL 78和ILD 80。此外,也蚀刻了介电层52和填充区域56的位于接触开口82下方并且暴露于接触开口82的部分,直至暴露掩埋电源轨50。也暴露了源极/漏极区域76A。另一方面,源极/漏极区域76B可以由ILD 80覆盖,并且不被暴露。
参照图21,形成源极/漏极硅化物区域84和接触插塞86。相应的工艺示出为图77所示的工艺流程200中的工艺232。为了形成源极/漏极硅化物区域84,沉积金属层(诸如Ti层)并且使金属层延伸至接触开口82中。可以形成金属氮化物覆盖层。然后实施退火工艺以使金属层与源极/漏极区域76A的顶部反应以形成硅化物区域84。接下来,留下先前形成的金属氮化物层不被去除,或去除先前形成的金属氮化物层,随后是新的金属氮化物层(诸如氮化钛层)的沉积。然后在接触开口中填充诸如钨、钴等的填充金属材料,随后平坦化以去除过量的材料,从而形成源极/漏极接触插塞86。由此形成FinFET 100A。
参照图22,例如,在蚀刻工艺中,使接触插塞86凹进。然后用介电材料填充产生的凹槽,该介电材料可以是氮化硅、氮氧化硅、氧化硅等。然后实施平坦化工艺以去除介电材料的过量部分,从而产生介电硬掩模90。
参照图23,形成接触开口92。接触开口92的形成包括蚀刻CESL 78和ILD 80以至少暴露源极/漏极区域76B的顶面。
参照图24,形成源极/漏极硅化物区域94和接触插塞96。源极/漏极硅化物区域94和接触插塞96的形成工艺和材料分别与源极/漏极硅化物区域84和接触插塞86的形成工艺和材料类似。因此不讨论其细节。由此形成FinFET 100B。
接下来,使接触插塞96凹进,并且形成介电掩模98。介电硬掩模98可以由氮化硅、氮氧化硅、氧化硅等形成,并且介电硬掩模90和98可以由相同的介电材料或不同的介电材料形成。接下来,在介电硬掩模98中形成接触插塞102以连接至接触插塞96。然后形成介电层104和金属线106(金属线106是根据一些实施例的前侧电源轨)。相应的工艺示出为图77所示的工艺流程200中的工艺234。根据本发明的一些实施例,介电层104由低k介电材料形成,低k介电材料可以具有低于约3.0的介电常数。金属线106可以包括扩散阻挡层和填充金属。例如,扩散阻挡层可以由TiN、TaN、Ti、Ta等形成。例如,填充金属可以由铜形成。
如图24中的示例性实施例所示,可以形成掩埋电源轨50和前侧电源轨106,并且分别从FinFET的背侧和前侧连接至集成电路器件。随着掩埋电源轨50的形成,需要更少的前侧电源轨106。
根据本发明的一些实施例,掩埋电源轨50的厚度T1在约20nm和约60nm之间的范围内。掩埋电源轨50的宽度W1在约20nm和约40nm之间的范围内。掩埋电源轨50和半导体带30之间的间隔S1在约6nm和约20nm之间的范围内。接触插塞86和半导体带30之间的间隔S2在约6nm和约20nm之间的范围内。
图25至图36示出了从半导体衬底20的背侧延伸至半导体衬底20中以电连接至掩埋接触件48和掩埋电源轨50的通孔的形成。相应的工艺示出为图77所示的工艺流程200中的工艺236。图25至图30示出了通孔型通孔的形成,并且图31至图36示出了沟槽型通孔的形成。图25和图31所示的工艺从图24所示的结构继续。图24所示的一些部件未在图25至图36中示出,并且这些部件可以参照图24和相应的形成工艺找到。而且,图25至图36颠倒示出,而在实际工艺中,晶圆10可以使半导体衬底20的背侧朝上,与图25至图36所示的相反。
参照图25,示出了如图24所示的晶圆10的截面图。也示出了掩埋电源轨50和掩埋接触件48。接下来,如图26所示,形成并且图案化蚀刻掩模110,其可以是光刻胶。如图27所示,使用蚀刻掩模110蚀刻半导体衬底20以限定图案,从而形成通孔开口112。通孔开口112穿透半导体衬底20,并且介电层40暴露于通孔开口112。然后蚀刻介电层40的暴露部分以露出掩埋接触件48,并且产生的结构如图28所示。也可以蚀刻掩埋接触件48的底部尖端部分。然后去除如图26所示的光刻胶110。而且,在通孔开口112的侧壁上形成介电衬垫114。介电衬垫114可以由氧化物、氮化物等形成。形成工艺可以包括毯式沉积共形介电层,以及实施各向异性蚀刻以去除共形介电层的水平部分。
图29示出了用导电材料填充接触开口112以形成通孔116。通孔116可以由钨、铜、钴等形成,并且可以包括或不包括由氮化钛、氮化钽、钛、钽等形成的阻挡层。通孔116与掩埋接触件48物理接触,并且接触区域的宽度CW1大于半导体带30之间的间隔CW2。例如,比率CW1/CW2可以大于约2,并且可以在约2和约10之间的范围内。因此,未对准的可能性非常低。作为比较,如果没有形成掩埋接触件48,则将形成从半导体衬底20的背面延伸至位于掩埋电源轨50上的通孔。因此更可能存在未对准问题,并且如果发生未对准,则相应的通孔可能位于半导体带30上,导致高泄漏电流和/或器件故障。
图30示出了介电层118和128、金属通孔120和124以及金属线122和126的形成。金属线122和126以及通孔120和124电连接至通孔116、掩埋接触件48和掩埋电源轨50,掩埋电源轨50进一步连接至FinFET,诸如FinFET的源极/漏极区域。
图31至图36示出了沟槽型通孔的形成。工艺细节与图25至图30所示的工艺类似,除了产生的通孔116具有带状(细长)形状之外。图31示出了如图24所示的结构,除了多个掩埋接触件48示出为彼此连接为细长带之外。接下来,如图32所示,形成并且图案化光刻胶110。通过光刻胶110中的开口露出半导体衬底20的图示部分。接下来,参照图33,通过蚀刻半导体衬底20(在图示区域中未示出)形成沟槽112’。在图34中,蚀刻介电层40的暴露部分以露出掩埋接触件48。在随后的工艺中,如图35所示,形成与图28所示的介电衬垫114类似的介电衬垫(图示区域中未示出),随后是通孔116的形成。图36示出了介电层118和128、通孔120和124以及金属线122和126的形成。
图41示出了根据一些实施例的图36所示的结构的底视图。通孔116形成为位于多个掩埋接触件48上的细长通孔,该多个掩埋接触件48互连为细长接触件。因此,每个通孔116均连接至多个菱形掩埋接触件48。
图37示出了图24所示结构的部分的布局,其中,半导体鳍68在X方向上具有纵长向方向,并且栅极堆叠件130在Y方向上具有纵长向方向。掩埋电源轨50通过接触插塞86电连接至源极/漏极区域76A。在图37的右侧,示出了多条金属线106,其位于FinFET上面的金属层中。金属线106实际上在图37的左侧部分上的区域正上方延伸,并且可以通过接触插塞96电连接至源极/漏极区域76B。
图38示出了具有通孔型通孔的结构(图30)的底视图,其中,示出了掩埋电源轨50、背侧金属线122和126以及通孔116。背侧金属线122和126可以用作VDD电源线和VSS电源线。通孔116形成为离散通孔,其可以具有包括但不限于正方形、圆形、六边形等形状。
图39和图40分别示出了从图38中的参考截面39-39和40-40获得的截面图。参照图40(以及图43),掩埋电源轨50的底部至半导体衬底20的背面之间的距离D1可以在约0.5μm和约2.5μm之间的范围内。距离D1也是掩埋接触件48和通孔116的组合高度。菱形掩埋接触件48的相对尖端之间的距离D2可以在约150nm和约400nm之间的范围内。菱形掩埋接触件48的倾斜侧壁的倾斜角α1可以在约53°和约56°之间的范围内。
图41示出了具有沟槽型通孔的结构的底视图。图42和图43分别示出了从图41中的参考截面42-42和43-43获得的截面图。示出的结构与图38至图40所示的结构类似,除了形成细长通孔116之外。因此,此处不再重复细节。
图44至图67示出了根据本发明的可选实施例的FinFET、掩埋电源轨和掩埋接触件的形成中的中间阶段的截面图。除非另有说明,否则这些实施例中的组件的材料和形成工艺与相同的组件基本相同,其由图1至图24所示的实施例中的相同参考标号标记,除了形成蚀刻停止层(例如,硅锗(SiGe)层),使得在随后的沟槽的形成中,采用各向同性蚀刻工艺,而不是各向异性蚀刻工艺以及随后的各向同性蚀刻工艺(如图2所示)之外。因此,除非另有说明,否则关于图44至图67所示的组件的形成工艺和材料的细节可以在图1至图24所示的实施例的讨论中找到。
参照图44,形成半导体衬底20。半导体衬底20可以包括半导体层20A、位于半导体层20A上方的半导体层20B以及位于SiGe层20B上方的半导体层20C。半导体层20B可以是硅锗(SiGe)层或另一类型的晶体材料(诸如半导体材料),其可以相对于半导体层20A和半导体层20C具有足够的蚀刻选择性。在随后的讨论中,半导体层20B称为SiGe层20B,而半导体层20B可以由其它材料形成。SiGe层20B和半导体层20C可以通过外延形成。根据本发明的一些实施例,半导体层20A和半导体层20C由其中可以不含锗的晶体硅形成。半导体层20B可以由晶体SiGe形成。SiGe层20B的锗原子百分比可以在约30%和约100%之间的范围内。根据本发明的一些实施例,SiGe层20B的厚度在约5nm和约50nm之间的范围内。半导体层20C也可以由诸如III-V族化合物半导体材料的其它类型的半导体材料形成。
参照图45,形成图案化的垫氧化物层26和硬掩模层28。然后使用图案化的硬掩模层28作为蚀刻掩模蚀刻半导体层20C,形成如图45所示的半导体带30。在蚀刻工艺中,SiGe层20B用作蚀刻停止层,并且暴露SiGe层20B的顶面。蚀刻选择性(即半导体层20C的蚀刻速率与SiGe层20B的蚀刻速率的比率)足够高,使得SiGe层20B基本未被损坏。例如,蚀刻选择性可以高于约20或高于约50。图46也示出了共形介电层32的形成,其通过诸如ALD或CVD的共形沉积方法形成。
接下来,如图47所示,形成图案化的蚀刻掩模34,并且图案化的蚀刻掩模34覆盖半导体带30,并且去除蚀刻掩模34的位于相邻带30之间的部分。然后实施蚀刻工艺以蚀刻介电层32的暴露部分和下面的SiGe层20B的部分,从而产生图48所示的结构。在蚀刻工艺中,半导体层20A用作蚀刻停止层,使得它的顶面暴露。因此形成延伸至SiGe层20B中的沟槽36。如果从顶部观察,沟槽36是与直线对准(图74)的多个离散沟槽36中的一个。沟槽36的顶视图形状可以选自但不限于正方形、矩形、圆形等。而且,参照图74,其是晶圆10的底视图,离散沟槽36的位置将与在Y方向上延伸的直线对准。在蚀刻工艺之后,去除蚀刻掩模34(图47)。
参照图48,根据本发明的一些实施例,实施氧化工艺。可以在含氧(O2)的环境(诸如其中包含空气的烘箱)中实施氧化。可以在约400℃和约700℃之间的范围内的温度下实施氧化。由于氧化工艺,形成硅锗氧化物(SiGeO)区域37。如果在顶视图中观察,硅锗氧化物区域37形成环绕沟槽36的整个圆。根据本发明的一些实施例,硅锗氧化物区域37的宽度W2可以在约1nm和约30nm之间的范围内。根据可选实施例,跳过氧化工艺。根据一些实施例,硅锗氧化物区域37示出为虚线,以指示它们可以形成或可以不形成。虽然氧化物也形成在半导体层20A的表面上,但是当半导体层20A由硅形成时,其氧化速率显著低于SiGe的氧化速率,因此未在图48中示出产生的氧化硅。
参照图49,例如,使用侵蚀半导体层20A的蚀刻气体或蚀刻溶液来蚀刻半导体层20A,但是不侵蚀SiGe层20B和介电层32。因此,沟槽36向下延伸至半导体层20A中。蚀刻是各向同性的。由于在各向同性蚀刻之前没有实施各向异性蚀刻,所以沟槽36的侧壁(未示出)和底部圆化,而不是在(111)表面平面上。在各向同性蚀刻中,硅锗氧化物区域37和SiGe层20B用作保护层以保护半导体带30免受蚀刻。此外,硅锗氧化物区域37可以具有比SiGe层20B更低的蚀刻速率。锗氧化物区域37和SiGe层20B的底面暴露于沟槽36。如图74所示,相邻的沟槽36互连以形成在Y方向上延伸的细长带。
接下来,如图50所示,去除介电层32,并且形成介电层40。介电层40形成为共形层(例如,使用ALD),其保护硅锗氧化物区域37和SiGe层20B的侧壁和底面。此外,块状半导体衬底20的顶面(其顶面暴露于沟槽36)也由介电层40保护。
图51示出了导电晶种层42和牺牲材料44的形成。可以使用ALD或CVD形成导电晶种层42。牺牲材料44可以基本完全填充沟槽36,并且可以进一步使半导体带30嵌入在其内。
图52示出了牺牲材料44的凹进。剩余的牺牲材料44的顶面低于SiGe层20B的底面。完全去除牺牲材料44的位于沟槽36外部的部分,并且将牺牲材料的底部留在沟槽36中。接下来,蚀刻导电晶种层42。由牺牲材料44保护的导电晶种层42的底部不被蚀刻,并且在蚀刻之后保留,同时去除导电晶种层42的未保护部分。接下来,去除剩余的牺牲材料44,并且产生的结构如图53所示。
图54示出了导电材料46的形成,导电材料46可以通过镀形成。导电材料46填充沟槽36。因此,形成掩埋接触件48,其包括导电晶种层42和导电材料46。根据本发明的一些实施例,掩埋接触件48的顶面与SiGe层20B的顶面齐平或高于SiGe层20B的顶面。
参照图55,例如通过沉积、可能的平坦化和回蚀刻工艺形成掩埋电源轨50和导电带51。因此,掩埋电源轨50的至少一部分(可能整体)与半导体带30的下部处于相同的层级。
参照图56,介电层52沉积为共形层。然后形成并且图案化蚀刻掩模54。在随后的工艺中,如图57所示,蚀刻多个层和区域。在蚀刻工艺中,首先使用蚀刻掩模54来蚀刻介电层52的暴露部分,并且因此露出下面的导电带51。然后蚀刻露出的导电带51。接下来,也蚀刻了下面的介电层40暴露的部分。因此暴露SiGe层20B的顶面。
参照图58,填充区域56用于填充相邻半导体带30之间的凹槽。然后,如图59所示,形成介电层58和60。接下来,介电区域62形成为具有如图60所示的平坦顶面,随后使介电区域62凹进,填充和平坦化介电层64,并且回蚀刻介电层64。产生的结构如图61所示。
图62示出了平坦化工艺,其中介电层64用作停止层以停止平坦化。接下来,如图63所示,使介电层40、52、58和60凹进,从而形成凹槽66。因此暴露出半导体带30的侧壁。根据本发明的一些实施例,凹槽66的底部高于掩埋电源轨50的顶面。半导体带30的高于凹槽66的底部的部分在下文称为半导体鳍68或突出鳍68。
图64A示出了伪栅极堆叠件74的形成,伪栅极堆叠件74包括伪栅极电介质70和伪栅电极72。图64B示出了与图64A所示的相同的结构,除了图64A所示的截面图从包含伪栅极堆叠件74的平面获得,而图64B所示的截面图从不包括伪栅极堆叠件74的平面获得之外。
然后去除如图64B所示的垫氧化物层26和硬掩模层28,并且产生的结构如图65所示。然后去除介电层64。接下来,如图66所示,形成源极/漏极区域76(包括76A和76B),随后是CESL 78和ILD 80的形成。在图67中,蚀刻ILD 80和CESL 78,并且在源极/漏极区域76A上形成源极/漏极硅化物区域84。形成接触插塞86以将源极/漏极硅化物区域84电连接至掩埋电源轨50。介电硬掩模90形成为覆盖接触插塞86。在源极/漏极区域76B上形成源极/漏极硅化物区域94。接触插塞96形成为电连接至源极/漏极硅化物区域94。介电硬掩模98形成为覆盖接触插塞96。然后形成接触插塞102、介电层104和金属线106(金属线106可以是前侧电源轨)。接触插塞96将源极/漏极硅化物区域94电连接至前侧电源轨106。因此形成FinFET100A和100B。
根据本发明的一些实施例,掩埋电源轨50的厚度T1在约15nm和约60nm之间的范围内。掩埋电源轨50的宽度W1在约15nm和约40nm之间的范围内。掩埋电源轨50和最接近的半导体带30之间的间隔S1在约6nm和约20nm之间的范围内。接触插塞86和最接近的半导体带30之间的间隔S2在约6nm和约20nm之间的范围内。
图68至图73示出了穿透半导体衬底20以连接至掩埋接触件48的通孔的形成。图68示出了与图67相同的结构,其中一些细节未示出,其细节可以从图67和相应的形成工艺中找到。参照图69,在半导体衬底20的背侧上形成蚀刻掩模110。接下来,如图70所示,蚀刻半导体衬底20以形成通孔开口112’,然后去除蚀刻掩模110。图71示出了介电层40的蚀刻以暴露掩埋接触件48。接下来,如图72所示,形成通孔116。可以在掩埋接触件48的圆化底面之间留下半导体层20A的一些部分。图73示出了介电层118和128、金属通孔120和124以及金属线122和126的形成。金属线122和126以及通孔120和124连接至通孔116、掩埋接触件48和掩埋电源轨50,掩埋电源轨50进一步连接至FinFET,诸如FinFET的源极/漏极区域。
图68至图73示出了沟槽型通孔116的形成。根据本发明的可选实施例,可以形成通孔型通孔。除了沟槽36(和掩埋接触件48)形成为圆化表面而不是具有菱形形状之外,形成工艺和产生的结构与图25至图30所示的那些基本相同。
图74示出了具有沟槽型通孔116的结构的底视图,其中,示出了用作VDD电源线和VSS电源线的掩埋电源轨50、通孔116、背侧金属线122。
图75和图76分别示出了从图74中的参考截面75-75和76-76获得的截面图。参照图76,掩埋电源轨50的底部和半导体衬底20的背面之间的距离D3可以在约0.5μm和约2.5μm之间的范围内。距离D3也是掩埋接触件48和通孔116的组合高度。圆化的掩埋接触件48的直径D4可以在约100nm和约400nm之间的范围内。
本发明的实施例具有一些有利特征。掩埋电源轨可以替换一些前侧电源轨,并且减小前侧电源轨的密度。如果没有形成掩埋接触件,则难以将通孔与掩埋电源轨对准,并且如果发生未对准,则可能损坏半导体带。通过形成比相应的上面的掩埋电源轨宽的掩埋接触件,半导体衬底中的通孔可以容易地位于掩埋接触件上,并且消除了未对准问题。
根据本发明的一些实施例,形成集成电路结构的方法包括蚀刻半导体衬底以形成两个半导体带,其中,两个半导体带均位于半导体衬底的主体部分上方;蚀刻主体部分以在半导体衬底的主体部分中形成沟槽;形成内衬沟槽的衬垫介电层;在沟槽中形成掩埋接触件;在掩埋接触件上方形成连接至掩埋接触件的掩埋电源轨,其中,掩埋电源轨位于两个半导体带之间;以及在两个半导体带的相对侧上形成隔离区域,其中,掩埋电源轨位于隔离区域的部分下面。在实施例中,掩埋电源轨与两个半导体带的部分处于相同的层级。在实施例中,该方法还包括使隔离区域凹进,其中两个半导体带的顶部突出高于隔离区域的剩余部分的顶面,以形成第一半导体鳍和第二导体鳍;基于第一半导体鳍形成第一源极/漏极区域;以及形成接触插塞,以将第一源极/漏极区域电连接至掩埋电源轨和掩埋接触件。在实施例中,隔离区域的剩余部分的顶面高于掩埋电源轨的顶面。在实施例中,形成接触插塞包括蚀刻隔离区域的部分以形成接触开口,其中,掩埋电源轨暴露于接触开口;以及填充接触开口以形成接触插塞。在实施例中,形成掩埋接触件包括:形成内衬沟槽的晶种层,其中,晶种层位于衬垫介电层上;去除晶种层的顶部,其中,保留晶种层的底部;以及从晶种层的底部开始镀导电材料。在实施例中,蚀刻主体部分以形成沟槽包括:实施各向异性蚀刻以形成延伸至主体部分中的沟槽的部分;以及实施各向同性蚀刻以扩展沟槽,其中,在扩展之后,沟槽具有菱形截面图形状。在实施例中,半导体衬底包括:第一半导体层;位于第一半导体层上方的硅锗层;位于硅锗层上方的第二半导体层,其中,蚀刻半导体衬底包括蚀刻第二半导体层并且停止在硅锗层上。在实施例中,蚀刻主体部分以形成沟槽包括:蚀刻穿过硅锗层;以及实施氧化以氧化硅锗层的部分。
根据本发明的一些实施例,形成集成电路结构的方法包括在半导体衬底的主体部分上方形成第一半导体带和第二半导体带;在第一半导体带和第二半导体带之间形成掩埋电源轨,其中,掩埋电源轨与第一半导体带的第一部分处于相同的层级;基于第一半导体带的第二部分形成源极/漏极区域,其中,第二部分高于第一部分;形成延伸至半导体衬底的主体部分中的掩埋接触件;蚀刻半导体衬底的主体部分以形成接触开口,其中,掩埋接触件暴露于接触开口;以及填充接触开口以形成通孔,其中,通孔通过掩埋接触件电连接至掩埋电源轨。在实施例中,该方法还包括形成将源极/漏极区域电连接至掩埋电源轨的接触插塞。在实施例中,形成掩埋接触件包括:从半导体衬底的前侧蚀刻主体部分,以形成延伸至半导体衬底的主体部分中的沟槽;以及用导电材料填充沟槽以形成掩埋接触件。在实施例中,蚀刻主体部分包括:实施各向异性蚀刻以形成延伸至主体部分中的沟槽的部分;以及实施各向同性蚀刻以扩展沟槽,其中,该沟槽具有菱形截面图形状。在实施例中,使用各向同性蚀刻来实施蚀刻主体部分,以及在蚀刻之后将半导体衬底的主体部分中的硅锗层暴露于沟槽。在实施例中,掩埋接触件形成为在掩埋接触件的截面图中具有菱形形状。在实施例中,该方法还包括在主体部分中形成多个附加掩埋接触件,其中,多个附加掩埋接触件与掩埋接触件连接以形成细长接触件。
根据本发明的一些实施例,集成电路结构包括块状半导体衬底;位于块状半导体衬底上方并且连接至块状半导体衬底的第一半导体带和第二半导体带;位于第一半导体带和第二半导体带之间的掩埋电源轨,其中,掩埋电源轨与第一半导体带的第一部分处于相同的层级;延伸至块状半导体衬底中并且电连接至掩埋电源轨的掩埋接触件;以及从块状半导体衬底的背面延伸至掩埋接触件的通孔。在实施例中,掩埋接触件包括与第一半导体带和第二半导体带之间的间隔重叠的第一部分;以及分别与第一半导体带和第二半导体带重叠的第二部分和第三部分。在实施例中,掩埋接触件具有菱形形状,并且菱形形状的顶部与掩埋电源轨的底面接触。在实施例中,掩埋接触件具有圆化表面。
上面概述了若干实施例的特征,使得本领域人员可以更好地理解本发明的方面。本领域人员应该理解,它们可以容易地使用本发明作为基础来设计或修改用于实施与本文所介绍实施例相同的目的和/或实现相同优势的其它工艺和结构。本领域技术人员也应该意识到,这种等同构造并不背离本发明的精神和范围,并且在不背离本发明的精神和范围的情况下,本文中它们可以做出多种变化、替换以及改变。
Claims (10)
1.一种形成集成电路结构的方法,所述方法包括:
蚀刻半导体衬底以形成两个半导体带,其中,所述两个半导体带均位于所述半导体衬底的主体部分上方;
蚀刻所述主体部分以在所述半导体衬底的主体部分中形成沟槽;
形成内衬所述沟槽的衬垫介电层;
在所述沟槽中形成掩埋接触件;
在所述掩埋接触件上方形成连接至所述掩埋接触件的掩埋电源轨,其中,所述掩埋电源轨位于所述两个半导体带之间;以及
在所述两个半导体带的相对侧上形成隔离区域,其中,所述掩埋电源轨位于所述隔离区域的部分下面。
2.根据权利要求1所述的方法,其中,所述掩埋电源轨与所述两个半导体带的部分处于相同的层级。
3.根据权利要求1所述的方法,还包括:
使所述隔离区域凹进,其中,所述两个半导体带的顶部突出高于所述隔离区域的剩余部分的顶面,以形成第一半导体鳍和第二导体鳍;
基于所述第一半导体鳍形成第一源极/漏极区域;以及
形成接触插塞,以将所述第一源极/漏极区域电连接至所述掩埋电源轨和所述掩埋接触件。
4.根据权利要求3所述的方法,其中,所述隔离区域的剩余部分的顶面高于所述掩埋电源轨的顶面。
5.根据权利要求3所述的方法,其中,形成所述接触插塞包括:
蚀刻所述隔离区域的部分以形成接触开口,其中,所述掩埋电源轨暴露于所述接触开口;以及
填充所述接触开口以形成所述接触插塞。
6.根据权利要求1所述的方法,其中,形成所述掩埋接触件包括:
形成内衬所述沟槽的晶种层,其中,所述晶种层位于所述衬垫介电层上;
去除所述晶种层的顶部,其中,保留所述晶种层的底部;以及
从所述晶种层的底部开始镀导电材料。
7.根据权利要求1所述的方法,其中,蚀刻所述主体部分以形成所述沟槽包括:
实施各向异性蚀刻以形成延伸至所述主体部分中的所述沟槽的部分;以及
实施各向同性蚀刻以扩展所述沟槽,其中,在所述扩展之后,所述沟槽具有菱形截面图形状。
8.根据权利要求1所述的方法,其中,所述半导体衬底包括:
第一半导体层;
硅锗层,位于所述第一半导体层上方;以及
第二半导体层,位于所述硅锗层上方,其中,蚀刻所述半导体衬底包括蚀刻所述第二半导体层并且停止在所述硅锗层上。
9.一种形成集成电路结构的方法,所述方法包括:
在半导体衬底的主体部分上方形成第一半导体带和第二半导体带;
在所述第一半导体带和所述第二半导体带之间形成掩埋电源轨,其中,所述掩埋电源轨与所述第一半导体带的第一部分处于相同的层级;
基于所述第一半导体带的第二部分形成源极/漏极区域,其中,所述第二部分高于所述第一部分;
形成延伸至所述半导体衬底的主体部分中的掩埋接触件;
蚀刻所述半导体衬底的主体部分以形成接触开口,其中,所述掩埋接触件暴露于所述接触开口;以及
填充所述接触开口以形成通孔,其中,所述通孔通过所述掩埋接触件电连接至所述掩埋电源轨。
10.一种集成电路结构,包括:
块状半导体衬底;
第一半导体带和第二半导体带,位于所述块状半导体衬底上方并且连接至所述块状半导体衬底;
掩埋电源轨,位于所述第一半导体带和所述第二半导体带之间,其中,所述掩埋电源轨与所述第一半导体带的第一部分处于相同的层级;
掩埋接触件,延伸至所述块状半导体衬底中并且电连接至所述掩埋电源轨;以及
通孔,从所述块状半导体衬底的背面延伸至所述掩埋接触件。
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US201862750944P | 2018-10-26 | 2018-10-26 | |
US62/750,944 | 2018-10-26 | ||
US16/293,858 US10872818B2 (en) | 2018-10-26 | 2019-03-06 | Buried power rail and method forming same |
US16/293,858 | 2019-03-06 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN111106059A true CN111106059A (zh) | 2020-05-05 |
CN111106059B CN111106059B (zh) | 2022-08-05 |
Family
ID=70327678
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201911015432.9A Active CN111106059B (zh) | 2018-10-26 | 2019-10-24 | 集成电路结构和形成集成电路结构的方法 |
Country Status (5)
Country | Link |
---|---|
US (1) | US10872818B2 (zh) |
KR (1) | KR102209956B1 (zh) |
CN (1) | CN111106059B (zh) |
DE (1) | DE102019106763B4 (zh) |
TW (1) | TWI715266B (zh) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2023040722A1 (en) * | 2021-09-14 | 2023-03-23 | International Business Machines Corporation | Buried power rail for semiconductors |
WO2024125247A1 (en) * | 2022-12-14 | 2024-06-20 | International Business Machines Corporation | Improved contact structure for power delivery on semiconductor device |
Families Citing this family (39)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10700207B2 (en) * | 2017-11-30 | 2020-06-30 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor device integrating backside power grid and related integrated circuit and fabrication method |
US11171142B2 (en) * | 2018-11-16 | 2021-11-09 | International Business Machines Corporation | Integrated circuit with vertical structures on nodes of a grid |
US11164879B2 (en) * | 2018-11-16 | 2021-11-02 | International Business Machines Corporation | Microelectronic device with a memory element utilizing stacked vertical devices |
US11183419B2 (en) * | 2020-03-17 | 2021-11-23 | International Business Machines Corporation | Unconfined buried interconnects |
KR102436689B1 (ko) * | 2020-05-11 | 2022-08-25 | 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 | 후면 측 전력 레일 디바이스를 위한 캐패시턴스 감소 |
US11289606B2 (en) | 2020-05-11 | 2022-03-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Capacitance reduction for back-side power rail device |
KR20210138995A (ko) * | 2020-05-13 | 2021-11-22 | 삼성전자주식회사 | 표준 셀을 포함하는 집적 회로, 및 이를 제조하기 위한 방법 |
KR102674033B1 (ko) * | 2020-05-29 | 2024-06-13 | 삼성전자주식회사 | 반도체 장치 |
EP4154308A1 (en) * | 2020-06-25 | 2023-03-29 | Huawei Technologies Co., Ltd. | Semiconductor device, semiconductor die, and method of manufacturing a semiconductor device |
US11393819B2 (en) * | 2020-07-09 | 2022-07-19 | Qualcomm Incorporated | Semiconductor device implemented with buried rails |
US11728244B2 (en) * | 2020-07-17 | 2023-08-15 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and method for forming the same |
US20220028758A1 (en) * | 2020-07-23 | 2022-01-27 | Qualcomm Incorporated | Backside power distribution network (pdn) processing |
US11984488B2 (en) | 2020-07-31 | 2024-05-14 | Taiwan Semiconductor Manufacturing Co., Ltd. | Multigate device with air gap spacer and backside rail contact and method of fabricating thereof |
KR20220017023A (ko) * | 2020-08-03 | 2022-02-11 | 삼성전자주식회사 | 반도체 소자 및 반도체 패키지 |
US11948886B2 (en) * | 2020-10-23 | 2024-04-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and methods of manufacturing same |
US20220130968A1 (en) * | 2020-10-27 | 2022-04-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuit, system and method of forming same |
US11769728B2 (en) * | 2020-11-13 | 2023-09-26 | Samsung Electronics Co., Ltd. | Backside power distribution network semiconductor package and method of manufacturing the same |
KR20220096442A (ko) | 2020-12-31 | 2022-07-07 | 삼성전자주식회사 | 반도체 장치 |
US20220336355A1 (en) * | 2021-04-19 | 2022-10-20 | Samsung Electronics Co., Ltd. | Thermal budget enhanced buried power rail and method of manufacturing the same |
US11915966B2 (en) * | 2021-06-09 | 2024-02-27 | International Business Machines Corporation | Backside power rail integration |
US20230032866A1 (en) * | 2021-07-27 | 2023-02-02 | Intel Corporation | Self-aligned lateral contacts |
US11735513B2 (en) * | 2021-08-05 | 2023-08-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated chip having a back-side power rail |
US20230043634A1 (en) * | 2021-08-06 | 2023-02-09 | Taiwan Semiconductor Manufacturing Company Ltd. | Photonic structure and semiconductor structure and method for manufacturing the same |
EP4135016A1 (en) * | 2021-08-11 | 2023-02-15 | Imec VZW | A method for producing a buried interconnect rail of an integrated circuit chip |
US11804436B2 (en) | 2021-09-03 | 2023-10-31 | International Business Machines Corporation | Self-aligned buried power rail cap for semiconductor devices |
US11830774B2 (en) * | 2021-09-23 | 2023-11-28 | International Business Machines Corporation | Buried contact through fin-to-fin space for vertical transport field effect transistor |
US11990412B2 (en) * | 2021-09-29 | 2024-05-21 | International Business Machines Corporation | Buried power rails located in a base layer including first, second, and third etch stop layers |
US20230132353A1 (en) * | 2021-10-26 | 2023-04-27 | International Business Machines Corporation | Semiconductor device with early buried power rail (bpr) and backside power distribution network (bspdn) |
US20230163020A1 (en) * | 2021-11-22 | 2023-05-25 | International Business Machines Corporation | Buried power rail after replacement metal gate |
EP4187581A1 (en) * | 2021-11-26 | 2023-05-31 | Imec VZW | An interconnect structure of a semiconductor component and methods for producing said structure |
US20230187353A1 (en) * | 2021-12-15 | 2023-06-15 | Intel Corporation | Signal routing using structures based on buried power rails |
US20230197613A1 (en) * | 2021-12-20 | 2023-06-22 | Intel Corporation | Replacement via and buried or backside power rail |
US20230207622A1 (en) * | 2021-12-23 | 2023-06-29 | International Business Machines Corporation | Semiconductor structure having stacked power rails |
US20230207466A1 (en) * | 2021-12-24 | 2023-06-29 | Leonard P. GULER | Recessed and self-aligned buried power rail |
US20230207468A1 (en) * | 2021-12-28 | 2023-06-29 | International Business Machines Corporation | Stacked staircase cmos with buried power rail |
US20230207697A1 (en) * | 2021-12-29 | 2023-06-29 | International Business Machines Corporation | Buried power rail formation for vertical field effect transistors |
US20230253322A1 (en) * | 2022-02-09 | 2023-08-10 | International Business Machines Corporation | Nano-tsv landing over buried power rail |
US20230299000A1 (en) * | 2022-03-17 | 2023-09-21 | International Business Machines Corporation | Method and structure for forming landing for backside power distribution network |
KR102619817B1 (ko) * | 2022-05-19 | 2024-01-02 | 세메스 주식회사 | 반도체 소자의 형성 방법 및 반도체 소자의 형성을 위한 기판 처리 시스템 |
Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6566177B1 (en) * | 1999-10-25 | 2003-05-20 | International Business Machines Corporation | Silicon-on-insulator vertical array device trench capacitor DRAM |
US20120086064A1 (en) * | 2010-10-07 | 2012-04-12 | International Business Machines Corporation | Method of forming enhanced capacitance trench capacitor |
US20150162337A1 (en) * | 2013-12-06 | 2015-06-11 | International Business Machines Corporation | Pattern factor dependency alleviation for edram and logic devices with disposable fill to ease deep trench integration with fins |
CN104952924A (zh) * | 2014-03-28 | 2015-09-30 | 台湾积体电路制造股份有限公司 | 具有低源极/漏极接触电阻的FinFET |
US20150371893A1 (en) * | 2014-06-18 | 2015-12-24 | International Business Machines Corporation | Buried signal transmission line |
CN107680943A (zh) * | 2016-08-02 | 2018-02-09 | 台湾积体电路制造股份有限公司 | 多层膜器件及方法 |
CN108288604A (zh) * | 2017-01-09 | 2018-07-17 | 台湾积体电路制造股份有限公司 | 接触插塞及其制造方法 |
TWI638441B (zh) * | 2017-08-31 | 2018-10-11 | 台灣積體電路製造股份有限公司 | 積體電路及其製造方法 |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US446555A (en) * | 1891-02-17 | Machine for cutting soles | ||
US6583045B1 (en) | 2001-11-16 | 2003-06-24 | Taiwan Semiconductor Manufacturing Company | Chip design with power rails under transistors |
US9318607B2 (en) | 2013-07-12 | 2016-04-19 | Samsung Electronics Co., Ltd. | Semiconductor device and method of fabricating the same |
KR102154188B1 (ko) * | 2014-08-26 | 2020-09-09 | 삼성전자 주식회사 | 신호 배선의 상부로 연장된 랜딩 패드가 선택적으로 배치된 메모리 소자 |
EP3139405B1 (en) | 2015-09-01 | 2021-08-11 | IMEC vzw | Buried interconnect for semicondutor circuits |
US9570395B1 (en) * | 2015-11-17 | 2017-02-14 | Samsung Electronics Co., Ltd. | Semiconductor device having buried power rail |
US10141443B2 (en) | 2016-03-24 | 2018-11-27 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor devices FinFET devices with optimized strained-sourece-drain recess profiles and methods of forming the same |
EP3229270A1 (en) | 2016-04-06 | 2017-10-11 | IMEC vzw | Integrated circuit power distribution network |
US9917059B2 (en) | 2016-06-03 | 2018-03-13 | International Business Machines Corporation | Self-aligned vertical transistor with local interconnect |
TWI744358B (zh) | 2016-07-19 | 2021-11-01 | 日商東京威力科創股份有限公司 | 三維半導體裝置及其製造方法 |
EP3324436B1 (en) | 2016-11-21 | 2020-08-05 | IMEC vzw | An integrated circuit chip with power delivery network on the backside of the chip |
US9831317B1 (en) | 2017-03-02 | 2017-11-28 | Globalfoundries Inc. | Buried contact structures for a vertical field-effect transistor |
US10475692B2 (en) | 2017-04-07 | 2019-11-12 | Globalfoundries Inc. | Self aligned buried power rail |
CN108305835A (zh) | 2018-03-19 | 2018-07-20 | 中国科学院微电子研究所 | 一种鳍式晶体管器件的制造方法 |
-
2019
- 2019-03-06 US US16/293,858 patent/US10872818B2/en active Active
- 2019-03-18 DE DE102019106763.4A patent/DE102019106763B4/de active Active
- 2019-06-07 KR KR1020190067236A patent/KR102209956B1/ko active IP Right Grant
- 2019-10-24 CN CN201911015432.9A patent/CN111106059B/zh active Active
- 2019-10-25 TW TW108138505A patent/TWI715266B/zh active
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6566177B1 (en) * | 1999-10-25 | 2003-05-20 | International Business Machines Corporation | Silicon-on-insulator vertical array device trench capacitor DRAM |
US20120086064A1 (en) * | 2010-10-07 | 2012-04-12 | International Business Machines Corporation | Method of forming enhanced capacitance trench capacitor |
US20150162337A1 (en) * | 2013-12-06 | 2015-06-11 | International Business Machines Corporation | Pattern factor dependency alleviation for edram and logic devices with disposable fill to ease deep trench integration with fins |
CN104952924A (zh) * | 2014-03-28 | 2015-09-30 | 台湾积体电路制造股份有限公司 | 具有低源极/漏极接触电阻的FinFET |
US20150371893A1 (en) * | 2014-06-18 | 2015-12-24 | International Business Machines Corporation | Buried signal transmission line |
CN107680943A (zh) * | 2016-08-02 | 2018-02-09 | 台湾积体电路制造股份有限公司 | 多层膜器件及方法 |
CN108288604A (zh) * | 2017-01-09 | 2018-07-17 | 台湾积体电路制造股份有限公司 | 接触插塞及其制造方法 |
TWI638441B (zh) * | 2017-08-31 | 2018-10-11 | 台灣積體電路製造股份有限公司 | 積體電路及其製造方法 |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2023040722A1 (en) * | 2021-09-14 | 2023-03-23 | International Business Machines Corporation | Buried power rail for semiconductors |
GB2625643A (en) * | 2021-09-14 | 2024-06-26 | Ibm | Buried power rail for semiconductors |
WO2024125247A1 (en) * | 2022-12-14 | 2024-06-20 | International Business Machines Corporation | Improved contact structure for power delivery on semiconductor device |
Also Published As
Publication number | Publication date |
---|---|
KR102209956B1 (ko) | 2021-02-02 |
TWI715266B (zh) | 2021-01-01 |
DE102019106763B4 (de) | 2023-10-26 |
KR20200049468A (ko) | 2020-05-08 |
DE102019106763A1 (de) | 2020-04-30 |
US10872818B2 (en) | 2020-12-22 |
CN111106059B (zh) | 2022-08-05 |
US20200135634A1 (en) | 2020-04-30 |
TW202022990A (zh) | 2020-06-16 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN111106059B (zh) | 集成电路结构和形成集成电路结构的方法 | |
US12034076B2 (en) | Semiconductor device integrating backside power grid and related integrated circuit and fabrication method | |
US11532504B2 (en) | Low-resistance contact plugs and method forming same | |
US11114550B2 (en) | Recessing STI to increase FIN height in FIN-first process | |
CN108807160B (zh) | 半导体器件及其形成方法 | |
CN110416157B (zh) | 晶体管中的空气间隔件及其形成方法 | |
CN108288604B (zh) | 接触插塞及其制造方法 | |
CN109427775B (zh) | 集成电路及其形成方法 | |
CN104952924A (zh) | 具有低源极/漏极接触电阻的FinFET | |
JP7394550B2 (ja) | 半導体装置 | |
US12009265B2 (en) | Slot contacts and method forming same | |
CN113793834B (zh) | 半导体器件及其形成方法 | |
US20230223276A1 (en) | Semiconductor structure and method for forming the same | |
US20230420525A1 (en) | Method for forming semiconductor device | |
US20240072155A1 (en) | Contact plugs and methods forming same | |
US20230411457A1 (en) | Semiconductor device and method of manufacturing thereof | |
CN115939044A (zh) | 在隔离区形成接缝的方法 | |
CN118231406A (zh) | 半导体器件及其形成方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant |