CN108807160B - 半导体器件及其形成方法 - Google Patents

半导体器件及其形成方法 Download PDF

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CN108807160B
CN108807160B CN201711139862.2A CN201711139862A CN108807160B CN 108807160 B CN108807160 B CN 108807160B CN 201711139862 A CN201711139862 A CN 201711139862A CN 108807160 B CN108807160 B CN 108807160B
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layer
metal
cobalt
forming
over
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CN108807160A (zh
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蔡嘉庆
邱意为
许立德
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明的实施例涉及半导体器件及其形成方法，该方法包括形成晶体管，形成晶体管包括在半导体区域上形成栅极电介质，在栅极电介质上方形成栅电极，并且形成延伸至半导体区域内的源极/漏极区域。该方法还包括在源极/漏极区域上方形成电连接至源极/漏极区域的源极/漏极接触插塞，并且在栅电极上方形成与栅电极接触的栅极接触插塞。形成栅电极、形成源极/漏极接触插塞和形成栅极接触插塞的至少一个包括形成金属氮化物阻挡层，并且在金属氮化物阻挡层上方形成与金属氮化物阻挡层接触的含金属层。含金属层包括钴层和金属硅化物层的至少一个。本发明的实施例还涉及具有减小的电阻率的晶体管的金属栅极。

Description

半导体器件及其形成方法
技术领域
本发明的实施例涉及半导体器件及其形成方法。
背景技术
金属氧化物半导体(MOS)器件是集成电路中的基本构建元件。现有的MOS器件通常具有由多晶硅形成的栅电极，使用诸如离子注入或热扩散的掺杂操作使多晶硅掺杂有p型或n型杂质。栅电极的功函数可以调整为硅的带边。对于n型金属氧化物半导体(NMOS)器件，功函数可以调整为接近硅的导电带。对于p型金属氧化物半导体(PMOS)器件，功函数可以调整为接近硅的价带。可以通过选择适当的杂质来实现调整多晶硅栅电极的功函数。
具有多晶硅栅电极的MOS器件显示出载流子耗尽效应，载流子耗尽效应也称为多晶硅耗尽效应。当施加的电场从接近栅极电介质的栅极区域清除载流子时，发生多晶硅耗尽效应，形成耗尽层。在n掺杂的多晶硅层中，耗尽层包括离子化的非移动供体位点，其中，在p掺杂的多晶硅层中，耗尽层包括离子化的非移动受体位点。耗尽效应导致有效栅极电介质厚度的增加，使得在半导体的表面处生成反型层更加困难。
可以通过形成金属栅电极来解决多晶硅耗尽问题，其中，用于NMOS器件和PMOS器件的金属栅极也可以具有带边功函数。因此，产生的金属栅极包括多个层以满足NMOS器件和PMOS器件的需求。
金属栅极的形成通常涉及沉积金属层并且之后实施化学机械抛光(CMP)以去除金属层的过量部分。金属层的剩余部分形成金属栅极。之后，使金属栅极凹进。金属栅极可以包括钨。然而，钨对下面的层不具有良好的粘合。因此，形成钨成核层，随后沉积额外的钨层。钨成核层对其下面的层具有改进的粘合。然而，钨成核层的电阻率远高于上面沉积的钨。因此，当MOS器件按比率缩小并且金属栅极的宽度非常小时，钨成核层的电阻率显着影响了产生的晶体管的性能。
发明内容
本发明的实施例提供了一种形成半导体器件的方法，包括：形成晶体管，包括：在半导体区域上形成栅极电介质；在所述栅极电介质上方形成栅电极；和形成延伸至所述半导体区域内的源极/漏极区域；在所述源极/漏极区域上方形成电连接至所述源极/漏极区域的源极/漏极接触插塞；以及在所述栅电极上方形成与所述栅电极接触的栅极接触插塞，其中，形成所述栅电极、形成所述源极/漏极接触插塞或形成所述栅极接触插塞的至少一个包括：形成金属氮化物阻挡层；和在所述金属氮化物阻挡层上方沉积与所述金属氮化物阻挡层接触的含金属层，其中，所述含金属层包括钴层或金属硅化物层的至少一个。
本发明的另一实施例提供了一种形成半导体器件的方法，包括：在半导体区域上方形成伪栅极堆叠件；形成层间电介质(ILD)，其中，所述伪栅极堆叠件位于所述层间电介质中；去除所述伪栅极堆叠件以在所述层间电介质中形成开口；形成延伸至所述开口内的置换栅极电介质；在所述置换栅极电介质上方形成功函金属层；在所述置换栅极电介质上方形成包括氮化钛层的阻挡层；沉积延伸至所述开口内的含钴层，其中，所述含钴层位于所述阻挡层上面并且与所述阻挡层接触；实施平坦化以去除所述置换栅极电介质、所述功函金属层、所述阻挡层和所述含钴层的过量部分以形成置换栅极堆叠件；以及形成源极区域和漏极区域，其中，所述源极区域和所述漏极区域位于所述置换栅极堆叠件的相对侧上。
本发明的又一实施例提供了一种半导体器件，包括：栅极间隔件；栅极电介质，延伸至所述栅极间隔件之间的间隔内；栅电极，包括：第一金属氮化物层，位于所述栅极电介质上方；以及功函金属层，位于所述第一金属氮化物层上方，其中，所述第一金属氮化物层和所述功函金属层在所述栅极间隔件之间延伸；栅极接触插塞，位于所述栅电极上方并且与所述栅电极接触；以及源极/漏极区域，邻近于所述栅电极；以及源极/漏极接触插塞，位于所述源极/漏极区域上方并且电连接至所述源极/漏极区域，其中，所述栅电极、所述源极/漏极接触插塞和所述栅极接触插塞的至少一个包括：第二金属氮化物层；和含金属层，位于所述第二金属氮化物层上方并且与所述第二金属氮化物层接触，其中，所述含金属层包括钴层和金属硅化物层的至少一个。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳理解本发明的各个方面。应该指出，根据工业中的标准实践，各个部件未按比率绘制。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1至图18示出了根据一些实施例的在鳍式场效应晶体管(FinFET)的形成中的中间阶段的截面图和立体图。
图19示出了根据一些实施例的具有示出的实际轮廓的FinFET的截面图。
图20示出了根据一些实施例的用于形成FinFET的工艺的流程图。
具体实施方式
以下公开内容提供了许多用于实现本发明的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。此外，本发明可在各个实施例中重复参考标号和/或字符。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且，为便于描述，在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等空间相对术语，以描述如图所示的一个元件或部件与另一个(或另一些)原件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上)，而本文使用的空间相对描述符可以同样地作出相应的解释。
根据各个示例性实施例提供了晶体管及其形成方法。根据一些实施例示出了形成晶体管的中间阶段。讨论了一些实施例的一些变化。贯穿各个视图和示例性实施例，相同的参考标号用于指定相同的元件。在示出的示例性实施例中，将鳍式场效应晶体管(FinFET)的形成用作实例来说明本发明的概念。平面晶体管也可以采用本发明的概念。
图1至图18示出了根据本发明的一些实施例的FinFET的形成中的中间阶段的截面图和立体图。图1至图18所示的步骤也示意性地反映在图20所示的工艺流程中。
图1示出了初始结构的立体图。初始结构包括晶圆10，该晶圆10进一步包括衬底20。衬底20可以是半导体衬底，该半导体衬底可以是硅衬底、硅锗衬底或由其它半导体材料形成的衬底。衬底20可以用p型或n型杂质掺杂。可以形成诸如浅沟槽隔离(STI)区域的隔离区域22以从衬底20的顶面延伸至衬底20，其中，衬底20的顶面是晶圆10的主表面10A。位于相邻的STI区域22之间的衬底20的部分称为半导体带24。根据一些示例性实施例，半导体带24的顶面和STI区域22的顶面基本可以彼此齐平。
STI区域22可以包括衬垫氧化物(未示出)。衬垫氧化物可以由通过衬底20的表面层的热氧化形成的热氧化物形成。衬垫氧化物也可以是使用例如原子层沉积(ALD)、高密度等离子体化学汽相沉积(HDPCVD)或化学汽相沉积(CVD)形成的沉积的氧化硅层。STI区域22也可以包括位于衬垫氧化物上方的介电材料，其中，介电材料可以由可流动化学汽相沉积(FCVD)、旋涂等形成。
参照图2，使STI区域22凹进，使得半导体带24的顶部突出高于STI区域22的顶面以形成突出鳍24’。可以使用干蚀刻工艺实施蚀刻，其中，HF3和NH3用作蚀刻气体。在蚀刻工艺期间，可以产生等离子体。也可以包括氩。根据本发明的可选实施例，使用湿蚀刻工艺实施STI区域22的凹进。例如，蚀刻化学物质可以包括稀释的HF。
参照图3，在突出鳍24’的顶面和侧壁上形成伪栅极堆叠件30。伪栅极堆叠件30可以包括伪栅极电介质32和位于伪栅极电介质32上方的伪栅电极34。例如，伪栅电极34可以使用多晶硅形成，也可以使用其它材料形成。伪栅极堆叠件30也可以包括位于伪栅电极34上方的一个(或多个)硬掩模层36。硬掩模层36可以由氮化硅、碳氮化硅等形成。伪栅极堆叠件30可以横跨在单个或多个突出鳍24’和/或STI区域22上方。伪栅极堆叠件30也可以具有垂直于突出鳍24’的纵向方向的纵向方向。
下一步，在伪栅极堆叠件30的侧壁上形成栅极间隔件38。根据本发明的一些实施例，栅极间隔件38由诸如碳氮化硅(SiCN)、氮化硅等的介电材料形成，并且可以具有单层结构或包括多个介电层的多层结构。
之后，实施蚀刻步骤(在下文中称为源极/漏极凹进)以蚀刻未由伪栅极堆叠件30和栅极间隔件38覆盖的突出鳍24’的部分，产生图4中所示的结构。该凹进可以是各向异性的，并且因此直接位于伪栅极堆叠件30和栅极间隔件38下面的鳍24’的部分受到保护并且不被蚀刻。根据一些实施例，凹进的半导体带24的顶面24A可以低于STI区域22的顶面22A。因此，在STI区域22之间形成凹槽40。凹槽40位于伪栅极堆叠件30的相对侧上。
下一步，通过在凹槽40中选择性生长半导体材料形成外延区域(源极/漏极区域)，产生图5中的结构。根据一些示例性实施例，外延区域42包括硅锗或硅。根据产生的FinFET是p型FinFET还是n型FinFET，随着外延的进行，可以原位掺杂p型或n型杂质。例如，当产生的FinFET是p型FinFET时，可以生长硅锗硼(SiGeB)。相反地，当产生的FinFET是n型FinFET时，可以生长硅磷(SiP)或硅碳磷(SiCP)。根据本发明的可选实施例，外延区域42由诸如GaAs、InP、GaN、InGaAs、InAlAs、GaSb、AlSb、AlAs、AlP、GaP、它们的组合或它们的多层的III-V族化合物半导体形成。在用外延区域42填充凹槽40之后，外延区域42的进一步外延生长引起外延区域42的水平扩展，并且可以形成小平面。
在外延步骤之后，外延区域42可以进一步注入p型或n型杂质以形成源极和漏极区域，也用参照标号42表示。根据本发明的可选实施例，当在外延期间用p型或n型杂质原位掺杂外延区域42时，跳过注入步骤。外延区域42包括在STI区域22中形成的下部42A和在STI区域22的顶面22A上方形成的上部42B。下部42A(其侧壁由凹槽40(图4)的形状成形)可以具有(基本)直的边缘，该直的边缘也可以是基本垂直于衬底20的主表面(诸如底面)的基本垂直的边缘。
图6A示出了形成有层间电介质(ILD)46的结构的立体图。根据本发明的一些实施例，在ILD 46的形成之前，在源极和漏极区域42上形成缓冲氧化物层(未示出)和接触蚀刻停止层(CESL)47。缓冲氧化物层可以由氧化硅形成，并且CESL 47可以由氮化硅、碳氮化硅等形成。例如，可以使用诸如ALD的共形沉积方法形成缓冲氧化物层和CESL 47。ILD 46可以包括使用例如FCVD、旋涂、CVD或其它沉积方法形成的介电材料。ILD 46也可以由磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BSG)、硼掺杂的磷硅酸盐玻璃(BPSG)、正硅酸乙酯(TEOS)氧化物等形成。可以实施诸如化学机械抛光(CMP)或机械研磨的平坦化以使ILD 46、伪栅极堆叠件30和栅极间隔件38的顶面彼此齐平。
图6B示出了图6A所示的结构的截面图，其中，该截面图从图6A中包含线A-A的垂直平面获得。下一步，用金属栅极和置换栅极电介质替换包括硬掩模层36、伪栅电极34和伪栅极电介质32的伪栅极堆叠件30。图7至图18中所示的截面图从图6A中包含线A-A的相同的垂直平面获得。在图7至图18中，示出了STI区域22的顶面的水平22A，并且半导体鳍24’位于水平22A上方。
去除如图6A和图6B所示的硬掩模层36、伪栅电极34和伪栅极电介质32，导致形成图7所示的开口48。相应的步骤示出为图20中所示的工艺流程中的步骤202。突出鳍24’的顶面和侧壁暴露于开口48。
图7还示出了根据一些实施例的栅极间隔件50的形成。根据可选实施例，没有形成栅极间隔件50。为了形成栅极间隔件50，例如，可以使用诸如ALD或CVD的沉积方法形成毯式栅极间隔件层。毯式栅极间隔件层是共形的。根据本发明的一些实施例，栅极间隔件层由氮化硅(SiN)、SiC、SiON或另一介电材料形成，其可以与栅极间隔件38的材料以及CESL 47和ILD 46的材料的任一种相同或不同。栅极间隔件50将随后形成的金属栅极与源极/漏极区域42分隔开并且远离，并且减少了它们之间的泄漏和电短路的可能性。
下一步，参照图8，形成延伸至开口48内的栅极电介质52。相应的步骤示出为图20中所示的工艺流程中的步骤204。根据本发明的一些实施例，栅极电介质52包括作为它的下部的界面层(IL)54。IL 54形成在突出鳍24’的暴露的表面上。IL 54可以包括诸如氧化硅层的氧化物层，该氧化物层通过突出鳍24’的热氧化、化学氧化工艺或沉积工艺形成。栅极电介质52也可以包括在IL 54上方形成的高k介电层56。高k介电层56包括诸如氧化铪、氧化镧、氧化铝、氧化锆等的高k介电材料。高k介电材料的介电常数(k值)高于3.9，并且可以高于约7.0。高k介电层56位于IL 54上面并且可以接触IL 54。高k介电层56形成为共形层，并且在突出鳍24’的侧壁以及栅极间隔件38/50的顶面和侧壁上延伸。根据本发明的一些实施例，使用ALD或CVD形成高k介电层56。
进一步参照图8，沉积堆叠层58。相应的步骤示出为图20中所示的工艺流程中的步骤206。未单独示出堆叠层58中的子层，而实际上，由于子层由不同的材料和/或具有不同百分比的元素形成，因此子层是可区分的。可以使用诸如ALD或CVD的共形沉积方法实施沉积，使得堆叠层58(以及每个子层)的垂直部分的厚度T1和水平部分的厚度T2彼此基本相等。堆叠层58延伸至开口48内，并且包括位于ILD 46上方的一些部分。
堆叠层58可以包括扩散阻挡层和位于扩散阻挡层上方的一个或多个功函层。扩散阻挡层可以由氮化钛(可以(或可以不)掺杂有硅)形成。当掺杂有硅时，氮化钛有时也称为氮化钛硅(Ti-Si-N或TSN)。氮化钛或氮化钛硅是导电材料。功函层决定了栅电极的功函数，并且包括至少一层或由不同材料形成的多个层。可以根据相应的FinFET是n型FinFET还是p型FinFET选择功函层的具体材料。例如，当FinFET是n型FinFET时，功函层可以包括TaN层和位于TaN层上方的钛铝(TiAl)层。当FinFET是p型FinFET时，功函层可以包括TaN层、位于TaN层上方的TiN层和位于TiN层上方的TiAl层。在堆叠层58的沉积之后，形成可以是另一TiN层的阻挡层60。TiN层60可以使用CVD形成，并且可以用作阻塞层。相应的步骤也示出为图20中所示的工艺流程中的步骤206。根据一些实施例，TiN层60可以不含硅。
下一步，沉积含金属材料62，该含金属材料62可以具有与TiN层60的顶面物理接触的底面。相应的步骤示出为图20中所示的工艺流程中的步骤208。含金属材料62的形成可以通过CVD、ALD或PVD来实现。根据本发明的一些实施例，使用物理汽相沉积(PVD)，该物理汽相沉积(PVD)使用设置在相应的晶圆10上方的钴靶实施。此外，也在PVD期间引入前体。因此，沉积包括PVD和CVD。根据一些实施例，用于沉积含金属材料62的前体包括含钴前体、含硅前体和可能的其它气体。例如，用于形成含金属材料62的前体可以包括正硅酸乙酯(TEOS)、SiHCl3和含钴前体(诸如八羰基二钴、钴亚硝酰基络合物或钴(II)和钴(III)的β-二酮酸酯等)。
根据一些实施例，含金属材料62包括层62A和位于层62A上方的层62B。根据一些实施例，层62A是硅化钴(CoxSiy，其中，x和y是原子百分比并且具有介于0和1.0之间的值)层。层62B是不含或基本不含(例如，原子百分比低于约1％)硅或其它元素的钴层。由于层62A和62B都是含钴层，因此可以减小制造成本。例如，相同的含硅前体和含钴前体(以及可能的额外的Co靶)可以用于沉积层62A和层62B。根据示例性沉积工艺，当沉积层62A(CoxSiy)时，晶圆10的温度可以在介于约85℃和约120℃之间的范围内。在层62A的沉积结束之后，例如，将晶圆10的温度降低至约25℃，并且使用相同的前体(使用或不使用额外的Co靶)，形成不含或基本不含硅的钴层62B。根据一些实施例，通过降低晶圆10的温度来实现从层62A的沉积至层62B的沉积的过渡，同时保持其它工艺条件(诸如前体的流率、分压、功率等)不变。含金属材料62的形成也可以通过逐渐降低晶圆10的温度来实现，从而使得层62A具有逐渐减小的硅含量，其中，层62A的上部具有比相应的下部更少的硅。温度的逐渐降低可以是连续的。温度的逐渐降低也可以是通过突然的步骤，这意味着该温度突然下降至较低的步骤，并且在下降至另一较低的阶段之前，保持不变一段时间。继续进行逐渐转变，直至相应形成的层不含或基本不含硅，此时开始形成层62。之后，当产生的层是钴层时，温度可以是稳定的。因此，整个层62B可以是不含或基本不含硅和其它元素的钴层，而层62A具有逐渐(突然或连续)减小的硅百分比。
根据可选实施例，下层62A是钴层，并且上层62B是硅化钴层。形成工艺可以与上述讨论相反以形成层62A和62B。
根据一些实施例，层62A由金属硅化物(使用除了钴之外的金属)形成，该金属硅化物可以是TixSiy、NixSiy、WxSiy、MoxSiy、TaxSiy，并且层62B是不含或基本不含硅和其它元素的钴层。
根据一些实施例，整个层62由均质材料形成，该均质材料可以是钴(不含或基本不含硅和其它元素)或诸如TixSiy、NixSiy、WxSiy、MoxSiy或TaxSiy的金属硅化物。整个层62具有均匀的电阻率。当由硅化物层形成时，整个层62可以具有恒定百分比x和y，并且具有均匀的电阻率或可以具有从下到上逐渐改变的(诸如逐渐减小的或逐渐增加的)百分比x和y。因此，该形成工艺可以在贯穿整个层62的形成中具有恒定的工艺条件(诸如温度、压力、流率等)。
下一步，实施诸如化学机械抛光(CMP)或机械研磨的平坦化，从而去除位于ILD 46上方的层56、58、60和62的部分。相应的步骤示出为图20中所示的工艺流程中的步骤210。下一步，如图9所示，回蚀刻层56、58、60和62，形成凹槽63。相应的步骤示出为图20中所示的工艺流程中的步骤212。在下文中，层54、56、58、60和62的剩余部分称为置换栅极堆叠件64。
如图10所示，在置换栅极堆叠件64上方形成硬掩模66。相应的步骤也示出为图20中所示的工艺流程中的步骤212。根据本发明的一些实施例，硬掩模66的形成包括形成毯式介电材料的沉积步骤，以及去除位于栅极间隔件38和ILD 46上方的过量介电材料的平坦化步骤。例如，硬掩模66可以由氮化硅形成。
图11至图14示出了下源极/漏极接触插塞的形成。参照图11，在图10中所示的结构上方形成介电层67，随后施加图案化的光刻胶(未示出)。下一步，蚀刻介电层67、ILD 46和CESL 47以形成接触开口68。相应的步骤示出为图20中所示的工艺流程中的步骤214。
进一步参照图11，例如，使用PVD沉积金属层72(诸如钛层或钽层)。之后，在金属层72上方形成阻挡层74，该阻挡层74可以是诸如氮化钛层或氮化钽层的金属氮化物层。相应的步骤示出为图20中所示的工艺流程中的步骤216。阻挡层74可以使用CVD形成。层72和74都是共形的，并且延伸至开口68内。
之后，如图12所示，实施退火以形成源极/漏极硅化物区域76。相应的步骤示出为图20中所示的工艺流程中的步骤218。可以通过快速热退火(RTA)、炉退火等实施退火。因此，金属层72的底部与源极/漏极区域42反应以形成硅化物区域76。在硅化工艺之后，金属层72的侧壁部分保留。根据本发明的一些实施例，硅化物区域76的顶面与阻挡层74的底面接触。
下一步，如图13所示，含金属层78沉积在阻挡层74上方并且与阻挡层74接触。相应的步骤示出为图20中所示的工艺流程中的步骤220。选自与含金属材料62的备选材料相同的组的材料可以形成含金属层78。此外，含金属层78的形成方法、材料和结构也可以选自含金属材料62的备选形成方法、备选材料和备选结构。例如，含金属层78可以是均质钴层或均质金属硅化物层，或可以包括下层78A和上层78B，其中，层78A和78B的形成方法、材料和结构可以分别参照以上讨论的层62A和62B的任何组合找到。
之后，实施诸如CMP的平坦化以去除位于层67上方的层72和74的部分。相应的步骤示出为图20中所示的工艺流程中的步骤222。产生图14中所示的结构，图14示出了源极/漏极接触插塞79。源极/漏极接触插塞79的每个均包括含金属层78、阻挡层74和金属层72。
图15至图17示出了栅极接触插塞的形成。相应的步骤示出为图20中所示的工艺流程中的步骤224。参照图15，使用光刻掩模(未示出)实施光刻工艺以蚀刻穿过介电层67。之后，去除硬掩模66(图14)，形成开口80。根据本发明的一些实施例，开口80的形成包括蚀刻穿过介电层67的各向异性蚀刻和去除硬掩模66的各向同性蚀刻(干或湿)或各向异性蚀刻。因此，暴露栅极间隔件50(如果存在的话)的侧壁。在没有形成栅极间隔件50的实施例中，栅极间隔件38的侧壁暴露于开口80。选择用于蚀刻介电层67和硬掩模66的蚀刻剂，使得栅极间隔件50和38基本未被蚀刻。根据本发明的可选实施例，开口80比硬掩模66窄，并且因此在蚀刻之后留下硬掩模66的一些边缘部分。
参照图16，沉积阻挡层82和含金属材料84。阻挡层82可以由氮化钛或氮化钽形成。含金属材料84的材料、结构和形成方法可以分别选自含金属材料62的备选材料、备选结构和备选形成方法，并且因此未在此处重复细节，并且可以参照含金属材料62的讨论找到。因此，与含金属材料62类似，含金属材料84也可以由钴、金属硅化物或它们的复合层形成。在随后的步骤中，实施诸如CMP的平坦化。可以实施平坦化直至去除全部的层67，并且暴露ILD46。因此，层67用作牺牲层。产生的结构如图17所示，图17示出了由层82和84的剩余部分形成的接触插塞86。因此，形成FinFET 300。
图18示出了蚀刻停止层88、ILD 90以及位于蚀刻停止层88和ILD 90中的源极/漏极接触插塞(通孔)92的形成。蚀刻停止层88可以由碳化硅、氮氧化硅、碳氮化硅等形成，并且可以使用诸如CVD的沉积方法形成。ILD 90可以包括选自PSG、BSG、BPSG、氟掺杂的硅玻璃(FSG)、TEOS氧化物或其它无孔低k介电材料的材料。ILD 90可以使用旋涂、可流动化学汽相沉积(FCVD)等形成，或使用诸如等离子体增强化学汽相沉积(PECVD)、低压化学汽相沉积(LPCVD)等的沉积方法形成。
蚀刻ILD 90和蚀刻停止层88以形成开口(由通孔92占据)。例如，可以使用反应离子蚀刻(RIE)实施蚀刻。在随后的步骤中，形成通孔92。根据一些实施例，通孔92包括阻挡层94和位于阻挡层94上方的含金属材料96。根据本发明的一些实施例，通孔92的形成包括蚀刻层88和90以形成接触开口，形成毯式阻挡层以及位于毯式阻挡层上方的含金属材料，并且实施平坦化以去除毯式阻挡层和含金属材料的过量部分。阻挡层94可以由诸如氮化钛或氮化钽的金属氮化物形成。含金属材料96的材料、结构和形成方法可以分别选自含金属材料62的备选材料、备选结构和备选形成方法，并且因此未在此处重复细节。
通孔92具有介于约80度和约90度之间的范围内的倾斜角度α的侧壁。通孔92也具有大于相应底部宽度W底部的顶部宽度W顶部。例如，比率W顶部/W底部可以在介于约1.2和约1.5之间的范围内。这种轮廓对间隙填充是有益的。
图19示出了根据一些实施例的FinFET的截面图。根据本发明的一些实施例，如图19所示，接触插塞92的侧壁具有基本直的和倾斜的下部，以及弯曲的上部，并且绘制线93以示出上部和下部之间的过渡水平。与相应的下部相比，侧壁的上部可以具有相当大的斜率的变化。接触插塞92的高度标记为H1。接触插塞92的顶部的高度标记为H2。顶部宽度和底部宽度分别标记为W顶部和W底部。宽度W底部在接触插塞92的深度H1的95％处测量。接触插塞92在过渡点处的宽度为W过渡。根据本发明的一些实施例，比率W过渡/W底部可以介于约1.2和约1.5之间。比率H2/H1可以介于约0.1和约0.2之间。倾斜角度α可以介于约80度和约90度之间，并且可以是约85度。虽然未详细地示出接触插塞79的尺寸和倾斜角度，但是接触插塞79可以具有类似的轮廓。
本发明的实施例具有一些有利特征。当蚀刻介电层时，可以产生聚合物。为了去除由于介电层的蚀刻形成的残留聚合物，可以使用酸性溶液(诸如H2O2)。钴具有良好的耐酸性。酸性溶液引起暴露的金属的腐蚀。如果使用钨，则它更有可能被腐蚀。另一方面，钴更具耐蚀性，并且可以减少金属的腐蚀(诸如金属栅极损耗)产生的问题。钴也具有比钨更小的粗糙度，使得它成为用于形成高质量膜的更好的材料。
此外，由于散射效应，钴和金属硅化物在非常小的尺寸处具有比钨低的电阻率值。同样，钨对诸如TiN的一些阻挡材料不具有良好的粘合。因此，通常形成钨成核层，随后使用CVD沉积钨。钨成核层具有介于约200μΩ·cm和约250μΩ·cm之间的范围内的电阻率，其远高于CVD钨的电阻率(约5.7μΩ·cm)。因此，钨成核层的电阻率显著降低了产生的晶体管的性能。另一方面，钴(或金属硅化物)具有非常低的电阻率(硅化钴为约5.8μΩ·cm)，并且对TiN具有良好的粘合。因此，通过采用钴和/或金属硅化物，对下面的阻挡层的粘合是良好的，并且金属栅极的电阻率低。
根据本发明的一些实施例，方法包括形成晶体管，形成晶体管包括在半导体区域上形成栅极电介质，在栅极电介质上方形成栅电极，并且形成延伸至半导体区域内的源极/漏极区域。该方法还包括在源极/漏极区域上方形成电连接至源极/漏极区域的源极/漏极接触插塞，并且在栅电极上方形成与栅电极接触的栅极接触插塞。形成栅电极、形成源极/漏极接触插塞和形成栅极接触插塞的至少一个包括形成金属氮化物阻挡层，并且在金属氮化物阻挡层上方沉积与金属氮化物阻挡层接触的含金属层。含金属层包括钴层和金属硅化物层的至少一个。
在上述方法中，其中，形成所述栅电极包括：沉积含氮化钛层；在所述含氮化钛层上方沉积功函层，其中，所述金属氮化物阻挡层位于所述功函层上方；以及实施平坦化以去除所述含氮化钛层和所述功函层的过量部分。
在上述方法中，其中，形成所述源极/漏极接触插塞包括：蚀刻层间电介质以形成源极/漏极接触开口，其中，所述源极/漏极区域暴露于所述源极/漏极接触开口；沉积金属层，所述金属层具有延伸至所述源极/漏极接触开口内的部分，其中，所述金属氮化物阻挡层沉积在所述金属层上方；实施退火以形成源极/漏极硅化物；以及实施平坦化以去除所述金属层和所述金属氮化物阻挡层的过量部分。
在上述方法中，其中，形成所述栅极接触插塞包括：去除栅极间隔件的相对部分之间的硬掩模，其中，所述金属氮化物阻挡层和所述含金属层延伸至由去除的硬掩模留下的开口内；以及实施平坦化以去除所述金属氮化物阻挡层和所述含金属层的过量部分。
在上述方法中，其中，沉积所述含金属层包括：沉积金属硅化物层；以及在所述金属硅化物层上方沉积不含硅的钴层。
在上述方法中，其中，沉积所述含金属层包括：沉积金属硅化物层；以及在所述金属硅化物层上方沉积不含硅的钴层，其中，所述金属硅化物层的上部比所述金属硅化物层的相应的下部具有越来越低的硅百分比。
在上述方法中，所述含金属层的整个均由具有均匀电阻率的钴形成，并且所述含金属层不含除了钴之外的元素。
在上述方法中，其中，所述含金属层的整个均由具有均匀电阻率的所述金属硅化物层形成。
在上述方法中，其中，沉积所述含金属层包括沉积所述金属硅化物层，并且当沉积所述金属硅化物层时，改变相应的晶圆的温度。
根据本发明的一些实施例，方法包括形成晶体管，形成晶体管包括在半导体区域上方形成伪栅极堆叠件，形成ILD，其中，伪栅极堆叠件位于ILD中，去除伪栅极堆叠件以在ILD中形成开口，形成延伸至开口内的置换栅极电介质，在置换栅极电介质上方形成功函金属层，在置换栅极电介质上方形成包括氮化钛的阻挡层，并且沉积延伸至开口内的含钴层。含钴层位于阻挡层上面并且与阻挡层接触。实施平坦化以去除置换栅极电介质、功函金属层、阻挡层和含钴层的过量部分以形成置换栅极堆叠件。在置换栅极堆叠件的相对侧上形成源极区域和漏极区域。
在上述方法中，其中，所述含钴层包括钴，所述钴不含除了钴之外的元素。
在上述方法中，其中，所述含钴层包括硅化钴层。
在上述方法中，其中，所述含钴层包括硅化钴层，其中，所述含钴层还包括位于所述硅化钴层上方的不含硅的钴层。
在上述方法中，其中，所述含钴层包括硅化钴层，其中，所述含钴层还包括位于所述硅化钴层上方的不含硅的钴层，所述硅化钴层和所述钴层使用相同的前体形成，其中，在比用于沉积所述硅化钴层的温度低的温度下沉积所述钴层。
在上述方法中，其中，所述含钴层包括硅化钴层，其中，用连续改变的温度实施所述含钴层的沉积，并且所述硅化钴层具有连续改变的硅百分比。
根据本发明的一些实施例，器件包括栅极间隔件、栅极电介质和栅电极。栅电极包括位于栅极电介质上方的第一金属氮化物层和位于第一金属氮化物层上方的功函金属层。栅极电介质和栅电极在栅极间隔件之间延伸。栅极接触插塞位于栅电极上方并且与栅电极接触。源极/漏极区域邻近于栅电极。源极/漏极接触插塞位于源极/漏极区域上方并且电连接至源极/漏极区域。栅电极、源极/漏极接触插塞和栅极接触插塞的至少一个包括第二金属氮化物层和位于第二金属氮化物上方并且与第二金属氮化物层接触的含金属层。含金属层包括钴层和金属硅化物层的至少一个。
在上述器件中，其中，所述含金属层的整个均由钴形成并且具有均匀的电阻率，并且所述含金属层不含除了钴之外的元素。
在上述器件中，其中，所述含金属层的整个均由硅化钴形成。
在上述器件中，其中，所述含金属层包括：金属硅化物层；以及钴层，不含硅并且位于所述金属硅化物层上方。
在上述器件中，其中，所述含金属层包括：金属硅化物层；以及钴层，不含硅并且位于所述金属硅化物层上方，其中，所述金属硅化物层包括硅化钴，并且所述硅化钴的上部比所述硅化钴的相应的下部具有越来越低的硅百分比。
上面概述了若干实施例的特征，使得本领域人员可以更好地理解本发明的方面。本领域人员应该理解，他们可以容易地使用本发明作为基础来设计或修改用于实施与本人所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，本文中他们可以做出多种变化、替换以及改变。

Claims (20)

1.一种形成半导体器件的方法，包括：
形成晶体管，包括：
在半导体区域上形成栅极电介质；
在所述栅极电介质上方形成栅电极；和
形成延伸至所述半导体区域内的源极/漏极区域；
在所述源极/漏极区域上方形成电连接至所述源极/漏极区域的源极/漏极接触插塞；以及
在所述栅电极上方形成与所述栅电极接触的栅极接触插塞，其中，形成所述栅极接触插塞包括：
去除栅极间隔件的相对部分之间的硬掩模；
形成金属氮化物阻挡层；
在所述金属氮化物阻挡层上方沉积与所述金属氮化物阻挡层接触的含金属层，其中，所述含金属层包括钴层或金属硅化物层的至少一个，所述金属氮化物阻挡层和所述含金属层延伸至由去除的硬掩模留下的开口内；和
实施平坦化以去除所述金属氮化物阻挡层和所述含金属层的过量部分。
2.根据权利要求1所述的方法，其中，形成所述栅电极包括：
沉积含氮化钛层；
在所述含氮化钛层上方沉积功函层，其中，所述金属氮化物阻挡层位于所述功函层上方；以及
实施平坦化以去除所述含氮化钛层和所述功函层的过量部分。
3.根据权利要求1所述的方法，其中，形成所述源极/漏极接触插塞包括：
蚀刻层间电介质以形成源极/漏极接触开口，其中，所述源极/漏极区域暴露于所述源极/漏极接触开口；
沉积金属层，所述金属层具有延伸至所述源极/漏极接触开口内的部分，其中，所述金属氮化物阻挡层沉积在所述金属层上方；
实施退火以形成源极/漏极硅化物；以及
实施平坦化以去除所述金属层和所述金属氮化物阻挡层的过量部分。
4.根据权利要求1所述的方法，其中，所述含金属层包括金属硅化物层和不含硅的钴层，所述金属硅化物层和所述钴层使用相同的前体形成。
5.根据权利要求1所述的方法，其中，沉积所述含金属层包括：
沉积金属硅化物层；以及
在所述金属硅化物层上方沉积不含硅的钴层。
6.根据权利要求5所述的方法，其中，所述金属硅化物层的上部比所述金属硅化物层的相应的下部具有越来越低的硅百分比。
7.根据权利要求1所述的方法，所述含金属层的整个均由具有均匀电阻率的钴形成，并且所述含金属层不含除了钴之外的元素。
8.根据权利要求1所述的方法，其中，所述含金属层的整个均由具有均匀电阻率的所述金属硅化物层形成。
9.根据权利要求1所述的方法，其中，沉积所述含金属层包括沉积所述金属硅化物层，并且当沉积所述金属硅化物层时，改变相应的晶圆的温度。
10.一种形成半导体器件的方法，包括：
在半导体区域上方形成伪栅极堆叠件；
形成层间电介质，其中，所述伪栅极堆叠件位于所述层间电介质中；
去除所述伪栅极堆叠件以在所述层间电介质中形成开口；
形成延伸至所述开口内的置换栅极电介质；
在所述置换栅极电介质上方形成功函金属层；
在所述置换栅极电介质上方形成包括氮化钛层的阻挡层；
沉积延伸至所述开口内的含钴层，其中，所述含钴层位于所述阻挡层上面并且与所述阻挡层接触，沉积所述含钴层包括沉积硅化钴层；
实施平坦化以去除所述置换栅极电介质、所述功函金属层、所述阻挡层和所述含钴层的过量部分以形成置换栅极堆叠件；以及
形成源极区域和漏极区域，其中，所述源极区域和所述漏极区域位于所述置换栅极堆叠件的相对侧上。
11.根据权利要求10所述的方法，其中，所述含钴层不含除了钴之外的元素。
12.根据权利要求10所述的方法，还包括：在所述源极区域和所述漏极区域上方形成电连接至所述源极区域和所述漏极区域的源极接触插塞和漏极接触插塞。
13.根据权利要求12所述的方法，其中，所述含钴层还包括位于所述硅化钴层上方的不含硅的钴层。
14.根据权利要求13所述的方法，其中，所述硅化钴层和所述钴层使用相同的前体形成，其中，在比用于沉积所述硅化钴层的温度低的温度下沉积所述钴层。
15.根据权利要求12所述的方法，其中，用连续改变的温度实施所述含钴层的沉积，并且所述硅化钴层具有连续改变的硅百分比。
16.一种半导体器件，包括：
栅极间隔件；
栅极电介质，延伸至所述栅极间隔件之间的间隔内；
栅电极，包括：
第一金属氮化物层，位于所述栅极电介质上方；和
功函金属层，位于所述第一金属氮化物层上方，其中，所述第一金属氮化物层和所述功函金属层在所述栅极间隔件之间延伸；
栅极接触插塞，位于所述栅电极上方并且与所述栅电极接触；
源极/漏极区域，邻近于所述栅电极；以及
源极/漏极接触插塞，位于所述源极/漏极区域上方并且电连接至所述源极/漏极区域，其中，所述栅电极、所述源极/漏极接触插塞和所述栅极接触插塞的至少一个包括：
第二金属氮化物层；和
含金属层，位于所述第二金属氮化物层上方并且与所述第二金属氮化物层接触，其中，所述含金属层包括钴层和金属硅化物层的至少一个。
17.根据权利要求16所述的半导体器件，其中，所述含金属层的整个均由钴形成并且具有均匀的电阻率，并且所述含金属层不含除了钴之外的元素。
18.根据权利要求16所述的半导体器件，其中，所述含金属层的整个均由硅化钴形成。
19.根据权利要求16所述的半导体器件，其中，所述含金属层包括：
金属硅化物层；以及
钴层，不含硅并且位于所述金属硅化物层上方。
20.根据权利要求19所述的半导体器件，其中，所述金属硅化物层包括硅化钴，并且所述硅化钴的上部比所述硅化钴的相应的下部具有越来越低的硅百分比。
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Families Citing this family (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10121873B2 (en) * 2016-07-29 2018-11-06 Taiwan Semiconductor Manufacturing Company, Ltd. Metal gate and contact plug design and method forming same
US10186456B2 (en) 2017-04-20 2019-01-22 Taiwan Semiconductor Manufacturing Company, Ltd. Methods for forming contact plugs with reduced corrosion
US10141225B2 (en) 2017-04-28 2018-11-27 Taiwan Semiconductor Manufacturing Company, Ltd. Metal gates of transistors having reduced resistivity
US10522392B2 (en) * 2017-05-31 2019-12-31 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and method of fabricating the same
US10490458B2 (en) 2017-09-29 2019-11-26 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of cutting metal gates and structures formed thereof
US10727065B2 (en) * 2017-11-28 2020-07-28 Taiwan Semiconductor Manufactruing Co., Ltd. Semiconductor structure and manufacturing method thereof
KR20190110845A (ko) * 2018-03-21 2019-10-01 삼성전자주식회사 반도체 소자
US10755917B2 (en) * 2018-06-29 2020-08-25 Taiwan Semiconductor Manufacturing Company, Ltd. Treatment for adhesion improvement
KR102612592B1 (ko) * 2018-10-15 2023-12-12 삼성전자주식회사 반도체 소자
CN109461651A (zh) * 2018-11-05 2019-03-12 武汉新芯集成电路制造有限公司 改善硅化物阻挡层刻蚀缺陷的方法
US11094795B2 (en) 2018-11-20 2021-08-17 Nanya Technology Corporation Semiconductor device and method for manufacturing the same
KR102491555B1 (ko) 2018-11-30 2023-01-20 삼성전자주식회사 반도체 장치 및 그 제조 방법
US11069784B2 (en) * 2019-05-17 2021-07-20 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufacture
US11342225B2 (en) 2019-07-31 2022-05-24 Taiwan Semiconductor Manufacturing Company, Ltd. Barrier-free approach for forming contact plugs
US11183431B2 (en) * 2019-09-05 2021-11-23 Taiwan Semiconductor Manufacturing Co., Ltd. Method of manufacturing semiconductor devices and semiconductor devices
US11302818B2 (en) * 2019-09-16 2022-04-12 Taiwan Semiconductor Manufacturing Company, Ltd. Gate resistance reduction through low-resistivity conductive layer
US11316045B2 (en) * 2019-11-22 2022-04-26 Globalfoundries U.S. Inc. Vertical field effect transistor (FET) with source and drain structures
US10964792B1 (en) 2019-11-22 2021-03-30 Taiwan Semiconductor Manufacturing Co., Ltd. Dual metal capped via contact structures for semiconductor devices
US11502185B2 (en) * 2019-11-26 2022-11-15 Taiwan Semiconductor Manufacturing Co., Ltd. Methods of manufacturing a gate electrode having metal layers with different average grain sizes
KR20210088827A (ko) 2020-01-07 2021-07-15 삼성전자주식회사 반도체 장치
KR20210090768A (ko) * 2020-01-10 2021-07-21 삼성전자주식회사 반도체 소자 및 이의 제조 방법
US11532509B2 (en) * 2020-01-30 2022-12-20 Taiwan Semiconductor Manufacturing Co., Ltd. Selective hybrid capping layer for metal gates of transistors
US11361986B2 (en) * 2020-03-04 2022-06-14 Taiwan Semiconductor Manufacturing Company, Ltd. Using a liner layer to enlarge process window for a contact via
US11295989B2 (en) * 2020-05-26 2022-04-05 Taiwan Semiconductor Manufacturing Co., Ltd. Gate structures for semiconductor devices
CN113809083A (zh) * 2020-06-11 2021-12-17 联华电子股份有限公司 静态随机存取存储器及其制作方法
CN113937162A (zh) * 2020-06-29 2022-01-14 中芯国际集成电路制造(上海)有限公司 半导体器件及其形成方法
CN114068395B (zh) * 2020-07-31 2024-03-19 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
US11594610B2 (en) * 2020-10-15 2023-02-28 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and method
US11908944B2 (en) 2021-09-16 2024-02-20 International Business Machines Corporation Contact formation for vertical field effect transistors

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103579175A (zh) * 2012-07-25 2014-02-12 台湾积体电路制造股份有限公司 具有阻挡层的铜接触插塞
CN105280591A (zh) * 2014-06-12 2016-01-27 台湾积体电路制造股份有限公司 具有保护层的自对准互连件

Family Cites Families (49)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1098366A1 (en) 1994-12-29 2001-05-09 STMicroelectronics, Inc. Semiconductor connection structure and method
KR0172524B1 (ko) 1995-12-29 1999-03-30 김주용 반도체 소자의 게이트 전극 형성방법
US5998873A (en) * 1998-12-16 1999-12-07 National Semiconductor Corporation Low contact resistance and low junction leakage metal interconnect contact structure
KR100727449B1 (ko) 2000-09-25 2007-06-13 하이닉스 세미컨덕터 매뉴팩쳐링 아메리카 인코포레이티드 고도전성 게이트, 로컬 인터커넥트 또는 커패시터 노드를 갖는 집적 장치
JP4441726B2 (ja) 2003-01-24 2010-03-31 石原薬品株式会社 スズ又はスズ合金の脂肪族スルホン酸メッキ浴の製造方法
JP2006066514A (ja) 2004-08-25 2006-03-09 Seiko Epson Corp 強誘電体メモリ及びその製造方法
US7189650B2 (en) 2004-11-12 2007-03-13 Taiwan Semiconductor Manufacturing Co., Ltd. Method and apparatus for copper film quality enhancement with two-step deposition
JP5211503B2 (ja) 2007-02-16 2013-06-12 富士通セミコンダクター株式会社 半導体装置の製造方法
US8110877B2 (en) 2008-12-19 2012-02-07 Intel Corporation Metal-insulator-semiconductor tunneling contacts having an insulative layer disposed between source/drain contacts and source/drain regions
CN102024744B (zh) 2009-09-16 2013-02-06 中国科学院微电子研究所 半导体器件及其制造方法
US8436404B2 (en) 2009-12-30 2013-05-07 Intel Corporation Self-aligned contacts
CN102939408B (zh) 2010-06-11 2015-12-02 埃其玛公司 铜电镀组合物和使用该组合物填充半导体衬底中的空腔的方法
US8749067B2 (en) * 2010-08-18 2014-06-10 Institute of Microelectronics, Chinese Academy of Sciences Semiconductor device and method for forming the same
US20120061698A1 (en) 2010-09-10 2012-03-15 Toscano Lenora M Method for Treating Metal Surfaces
US8816444B2 (en) 2011-04-29 2014-08-26 Taiwan Semiconductor Manufacturing Company, Ltd. System and methods for converting planar design to FinFET design
US9236267B2 (en) 2012-02-09 2016-01-12 Taiwan Semiconductor Manufacturing Company, Ltd. Cut-mask patterning process for fin-like field effect transistor (FinFET) device
US8785285B2 (en) 2012-03-08 2014-07-22 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor devices and methods of manufacture thereof
US8860148B2 (en) 2012-04-11 2014-10-14 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for FinFET integrated with capacitor
US8741717B2 (en) * 2012-07-02 2014-06-03 GlobalFoundries, Inc. Methods for fabricating integrated circuits having improved metal gate structures
US8492228B1 (en) 2012-07-12 2013-07-23 International Business Machines Corporation Field effect transistor devices having thick gate dielectric layers and thin gate dielectric layers
US8823065B2 (en) 2012-11-08 2014-09-02 Taiwan Semiconductor Manufacturing Company, Ltd. Contact structure of semiconductor device
US9105490B2 (en) 2012-09-27 2015-08-11 Taiwan Semiconductor Manufacturing Company, Ltd. Contact structure of semiconductor device
US8772109B2 (en) 2012-10-24 2014-07-08 Taiwan Semiconductor Manufacturing Company, Ltd. Apparatus and method for forming semiconductor contacts
US20140120711A1 (en) 2012-10-26 2014-05-01 United Microelectronics Corp. Method of forming metal gate
US20140117550A1 (en) 2012-10-29 2014-05-01 International Business Machines Corporation Semiconductor device including an insulating layer, and method of forming the semiconductor device
US9236300B2 (en) 2012-11-30 2016-01-12 Taiwan Semiconductor Manufacturing Company, Ltd. Contact plugs in SRAM cells and the method of forming the same
US9514983B2 (en) 2012-12-28 2016-12-06 Intel Corporation Cobalt based interconnects and methods of fabrication thereof
US8921226B2 (en) 2013-01-14 2014-12-30 United Microelectronics Corp. Method of forming semiconductor structure having contact plug
US20140220777A1 (en) 2013-02-05 2014-08-07 International Business Machines Corporation Processing system for combined metal deposition and reflow anneal for forming interconnect structures
US8836129B1 (en) 2013-03-14 2014-09-16 United Microelectronics Corp. Plug structure
US9209272B2 (en) * 2013-09-11 2015-12-08 Taiwan Semiconductor Manufacturing Company, Ltd. Oxidation and etching post metal gate CMP
US9153483B2 (en) 2013-10-30 2015-10-06 Taiwan Semiconductor Manufacturing Company, Ltd. Method of semiconductor integrated circuit fabrication
US9136106B2 (en) 2013-12-19 2015-09-15 Taiwan Semiconductor Manufacturing Company, Ltd. Method for integrated circuit patterning
US9147767B2 (en) 2014-02-07 2015-09-29 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and manufacturing method thereof
US9171758B2 (en) 2014-03-31 2015-10-27 International Business Machines Corporation Method of forming transistor contacts
KR102171023B1 (ko) 2014-07-21 2020-10-29 삼성전자주식회사 반도체 소자 제조방법
CN105280486B (zh) 2014-07-23 2020-09-22 联华电子股份有限公司 金属栅极结构的制作方法
US9601430B2 (en) 2014-10-02 2017-03-21 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device structure and method for forming the same
US9685340B2 (en) 2015-06-29 2017-06-20 International Business Machines Corporation Stable contact on one-sided gate tie-down structure
US10269651B2 (en) 2015-07-02 2019-04-23 Taiwan Semiconductor Manufacturing Co., Ltd. Fin field effect transistor (FinFET) device structure and method for forming the same
US9780199B2 (en) 2015-09-23 2017-10-03 United Microelectronics Corp. Method for forming semiconductor device
KR102467848B1 (ko) 2015-10-12 2022-11-16 삼성전자주식회사 집적회로 소자 및 그 제조 방법
US9502265B1 (en) 2015-11-04 2016-11-22 Taiwan Semiconductor Manufacturing Company, Ltd. Vertical gate all around (VGAA) transistors and methods of forming the same
US9520482B1 (en) 2015-11-13 2016-12-13 Taiwan Semiconductor Manufacturing Company, Ltd. Method of cutting metal gate
US9496362B1 (en) 2016-01-04 2016-11-15 International Business Machines Corporation Contact first replacement metal gate
US9741812B1 (en) 2016-02-24 2017-08-22 International Business Machines Corporation Dual metal interconnect structure
US10079290B2 (en) 2016-12-30 2018-09-18 United Microelectronics Corp. Semiconductor device having asymmetric spacer structures
US10186456B2 (en) 2017-04-20 2019-01-22 Taiwan Semiconductor Manufacturing Company, Ltd. Methods for forming contact plugs with reduced corrosion
US10141225B2 (en) * 2017-04-28 2018-11-27 Taiwan Semiconductor Manufacturing Company, Ltd. Metal gates of transistors having reduced resistivity

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103579175A (zh) * 2012-07-25 2014-02-12 台湾积体电路制造股份有限公司 具有阻挡层的铜接触插塞
CN105280591A (zh) * 2014-06-12 2016-01-27 台湾积体电路制造股份有限公司 具有保护层的自对准互连件

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US11430694B2 (en) 2022-08-30
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US20190103311A1 (en) 2019-04-04
US20200118873A1 (en) 2020-04-16
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US10510596B2 (en) 2019-12-17
US10825727B2 (en) 2020-11-03
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