TWI677924B - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

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TWI677924B
TWI677924B TW106135468A TW106135468A TWI677924B TW I677924 B TWI677924 B TW I677924B TW 106135468 A TW106135468 A TW 106135468A TW 106135468 A TW106135468 A TW 106135468A TW I677924 B TWI677924 B TW I677924B
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Taiwan
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layer
metal
gate
cobalt
source
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TW106135468A
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TW201839858A (zh
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蔡嘉慶
Chia Ching Tsai
邱意為
Yi Wei Chiu
許立德
Li Te Hsu
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台灣積體電路製造股份有限公司
Taiwan Semiconductor Manufacturing Co., Ltd.
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Abstract

半導體裝置的製造方法，包含形成電晶體，包括：在半導體區上形成閘介電質；在閘介電質的上方形成閘極；形成源/汲極區，源/汲極區延伸而進入半導體區。上述方法更包含：形成源/汲極接觸插塞，源/汲極接觸插塞在源/汲極區的上方並電性耦合於源/汲極區；形成閘極接觸插塞，閘極接觸插塞在閘極的上方並與閘極接觸。閘極的形成、源/汲極接觸插塞的形成及閘極接觸插塞的形成的至少一個包括：形成金屬氮化物阻障層；在金屬氮化物阻障層的上方形成含金屬層且含金屬層接觸金屬氮化物阻障層。含金屬層包括鈷層與金屬矽化物層的至少一個。

Description

半導體裝置及其製造方法
本揭露是關於半導體裝置及其製造方法，特別是關於電晶體的金屬閘極具有低電阻的半導體裝置及其製造方法。
金屬-氧化物-半導體(Metal-Oxide-Semiconductor；MOS)裝置是積體電路中的基本構成元件。一現有的金屬-氧化物-半導體裝置通常具有以摻雜有p型或n型不純物的多晶矽形成的一閘極，其使用的摻雜方法有例如離子摻雜或熱擴散。可將上述閘極的功函數調整至矽的能帶邊緣(band-edge)。對於一n型金屬-氧化物-半導體(n-type Metal-Oxide-Semiconductor；NMOS)裝置，可將功函數調整至接近矽的導帶(conduction band)。對於一p型金屬-氧化物-半導體(p-type Metal-Oxide-Semiconductor；PMOS)裝置，可將功函數調整至接近矽的價帶(valence band)。多晶矽閘極的功函數的調整，可藉由選擇適當的不純物來達成。
具有多晶矽閘極的金屬-氧化物-半導體裝置展現載子空乏效應(carrier depletion effect)，其亦被稱為多晶空乏效應(poly depletion effect)。當施加的電場從接近閘介電質的閘極區掃去載子而形成空乏層時，則發生多晶空乏效應。在一 n摻雜的多晶矽層，其空乏層包括離子化的不移動的施體部位；而在一p摻雜的多晶矽層，其空乏層包括離子化的不移動的受體部位。上述空乏效應會導致有效閘介電質厚度的增加，而變得更難以在半導體的表面產生一反轉層。
多晶空乏效應的問題可藉由形成金屬閘極來解決，其中用於n型金屬-氧化物-半導體裝置與p型金屬-氧化物-半導體裝置的金屬閘極亦可具有能帶邊緣的功函數。因此，產生的金屬閘極包括複數個層以滿足n型金屬-氧化物-半導體裝置與p型金屬-氧化物-半導體裝置的需求。
金屬閘極的形成通常包括沉積金屬層，然後施行化學機械研磨(Chemical Mechanical Polish；CMP)，以移除上述金屬層的多餘部分。上述金屬層留下來的部分則形成金屬閘極。然後，在上述金屬閘極形成凹部。上述金屬閘極可包含鎢。然而，鎢對於下方層不具有良好的黏著力。因此，先形成一鎢孕核層，隨後沉積一附加的鎢層。上述鎢孕核層對於其下方層具有較佳的黏著力。然而，上述鎢孕核層的電阻遠高於在其上方沉積的鎢層。因此，當縮減金屬-氧化物-半導體裝置的尺寸時，金屬閘極的寬度非常小，上述鎢孕核層的電阻則成為影響所形成的電晶體的效能的重要因子。
本揭露的某些實施例是關於一種半導體裝置的製造方法，包含形成一電晶體，其包括：在一半導體區上形成一閘介電質；在上述閘介電質的上方形成一閘極；及形成一源/汲極區，上述源/汲極區延伸而進入上述半導體區。上述方法 更包含：形成一源/汲極接觸插塞，上述源/汲極接觸插塞在上述源/汲極區的上方並電性耦合於上述源/汲極區；以及形成一閘極接觸插塞，上述閘極接觸插塞在上述閘極的上方並與上述閘極接觸。上述閘極的形成、上述源/汲極接觸插塞的形成及上述閘極接觸插塞的形成的至少一個包括：形成一金屬氮化物阻障層；及在上述金屬氮化物阻障層的上方形成一含金屬層且上述含金屬層接觸上述金屬氮化物阻障層。上述含金屬層包括一鈷層與一金屬矽化物層的至少一個。
本揭露的某些實施例是關於一種半導體裝置的製造方法，包含：形成一電晶體，其包括：在一半導體區的上方形成一虛置(dummy)閘極堆疊結構；形成一層間介電質，其中上述虛置閘極堆疊結構是在上述層間介電質中；移除上述虛置閘極堆疊結構，以在上述層間介電質形成一開口；形成一取代閘極介電質，上述取代閘極介電質延伸而進入上述開口；在上述取代閘極介電質的上方形成一功函數金屬層；在上述取代閘極介電質的上方形成一阻障層，上述阻障層包括氮化鈦；以及沉積一含鈷層，上述含鈷層延伸而進入上述開口。上述含鈷層在上述阻障層上並與上述阻障層接觸。施行一平坦化步驟以移除上述取代閘極介電質、上述功函數金屬層、上述阻障層與上述含鈷層的多餘部分，以形成一取代閘極堆疊結構。形成一源極區與一汲極區，其中上述源極區與上述汲極區是在上述取代閘極堆疊結構的相反側。
本揭露的某些實施例是關於一種半導體裝置包含：複數個閘極間隔物、一閘介電質與一閘極。上述閘極包括： 一第一金屬氮化物層，在上述閘介電質的上方；及一功函數金屬層，在上述第一金屬氮化物層的上方。上述閘介電質與上述閘極在上述些閘極間隔物之間延伸。一閘極接觸插塞是在上述閘極的上方並接觸上述閘極。一源/汲極區是鄰接上述閘極。一源/汲極接觸插塞是在上述源/汲極區的上方並電性耦合於上述源/汲極區。上述閘極、上述源/汲極接觸插塞與上述閘極接觸插塞的至少一個包含：一第二金屬氮化物層；及一含金屬層，在上述第二金屬氮化物層的上方並接觸上述第二金屬氮化物層。上述含金屬層包括一鈷層與一金屬矽化物層的至少一個。
10‧‧‧晶圓
10A‧‧‧主表面
20‧‧‧基底
22‧‧‧淺溝槽隔離區
22A、24A‧‧‧上表面
24‧‧‧半導體條
24’‧‧‧突出的鰭狀物
30‧‧‧虛置閘極堆疊結構
32‧‧‧虛置閘介電質
34‧‧‧虛置閘極
36‧‧‧硬罩幕層
38‧‧‧閘極間隔物
40‧‧‧凹部
42A‧‧‧下部
42B‧‧‧上部
42‧‧‧磊晶區(源極與汲極)
46、90‧‧‧層間介電質
47‧‧‧接觸蝕刻停止層
48、80‧‧‧開口
50‧‧‧閘極間隔物
52‧‧‧閘介電質
54‧‧‧介面層
56‧‧‧高介電常數介電層
58‧‧‧疊層結構
60‧‧‧阻障層(TiN層)
62、78、84‧‧‧含金屬材料層
62A、62B‧‧‧層
63‧‧‧凹部
64‧‧‧取代閘極堆疊結構
66‧‧‧硬罩幕
67‧‧‧介電層
68‧‧‧接觸開口
72‧‧‧金屬層
74、82、94‧‧‧阻障層
76‧‧‧源極/閘極矽化物區
78A‧‧‧下層
78B‧‧‧下層
79‧‧‧源極/汲極接觸插塞
86‧‧‧接觸插塞
88‧‧‧蝕刻停止層
92‧‧‧介層窗(源極/汲極接觸插塞)
93‧‧‧虛線
202、204、206、208、210、212、214、216、218、220、222、224‧‧‧步驟
300‧‧‧鰭式場效電晶體
H1、H2‧‧‧高度
T1‧‧‧垂直部分的厚度
T2‧‧‧水平部分的厚度
Wbottom‧‧‧底部寬度
Wtop‧‧‧頂部寬度
Wtran‧‧‧接觸插塞在轉換的水平線的寬度
α‧‧‧傾角
根據以下的詳細說明並配合所附圖式做完整揭露。應注意的是，根據本產業的一般作業，圖示並未必按照比例繪製。事實上，可能任意的放大或縮小元件的尺寸，以做清楚的說明。
第1圖是一透視圖，顯示關於某些實施例的鰭式場效電晶體(Fin Field-Effect Transistors；FinFETs)的形成當中的中間階段。
第2圖是一透視圖，顯示關於某些實施例的鰭式場效電晶體的形成當中的中間階段。
第3圖是一透視圖，顯示關於某些實施例的鰭式場效電晶體的形成當中的中間階段。
第4圖是一透視圖，顯示關於某些實施例的鰭式場效電晶體的形成當中的中間階段。
第5圖是一透視圖，顯示關於某些實施例的鰭式場效電晶體的形成當中的中間階段。
第6A圖是一透視圖，顯示關於某些實施例的鰭式場效電晶體的形成當中的中間階段。
第6B圖是一剖面圖，顯示關於某些實施例的鰭式場效電晶體的形成當中的中間階段。
第7圖是一剖面圖，顯示關於某些實施例的鰭式場效電晶體的形成當中的中間階段。
第8圖是一剖面圖，顯示關於某些實施例的鰭式場效電晶體的形成當中的中間階段。
第9圖是一剖面圖，顯示關於某些實施例的鰭式場效電晶體的形成當中的中間階段。
第10圖是一剖面圖，顯示關於某些實施例的鰭式場效電晶體的形成當中的中間階段。
第11圖是一剖面圖，顯示關於某些實施例的鰭式場效電晶體的形成當中的中間階段。
第12圖是一剖面圖，顯示關於某些實施例的鰭式場效電晶體的形成當中的中間階段。
第13圖是一剖面圖，顯示關於某些實施例的鰭式場效電晶體的形成當中的中間階段。
第14圖是一剖面圖，顯示關於某些實施例的鰭式場效電晶體的形成當中的中間階段。
第15圖是一剖面圖，顯示關於某些實施例的鰭式場效電晶體的形成當中的中間階段。
第16圖是一剖面圖，顯示關於某些實施例的鰭式場效電晶體的形成當中的中間階段。
第17圖是一剖面圖，顯示關於某些實施例的鰭式場效電晶體的形成當中的中間階段。
第18圖是一剖面圖，顯示關於某些實施例的鰭式場效電晶體的形成當中的中間階段。
第19圖是一剖面圖，顯示關於某些實施例的具有實際外觀的鰭式場效電晶體。
第20圖是一流程圖，顯示關於某些實施例的鰭式場效電晶體的形成的製程。
要瞭解的是本說明書以下的揭露內容提供許多不同的實施例或範例，以實施本揭露的不同特徵。以下將配合所附圖式詳述本揭露之實施例，其中同樣或類似的元件將盡可能以相同的元件符號表示。在圖式中可能誇大實施例的形狀與厚度以便清楚表面本揭露之特徵。而本說明書以下的揭露內容是敘述各個構件及其排列方式的特定範例，以求簡化發明的說明。當然，這些特定的範例並非用以限定本揭露。例如，若是本說明書以下的揭露內容敘述了將一第一特徵形成於一第一特徵之上或上方，即表示其包含了所形成的上述第一特徵與上述第二特徵是直接接觸的實施例，亦包含了尚可將附加的特徵形成於上述第一特徵與上述第二特徵之間，而使上述第一特徵與上述第二特徵可能未直接接觸的實施例。另外，本說明書以下的揭露內容可能在各個範例中使用重複的元件符號，以使說 明內容更加簡化、明確，但是重複的元件符號本身並未指示不同的實施例及/或結構之間的關係。
此外，其與空間相關用詞。例如「在...下方」、「下方」、「較低的」、「下」、「在…上方」、「較高的」、「上」及類似的用詞，係為了便於描述圖示中一個元件或特徵與另一個(些)元件或特徵之間的關係。除了在圖式中繪示的方位外，這些空間相關用詞意欲包含使用中或操作中的裝置之不同方位。裝置可能被轉向不同方位(旋轉90度或其他方位)，則在此使用的空間相關詞也可依此相同解釋。
在此提供半導體裝置及其製造方法的各種例示的實施例，並敘述某些實施例的電晶體的形成當中的中間階段，討論某些實施例的某些變化。在各個圖式及敘述的實施例中，同樣或類似的元件是以相同的元件符號表示。在敘述的例示的實施例中，是使用鰭式場效電晶體(Fin Field-Effect Transistors；FinFETs)的形成作為例子來說明本揭露的概念。而平面電晶體亦可適用於本揭露的概念。
第1~18圖是透視圖及剖面圖，顯示關於本揭露的某些實施例的鰭式場效電晶體的形成當中的中間階段。在第1~18圖所示的步驟亦示意性地反映於第20圖所示的製程流程。
第1圖繪示一初始結構的透視圖。上述初始結構包含晶圓10，其更包括基底20。晶圓10可以是一半導體基底，上述半導體基底可以是一矽基底、一矽鍺(silicon germanium)基底或是以其他半導體材料形成的一基底。基底20可被摻雜有p型或n型不純物。例如為淺溝槽隔離(Shallow Trench Isolation；STI)區22等的隔離區可被形成為從基底20的上表面延伸至基底20內，其中基底20的上表面是晶圓10的一主表面10A。基底20之位於相鄰的淺溝槽隔離區22之間的部分，稱為半導體條24。在某些實施例中，半導體條24的上表面與淺溝槽隔離區22的上表面可實質上相互齊平。
淺溝槽隔離區22可包括一襯墊氧化層(未繪示)。上述襯墊氧化層可以以一熱氧化物形成，上述熱氧化物是經由基底20的一表面層的熱氧化而形成。上述襯墊氧化層亦可以是使用例如原子層沉積(Atomic Layer Deposition；ALD)、高密度電漿化學氣相沉積(High-Density Plasma Chemical Vapor Deposition；HDPCVD)或化學氣相沉積(Chemical Vapor Deposition；CVD)而形成的一沉積氧化矽層。淺溝槽隔離區22亦可在上述襯墊氧化層的上方包含一介電材料，其中可以以流動式化學氣相沉積(Flowable Chemical Vapor Deposition；FCVD)、旋轉塗佈法或其他類似方法來形成上述介電材料。
請參考第2圖，使淺溝槽隔離區22凹陷，因此半導體條24突出而高於淺溝槽隔離區22的上表面，以形成突出的鰭狀物24’。使淺溝槽隔離區22凹陷的蝕刻步驟可使用一乾蝕刻製程來施行，其中使用HF3與NH3作為蝕刻氣體。在上述蝕刻製程的過程中，可產生電漿，亦可加入氬。在本揭露提供的替代性的實施例中，是使用一溼蝕刻製程來施行淺溝槽隔離區22的凹陷，其蝕刻劑可包含例如稀釋的氫氟酸。
請參考第3圖，在突出的鰭狀物24’的上表面與側壁上，形成虛置(dummy)閘極堆疊結構30。虛置閘極堆疊結構30 可包含虛置閘介電質32與在虛置閘介電質32的上方的虛置閘極34。虛置閘極34可以使用例如多晶矽來形成，亦可以使用其他材料來形成。虛置閘極堆疊結構30亦可以在虛置閘極34的上方包括一(或複數個)硬罩幕層36。硬罩幕層36可以以氮化矽、碳氮化矽或其他類似材料來形成。虛置閘極堆疊結構30可以在單一的或複數個突出的鰭狀物24’及/或淺溝槽隔離區22的上方而與其交叉。虛置閘極堆疊結構30亦可具有一縱長方向，其正交於突出的鰭狀物24’的縱長方向。
接下來，在虛置閘極堆疊結構30上形成閘極間隔物38。在本揭露的某些例示的實施例中，閘極間隔物38是以例如碳氧氮化矽(silicon carbon-oxynitride；SiCON)、氮化矽或其他類似材料等的一介電材料來形成，並可以具有一單層結構或包含複數個介電層的多層結構。
然後，施行一蝕刻步驟(後文稱為「源/汲極凹陷」)，以蝕刻突出的鰭狀物24’之未被虛置閘極堆疊結構30與閘極間隔物38覆蓋的部分，成為示於第4圖的結構。上述凹陷可為異向性，因此使突出的鰭狀物24’之在虛置閘極堆疊結構30與閘極間隔物38的正下方的部分受到保護，而未被蝕刻。在本揭露的某些例示的實施例中，被凹陷的半導體條24的上表面24A可低於淺溝槽隔離區22的上表面22A。因此，在淺溝槽隔離區22之間形成凹部40。凹部40是位於虛置閘極堆疊結構30的兩側。
接下來，藉由在凹部40內選擇性地成長一半導體材料，形成磊晶區(源極/汲極區)，而成為在第5圖所示的結構。
然後，施行一蝕刻步驟(後文稱為「源/汲極凹陷」)，以蝕刻突出的鰭狀物24’之未被虛置閘極堆疊結構30與閘極間隔物38覆蓋的部分，成為示於第4圖的結構。上述凹陷可為異向性，因此使突出的鰭狀物24’之在虛置閘極堆疊結構30與閘極間隔物38的正下方的部分受到保護，而未被蝕刻。在本揭露的某些例示的實施例中，被凹陷的半導體條24的上表面24A可低於淺溝槽隔離區22的上表面22A。因此，在淺溝槽隔離區22之間形成凹部40。凹部40是位於虛置閘極堆疊結構30的兩側。
接下來，藉由在凹部40內選擇性地成長一半導體材料，形成磊晶區(源極/汲極區)，而成為在第5圖所示的結構。 在本揭露的某些例示的實施例中，磊晶區42包括矽鍺或矽。取決於所形成的鰭式場效電晶體為p型鰭式場效電晶體或n型鰭式場效電晶體，可以在磊晶的製程當中臨場(in-situ)摻雜p型或n型不純物。例如，當所形成的鰭式場效電晶體為p型鰭式場效電晶體，可成長矽鍺硼(silicon germanium boron；SiGeB)。相反地，當所形成的鰭式場效電晶體為n型鰭式場效電晶體，可成長矽磷(silicon phosphorous；SiP)或矽碳磷(silicon carbon phosphorous；SiCP)。在本揭露的替代性的實施例中，是以例如GaAs、InP、GaN、InGaAs、InAlAs、GaSb、AlSb、AlAs、AlP、GaP、上述之組合或上述之多層結構等的III-V族化合物半導體來形成磊晶區42。在以磊晶區42填充凹部40之後，磊晶區42的進一步的磊晶成長會使磊晶區42水平擴展，而可形成複數個刻面(facets)。
在上述磊晶步驟之後，可進一步以p型或n型不純物來佈植磊晶區42，以形成源極與汲極，其仍使用元件符號42。在本揭露的替代性的實施例中，在磊晶的過程中磊晶區42已被臨場摻雜p型或n型不純物時，則跳過上述佈植步驟。磊晶區42包含下部42A與上部42B，其中下部42A是形成於淺溝槽隔離區22中，上部42B則形成在淺溝槽隔離區22的上表面22A的上方。下部42A的側壁是藉由凹部40(第4圖)的形狀而成形，而可具有(實質上)筆直的邊緣，其亦可以是正交於基底20的主表面(例如底表面)的實質上垂直的邊緣。
第6A圖顯示具有已形成層間介電質(Inter-Layer Dielectric；ILD)46的結構的透明圖。在本揭露的某些實施例 中，在形成層間介電質46之前，在源極與汲極42之上形成一緩衝氧化物層(未繪示)與接觸蝕刻停止層(Contact Etch Stop Layer；CESL)47。可以以氧化矽來形成上述緩衝氧化物層，且可以以氮化矽、碳氮化矽或其他類似材料來形成接觸蝕刻停止層47。上述緩衝氧化物層與接觸蝕刻停止層47的形成，可使用例如原子層沉積等的一共形(conformal)沉積法。層間介電質46可包含使用例如流動式化學氣相沉積、旋轉塗佈法、化學氣相沉積或其他沉積法形成的一介電材料。層間介電質46亦可以以磷矽玻璃(Phospho-Silicate Glass；PSG)、硼矽玻璃(Boro-Silicate Glass；BSG)、硼磷矽玻璃(Boron-Doped Phospho-Silicate Glass；BPSG)、四乙氧基矽烷(Tetra Ethyl Ortho Silicate；TEOS)氧化物或其他類似材料來形成。可以施行例如化學機械研磨(Chemical Mechanical Polish；CMP)或機械研磨(mechanical grinding)等的平坦化步驟，以使層間介電質46、虛置閘極堆疊結構30與閘極間隔物38的上表面彼此互相齊平。
在第6A圖所示的結構的一剖面視圖是繪示於第6B圖，其中上述剖面視圖是由包含第6A圖所示的線A-A的垂直平面所獲得。接下來，以一金屬閘極與一取代閘介電質來置換包括硬罩幕層36、虛置閘極34與虛置閘介電質32的虛置閘極堆疊結構30。示於第7圖至第18圖的剖面視圖是由相同的包含第6A圖所示的線A-A的垂直平面所獲得。在第7圖至第18圖，繪示了淺溝槽隔離區22的上表面22A的水平，而突出的鰭狀物24’是在淺溝槽隔離區22的上表面22A的上方。
移除如第6A與6B圖所示的硬罩幕層36、虛置閘極34與虛置閘介電質32，其結果，形成如第7圖所示的開口48，其對應的步驟是繪示於第20圖所示的流程圖中的步驟202。突出的鰭狀物24’的上表面及側壁是曝露於開口48。
第7圖進一步繪示了在某些實施例中的閘極間隔物50的形成。在替代性的實施例中，則不形成閘極間隔物50。為了形成閘極間隔物50，例如可使用如原子層沉積或化學氣相沉積等的沉積法來形成一包覆式的閘極間隔物層。上述包覆式的閘極間隔物層是與下層共形。在本揭露的某些實施例中，是以氮化矽(SiN)、SiC、SiON或其他介電材料來形成上述包覆式的閘極間隔物層，其材料可相同或不同於閘極間隔物38的材料以及接觸蝕刻停止層47與層間介電質46的材料的任一個。閘極間隔物50使後續形成的金屬閘極遠離源極與汲極42，而減低其間發生漏電流與短路的機率。
接下來，請參考第8圖，形成閘介電質52，其延伸進入開口48，其對應的步驟是繪示於第20圖所示的流程圖中的步驟204。在本揭露的某些實施例中，閘介電質52包含介面層(Interfacial Layer；IL)54作為其下部。介面層54是形成在突出的鰭狀物24’的曝露的表面上。介面層54可包括經由突出的鰭狀物24’的熱氧化、一化學性氧化製程或一沉積製程而形成的例如氧化矽層等的一氧化物層。閘介電質52亦可包括形成於介面層54的上方的高介電常數介電層56。高介電常數介電層56包括例如氧化鉿、氧化鑭、氧化鋁、氧化鋯或其類似物等的一高介電常數介電材料。上述高介電常數介電材料的介電常數(k值) 大於3.9，並可大於7.0。高介電常數介電層56是在介面層54之上，並可以接觸介面層54。高介電常數介電層56可以被形成為一共形層，並可以延伸到突出的鰭狀物24’的側壁上以及閘極間隔物38/50的上表面與側壁上。在本揭露的某些實施例中，是使用原子層沉積或化學氣相沉積來形成高介電常數介電層56。
請進一步參考第8圖，沉積疊層結構58，其對應的步驟是繪示於第20圖所示的流程圖中的步驟206。疊層結構58中的複數個分層(sub-layers)並未分開顯示，而實際上由於這些分層是以不同材料及/或具有不同元素百分比而可以彼此區分。其沉積可使用例如原子層沉積或化學氣相沉積等的一共形沉積法來施行，因此疊層結構58(與其每個分層)的垂直部分的厚度T1與水平部分的厚度T2具有實質上彼此相同的厚度。疊層結構58延伸進入開口48，其某些部分是在層間介電質46的上方。
疊層結構58可包括一擴散阻障層與在上述擴散阻障層的上方的一或複數個功函數層。上述擴散阻障層可以是以氮化鈦形成，並可以(或可以未)被摻雜有矽。氮化鈦被摻雜有矽時，有時亦被稱為氮化鈦矽(Ti-Si-N或TSN)。氮化鈦或氮化鈦矽為一導體材料。上述功函數層決定閘極的功函數，並包括至少一層或是以不同材料形成的複數層。上述功函數層的特定材料可根據對應的鰭式場效電晶體為一n型鰭式場效電晶體或一p型鰭式場效電晶體而選擇。例如，當鰭式場效電晶體為一n型鰭式場效電晶體，其功函數層可包括一TaN層與在上述TaN層上方的一鈦鋁(TiAl)層。當鰭式場效電晶體為一p型鰭式場效電晶體，其功函數層可包括一TaN層、在上述TaN層上方的一TiN層與在上述TiN層上方的一鈦鋁層。在沉積疊層結構58之後，形成一阻障層60，阻障層60可以是另一個TiN層。TiN層60的形成可使用化學氣相沉積，並可作為一阻擋層，其對應的步驟是繪示於第20圖所示的流程圖中的步驟206。在某些實施例中，TiN層60可以不含矽。
接下來，沉積含金屬材料層62，其具有與TiN層60的上表面有物理性接觸的一底表面，其對應的步驟是繪示於第20圖所示的流程圖中的步驟208。含金屬材料層62的形成可通過化學氣相沉積、原子層沉積或物理氣相沉積(Physical Vapor Deposition；PVD)來達成。在本揭露的某些實施例中，是使用物理氣相沉積，其是藉由使用置於對應的晶圓10的上方的一鈷靶材來施行。此外，亦在物理氣相沉積的過程中引入前驅物。因此，其沉積包括物理氣相沉積與化學氣相沉積的二者。在某些實施例中，用於沉積含金屬材料層62的上述前驅物包括一含鈷的前驅物、一含矽的前驅物以及還可包括其他氣體。例如，用於沉積含金屬材料層62的上述前驅物可包括四乙氧基矽烷(Tetra Ethyl Ortho Silicate；TEOS)、SiHCl3以及例如八羰基二鈷(di-cobalt octacarbonyl)、亞硝基鈷錯合物(cobalt nitrosyl complexes)或亞鈷與鈷的β-二酮配體(β-diketonates)及其他類似物的含鈷的前驅物。
在某些實施例中，含金屬材料層62包括層62A及在層62A的上方的層62B。在某些實施例中，層62A是矽化鈷 (CoxSiy，其中x與y為原子百分比並具有0與1.0之間的值)。層62B是不含或實質上不含(例如具有低於百分之一的原子百分比的)矽或其他元素的一鈷層。在以層62A與層62B的二者作為含鈷層之下，可以減少製造成本。例如，可以使用相同的含矽的前驅物與含鈷的前驅物(以及還可能具有一附加的鈷靶材)來沉積層62A與層62B的二者。在一例示的沉積製程中，在沉積層62A(CoxSiy)時，晶圓10的溫度可以在約85℃與約120℃之間。在結束層62A的沉積之後，將晶圓10的溫度降低，例如降至25℃，並使用相同的前驅物(搭配或不搭配使用上述附加的鈷靶材)而形成不含或實質上不含矽的層62B。在某些實施例中，從層62A的沉積轉換到層62B的沉積，是藉由降低晶圓10的溫度來達成，同時維持其他製程條件(例如前驅物的流速、分壓、功率等)不變。含金屬材料層62的形成亦可藉由漸變式地降低晶圓10的溫度來達成，因此層62A具有漸變式降低的矽含量，其中層62A的上部的矽含量低於對應的下部的矽含量。溫度的漸變式降低可以是連續性的。溫度的漸變式降低亦可經由驟變的階級，其意義為溫度驟降至一較低的階級，並在降至另一個較低的階級之前溫度維持不變一段時間。持續上述漸變式的轉變，直到對應形成的層為不含或實質上不含矽，此時則開始形成層62B。然後，當所形成的層為一鈷層時，溫度可為固定。因此，整個層62B可以是不含或實質上不含矽及其他元素，而層62A則具有漸變式地(驟然或連續式地)降低的矽百分比。
在替代性的實施例中，較下方的層62A為一鈷層，而較上方的層62B為一矽化鈷層，其形成製程可以將前文討論的用以形成層62A與層62B的製程互調。
在某些實施例中，層62A是以金屬矽化物形成(使用鈷以外的金屬)，上述金屬矽化物可以是TixSiy、NixSiy、WxSiy、MoxSiy、TaxSiy；而層62B為不含或實質上不含矽及其他元素的一鈷層。
在某些實施例中，整個含金屬材料層62是以一均質的材料形成，其可以是鈷(不含或實質上不含矽及其他元素)或是例如TixSiy、NixSiy、WxSiy、MoxSiy或TaxSiy等的一金屬矽化物。整個含金屬材料層62具有一均勻的電阻率。當以矽化物層形成時，整個含金屬材料層62具有的上述百分比x與y為常數並具有均勻的電阻率，或是可具有從底部到頂部為漸變的(例如漸變式地減少或漸變式地增加的)百分比x與y。其形成的製程因此在整個含金屬材料層62的形成中，自始至終具有不變的製程條件(例如溫度、壓力、流速或其他同類的製程條件)。
接下來，施行例如化學機械研磨(Chemical Mechanical Polish；CMP)或機械研磨(mechanical grinding)等的一平坦化步驟，因此移除在層間介電質46的上方的高介電常數介電層56、疊層結構58、阻障層60及含金屬材料層62，其對應的步驟是繪示於第20圖所示的流程圖中的步驟210。接下來，如第9圖所示，將高介電常數介電層56、疊層結構58、阻障層60及含金屬材料層62回蝕，形成凹部63，其對應的步驟是繪示於第20圖所示的流程圖中的步驟212。介面層54、高介電常數介電層56、疊層結構58、阻障層60及含金屬材料層62的留下來的部分在後文稱為取代閘極堆疊結構64。
如第10圖所示，在取代閘極堆疊結構64的上方形成硬罩幕66，其對應的步驟是繪示於第20圖所示的流程圖中的步驟212。在本揭露的某些實施例中，硬罩幕66的形成包括一沉積步驟以形成一包覆式的介電材料、以及一平坦化步驟以移除在閘極間隔物38與層間介電質46的上方的多餘的上述介電材料。硬罩幕66可例如以氮化矽形成。
第11圖至第14圖是繪示下源極/汲極接觸插塞的形成。請參考第11圖，將介電層67形成在第10圖所示的結構的上方，接下來塗佈一圖形化的光阻(未繪示)。接著，蝕刻介電層67、層間介電質46與接觸蝕刻停止層47，以形成接觸開口68，其對應的步驟是繪示於第20圖所示的流程圖中的步驟214。
進一步參考第11圖，例如使用物理氣相沉積，沉積金屬層72(例如一鈦層或鉭層)。然後，在金屬層72的上方沉積阻障層74，阻障層74可以是例如一氮化鈦層或一氮化鉭層等的一金屬氮化物層，其對應的步驟是繪示於第20圖所示的流程圖中的步驟216。阻障層74的形成可以使用化學氣相沉積。金屬層72與阻障層74均為共形層，並延伸進入接觸開口68。
然後，如第12圖所示，施行一退火步驟以形成源極/閘極矽化物區76，其對應的步驟是繪示於第20圖所示的流程圖中的步驟218。上述退火步驟可以通過快速熱退火(Rapid Thermal Anneal；RTA)、爐內退火(furnace anneal)或其他類似製程來施行。因此，金屬層72的底部和源極與汲極42反應，以形成源極/閘極矽化物區76。在矽化製程之後，留下金屬層72的側壁部分。在本揭露的某些實施例中，源極/閘極矽化物區 76的上表面是與阻障層74的底表面接觸。
接下來，如第13圖所示，將含金屬層78沉積在阻障層74的上方並與阻障層74接觸，其對應的步驟是繪示於第20圖所示的流程圖中的步驟220。含金屬層78可以以選自含金屬層62的候選材料的相同族群的材料所形成。此外，含金屬層78的形成方法、材料及結構亦可選自含金屬層62的候選的形成方法、候選材料與候選結構。例如，含金屬層78可以是一均質的鈷層或一均質的金屬矽化物層，或是可包含一下層78A與一上層78B，其中上層78B與下層78A的形成方法、材料及結構，其任何組合可分別參考前文討論的層62A與62B。
然後，施行例如一化學機械研磨步驟等的一平坦化步驟，以移除金屬層72與阻障層74之在介電層67上方的部分，其對應的步驟是繪示於第20圖所示的流程圖中的步驟222。所形成的結構示於第14圖，其繪示源極/汲極接觸插塞79。每個源極/汲極接觸插塞79包括含金屬層78、阻障層74與金屬層72。
第15圖至第17圖繪示一閘極接觸插塞的形成，其對應的步驟是繪示於第20圖所示的流程圖中的步驟224。請參考第15圖，使用一微影罩幕(未繪示)來施行一微影製程，以蝕穿介電層67。然後，移除硬罩幕66(第14圖)而形成開口80。在本揭露的某些實施例中，開口80的形成包含一異向性蝕刻以蝕穿介電層67以及一等向性蝕刻(乾式或濕式)或一異向性蝕刻以移除硬罩幕66。閘極間隔物50(如果有的話)的側壁因此而被曝露。在未形成閘極間隔物50的實施例中，則是閘極間隔物38的 側壁被曝露於開口80。選擇用以蝕刻介電層67與硬罩幕66的蝕刻劑，而使閘極間隔物50與38未被實質蝕刻。在本揭露的替代性的實施例中，開口80比硬罩幕66狹窄，因此在蝕刻後，硬罩幕66的某些邊緣部分被留下。
請參考第16圖，沉積阻障層82與含金屬材料層84。阻障層82可以以氮化鈦或氮化鉭形成。含金屬材料層84的形成方法、材料及結構，可以分別選自含金屬材料層62的候選的形成方法、候選材料及候選結構，因此在此處不再重複其細節，而可以參考含金屬材料層62的前文的討論。因此，類似於含金屬材料層62，含金屬材料層84亦可以以鈷、一金屬矽化物或上述的複合層來形成。在一後續的步驟，施行例如一化學機械研磨步驟等的一平坦化步驟。上述平坦化步驟可施行到移除全部的介電層67以及曝露出層間介電質46為止。因此，介電層67是作為一犧牲層使用。所形成的結構示於第17圖，其繪示以阻障層82與含金屬材料層84的留下來的部分形成的接觸插塞86。因此，形成了鰭式場效電晶體300。
第18圖繪示蝕刻停止層88、層間介電質90的形成以及在蝕刻停止層88與層間介電質90中形成源極/汲極接觸插塞(介層窗)92。蝕刻停止層88可以以碳化矽、氧氮化矽、碳氮化矽或其他類似材料來形成，並可以使用例如化學氣相沉積等的一沉積法形成。層間介電質90可包含選自磷矽玻璃、硼矽玻璃、硼磷矽玻璃、摻氟的二氧化矽(Fuorine-doped Silicon Glass；FSG)、四乙氧基矽烷氧化物或其他無孔質的低介電常數材料的一材料來形成。層間介電質90的形成可使用旋轉塗佈 法、流動式化學氣相沉積(Flowable Chemical Vapor Deposition；FCVD)或其他類似方法，或使用例如電漿增益化學氣相沉積法(Plasma Enhanced Chemical Vapor Deposition；PECVD)、低壓化學氣相沉積法(Low Pressure Chemical Vapor Deposition；LPCVD)或其他類似方法。
將層間介電質90與蝕刻停止層88予以蝕刻以形成開口(被介層窗92佔據)。上述蝕刻的施行，可使用例如反應性離子蝕刻(Reactive Ion Etch；RIE)。在一後續的步驟中，形成介層窗92。在某些實施例中，介層窗92包含阻障層94以及在阻障層94的上方的含金屬層96。在本揭露的某些實施例中，介層窗92的形成包括：對於蝕刻停止層88與層間介電質90予以蝕刻，以形成接觸開口；形成一包覆式的阻障層並在上述包覆式的阻障層的上方形成一含金屬材料；以及施行一平坦化步驟以移除上述包覆式的阻障層與上述含金屬材料的多餘的部分。阻障層94可以以例如氮化鈦或氮化鉭等的一金屬氮化物形成。含金屬層96的材料、結構及形成方法可分別選自含金屬層62的候選材料、候選結構與候選的形成方法，因此在此處不再重複其細節。
介層窗92所具有的側壁會帶有傾角α，傾角α的範圍在約80度與約90度之間。介層窗92亦具有頂部寬度Wtop，其大於對應的底部寬度Wbottom。例如比值Wtop/Wbottom可在約1.2與約1.5的範圍之間。這樣的外形，有益於階級覆蓋(gap filling)。
第19圖繪示關於某些實施例的一鰭式場效電晶體 的一剖面視圖。在本揭露的某些實施例中，如第19圖所示，源極/汲極接觸插塞92具有實質上筆直且傾斜的下部以及曲線狀的上部，圖中繪製虛線93以顯示上述上部與上述下部之間的水平轉換線。與對應的下部相比，上述側壁的上部可具有實質上較為急遽的斜率變化。圖中，源極/汲極接觸插塞92的高度是標為H1，而源極/汲極接觸插塞92的頂部的高度是標為H2，頂部寬度與底部寬度是分別標為Wtop與Wbottom。底部寬度Wbottom是由源極/汲極接觸插塞92的頂部起算，向底部達源極/汲極接觸插塞92的高度H1的百分之九十五之處所測量。源極/汲極接觸插塞92之在上述水平轉換線的寬度是標為Wtran。在本揭露的某些實施例中，比值Wtran/Wbottom可以在約1.2與約1.5之間的範圍；比值H2/H1可以在約0.1與約0.2之間的範圍；傾角α可以在約80度與約90度之間的範圍，並可以在85度附近。雖然未詳細敘述源極/汲極接觸插塞79的尺寸與傾角的細節，但源極/汲極接觸插塞79可以具有與接觸插塞92相似的外形。
本揭露的實施例具有一些有益的特徵。在蝕刻介電層時，可能會產生聚合物。為了移除由於蝕刻介電層而形成的聚合物殘渣，可使用一酸性溶液(例如過氧化氫)。鈷對於酸有良好的抗性，而酸性溶液會使受曝金屬的腐蝕。如果使用鎢，其被蝕刻的可能性較大。另一方面，鈷對於腐蝕有較大的抵抗能力，可以減低例如金屬閘極損失等的因為金屬的腐蝕所產生的問題。鈷亦具有比鎢還小的粗糙度，而使其成為用於形成高品質薄膜的較佳材料。
此外，由於散射效應，在非常小的尺寸，與鎢相 比，鈷與金屬矽化物具有較低的電阻率。此外，對於例如TiN等的某些阻障材料，鎢不具有良好的黏著力。因此在傳統上，是形成一鎢孕核層，之後使用化學氣相沉積來沉積鎢。上述鎢孕核層具有的電阻率是在約200μOhm˙cm與約250μOhm˙cm之間，其遠高於化學氣相沉積的鎢的電阻率(約5.7μOhm˙cm)。因此，上述鎢孕核層的電阻率大幅降低所形成的電晶體的效能。另一方面，鈷(或金屬矽化物)則具有非常低的電阻率(以矽化鈷為例，為約5.8μOhm˙cm)，且對於TiN具有良好的黏著力。因此，藉由鈷及/或金屬矽化物的應用，對於下層的阻障層的黏著力良好，且使金屬閘極的電阻率低。
在本揭露的某些實施例中，一種半導體裝置的製造方法，包含形成一電晶體，其包括：在一半導體區上形成一閘介電質；在上述閘介電質的上方形成一閘極；及形成一源/汲極區，上述源/汲極區延伸而進入上述半導體區。上述方法更包含：形成一源/汲極接觸插塞，上述源/汲極接觸插塞在上述源/汲極區的上方並電性耦合於上述源/汲極區；以及形成一閘極接觸插塞，上述閘極接觸插塞在上述閘極的上方並與上述閘極接觸。上述閘極的形成、上述源/汲極接觸插塞的形成及上述閘極接觸插塞的形成的至少一個包括：形成一金屬氮化物阻障層；及在上述金屬氮化物阻障層的上方形成一含金屬層且上述含金屬層接觸上述金屬氮化物阻障層。上述含金屬層包括一鈷層與一金屬矽化物層的至少一個。
在上述半導體裝置的製造方法的一例，上述閘極的形成包括：沉積一含氮化鈦層；在上述含氮化鈦層的上方沉 積一功函數層，其中上述金屬氮化物阻障層是在上述功函數層的上方；以及施行一平坦化步驟以移除上述含氮化鈦層與上述功函數層的多餘的部分。
在上述半導體裝置的製造方法的一例，上述源/汲極接觸插塞的形成包括：蝕刻一層間介電質以形成一源/汲極接觸開口，其中上述半導體區曝露於上述源/汲極接觸開口；沉積一金屬層，上述金屬層的一部分延伸而進入上述源/汲極接觸開口，其中上述金屬氮化物阻障層是沉積於上述金屬層的上方；施行一退火步驟以形成一源/汲極矽化物；以及施行一平坦化步驟以移除上述金屬層與上述金屬氮化物阻障層的多餘部分。
在上述半導體裝置的製造方法的一例，上述閘極接觸插塞的形成包括：移除在複數個閘極間隔物的對面部分之間的一硬罩幕，其中上述金屬氮化物阻障層與上述含金屬層延伸而進入移除上述硬罩幕而留下來的開口；以及施行一平坦化步驟以移除上述金屬氮化物阻障層與上述含金屬層的多餘部分。
在上述半導體裝置的製造方法的一例，上述含金屬層的沉積包括：沉積一金屬矽化物層；以及在上述金屬矽化物層的上方沉積一鈷層，上述鈷層實質上不含矽。
在上述半導體裝置的製造方法的一例，上述金屬矽化物層的上部具有逐漸降低的矽百分比而低於對應的上述金屬矽化物層的下部的矽百分比。
在上述半導體裝置的製造方法的一例，上述含金 屬層是以具有均勻的電阻率的鈷形成，且上述含金屬層實質上不含鈷以外的元素。
在上述半導體裝置的製造方法的一例，上述含金屬層的整體是以具有均勻的電阻率的上述金屬矽化物層形成。
在上述半導體裝置的製造方法的一例，上述含金屬層的沉積包括：沉積上述金屬矽化物層，且當沉積上述金屬矽化物層時，改變對應的晶圓的溫度。
在本揭露的某些實施例中，一種半導體裝置的製造方法，包含：形成一電晶體，其包括：在一半導體區的上方形成一虛置(dummy)閘極堆疊結構；形成一層間介電質，其中上述虛置閘極堆疊結構是在上述層間介電質中；移除上述虛置閘極堆疊結構，以在上述層間介電質形成一開口；形成一取代閘極介電質，上述取代閘極介電質延伸而進入上述開口；在上述取代閘極介電質的上方形成一功函數金屬層；在上述取代閘極介電質的上方形成一阻障層，上述阻障層包括氮化鈦；以及沉積一含鈷層，上述含鈷層延伸而進入上述開口。上述含鈷層在上述阻障層上並與上述阻障層接觸。施行一平坦化步驟以移除上述取代閘極介電質、上述功函數金屬層、上述阻障層與上述含鈷層的多餘部分，以形成一取代閘極堆疊結構。形成一源極區與一汲極區，其中上述源極區與上述汲極區是在上述取代閘極堆疊結構的兩側。
在上述半導體裝置的製造方法的一例，上述含鈷層包括鈷而實質上不含鈷以外的元素。
在上述半導體裝置的製造方法的一例，上述含鈷 層包括一矽化鈷層。
在上述半導體裝置的製造方法的一例，上述含鈷層更包括一鈷層，上述鈷層不含鈷以外的元素，上述鈷層在上述矽化鈷層的上方。
在上述半導體裝置的製造方法的一例，上述矽化鈷層與上述鈷層是使用相同的前驅物形成，且沉積上述鈷層的溫度低於用以沉積上述矽化鈷層的溫度。
在上述半導體裝置的製造方法的一例，上述含鈷層的沉積是在連續變化的溫度下施行，且上述矽化鈷層具有連續變化的矽百分比。
在本揭露的某些實施例中，一種半導體裝置包含：複數個閘極間隔物、一閘介電質與一閘極。上述閘極包括：一第一金屬氮化物層，在上述閘介電質的上方；及一功函數金屬層，在上述第一金屬氮化物層的上方。上述閘介電質與上述閘極在上述些閘極間隔物之間延伸。一閘極接觸插塞是在上述閘極的上方並接觸上述閘極。一源/汲極區是鄰接上述閘極。一源/汲極接觸插塞是在上述源/汲極區的上方並電性耦合於上述源/汲極區。上述閘極、上述源/汲極接觸插塞與上述閘極接觸插塞的至少一個包含：一第二金屬氮化物層；及一含金屬層，在上述第二金屬氮化物層的上方並接觸上述第二金屬氮化物層。上述含金屬層包括一鈷層與一金屬矽化物層的至少一個。
在上述半導體裝置的一例，上述含金屬層的整體是以鈷形成且具有均勻的電阻率，且上述含金屬層實質上不含 鈷以外的金屬。
在上述半導體裝置的一例，上述含金屬層的整體是以矽化鈷形成。
在上述半導體裝置的一例，上述含金屬層包括：一金屬矽化物層；以及一鈷層，實質上不含矽且在上述金屬矽化物層的上方。
在上述半導體裝置的一例，上述金屬矽化物層包含矽化鈷，且上述矽化鈷的上部具有逐漸降低的矽百分比而低於對應的上述矽化鈷的下部的矽百分比。
前述內文概述了許多實施例的特徵，使本技術領域中具有通常知識者可以從各個方面更佳地了解本揭露。本技術領域中具有通常知識者應可理解，且可輕易地以本揭露為基礎來設計或修飾其他製程及結構，並以此達到相同的目的及/或達到與在此介紹的實施例等相同之優點。本技術領域中具有通常知識者也應了解這些相等的結構並未背離本揭露的發明精神與範圍。在不背離本揭露的發明精神與範圍之前提下，可對本揭露進行各種改變、置換或修改。

Claims (13)

  1. 一種半導體裝置的製造方法，包含：形成一電晶體，包括：在一半導體區上形成一閘介電質；在該閘介電質的上方形成一閘極；形成一源/汲極區，該源/汲極區延伸而進入該半導體區；形成一源/汲極接觸插塞，該源/汲極接觸插塞在該源/汲極區的上方並電性耦合於該源/汲極區；以及形成一閘極接觸插塞，該閘極接觸插塞在該閘極的上方並與該閘極接觸；其中，該閘極的形成、該源/汲極接觸插塞的形成及該閘極接觸插塞的形成的至少一個包括：移除在複數個閘極間隔物的對面部分之間的一硬罩幕；形成一金屬氮化物阻障層；在該金屬氮化物阻障層的上方形成一含金屬層且該含金屬層接觸該金屬氮化物阻障層，其中該含金屬層包括一鈷層與一金屬矽化物層的至少一個，其中上述金屬氮化物阻障層與上述含金屬層延伸而進入移除上述硬罩幕而留下來的開口；以及施行一平坦化步驟以移除上述金屬氮化物阻障層與上述含金屬層的多餘部分。
  2. 如申請專利範圍第1項所述之半導體裝置的製造方法，其中該含金屬層的沉積包括：沉積一金屬矽化物層；以及在該金屬矽化物層的上方沉積一鈷層，該鈷層實質上不含矽。
  3. 如申請專利範圍第2項所述之半導體裝置的製造方法，其中該金屬矽化物層的上部具有逐漸降低的矽百分比而低於對應的該金屬矽化物層的下部的矽百分比。
  4. 如申請專利範圍第1項所述之半導體裝置的製造方法，其中該含金屬層是以具有均勻的電阻率的鈷形成，且該含金屬層實質上不含鈷以外的元素。
  5. 如申請專利範圍第1項所述之半導體裝置的製造方法，其中該含金屬層的整體是以具有均勻的電阻率的該金屬矽化物層形成。
  6. 如申請專利範圍第1項所述之半導體裝置的製造方法，其中該含金屬層的沉積包括：沉積該金屬矽化物層，且當沉積該金屬矽化物層時，改變對應的晶圓的溫度。
  7. 一種半導體裝置的製造方法，包含：在一半導體區的上方形成一虛置(dummy)閘極堆疊結構；形成一層間介電質(Inter-Layer Dielectric；ILD)，其中該虛置閘極堆疊結構是在該層間介電質中；移除該虛置閘極堆疊結構，以在該層間介電質形成一開口；形成一取代閘極介電質，該取代閘極介電質延伸而進入該開口；在該取代閘極介電質的上方形成一功函數金屬層；在該取代閘極介電質的上方形成一阻障層，該阻障層包括氮化鈦；沉積一含鈷層，該含鈷層延伸而進入該開口，其中該含鈷層在該阻障層上並與該阻障層接觸，其中沉積該含鈷層包括沉積一矽化鈷層；施行一平坦化步驟以移除該取代閘極介電質、該功函數金屬層、該阻障層與該含鈷層的多餘部分，以形成一取代閘極堆疊結構；以及形成一源極區與一汲極區，其中該源極區與該汲極區是在該取代閘極堆疊結構的兩側。
  8. 如申請專利範圍第7項所述之半導體裝置的製造方法，其中該含鈷層更包括一鈷層，該鈷層不含鈷以外的元素，該鈷層在該矽化鈷層的上方。
  9. 一種半導體裝置，包含：複數個閘極間隔物；一閘介電質，延伸進入該些閘極間隔物之間的空間；以及一閘極，包括：一第一金屬氮化物層，在該閘介電質的上方；一功函數金屬層，在該第一金屬氮化物層的上方，其中該第一金屬氮化物層與該功函數金屬層在該些閘極間隔物之間延伸；一閘極接觸插塞，在該閘極的上方並接觸該閘極；一源/汲極區，鄰接該閘極；以及一源/汲極接觸插塞，在該源/汲極區的上方並電性耦合於該源/汲極區；其中，該閘極、該源/汲極接觸插塞與該閘極接觸插塞的至少一個包含：一第二金屬氮化物層；以及一含金屬層，在該第二金屬氮化物層的上方並接觸該第二金屬氮化物層，其中該含金屬層包括一鈷層與一金屬矽化物層的至少一個。
  10. 如申請專利範圍第9項所述之半導體裝置，其中該含金屬層的整體是以鈷形成且具有均勻的電阻率，且該含金屬層實質上不含鈷以外的金屬。
  11. 如申請專利範圍第9項所述之半導體裝置，其中該含金屬層的整體是以矽化鈷形成。
  12. 如申請專利範圍第9項所述之半導體裝置，其中該含金屬層包括：一金屬矽化物層；以及一鈷層，實質上不含矽且在該金屬矽化物層的上方。
  13. 如申請專利範圍第12項所述之半導體裝置，其中該金屬矽化物層包含矽化鈷，且該矽化鈷的上部具有逐漸降低的矽百分比而低於對應的該矽化鈷的下部的矽百分比。
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