TW202320221A - 半導體結構與其製作方法 - Google Patents

半導體結構與其製作方法 Download PDF

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TW202320221A
TW202320221A TW111114793A TW111114793A TW202320221A TW 202320221 A TW202320221 A TW 202320221A TW 111114793 A TW111114793 A TW 111114793A TW 111114793 A TW111114793 A TW 111114793A TW 202320221 A TW202320221 A TW 202320221A
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Taiwan
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source
isolation layer
layer
drain
contact plug
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TW111114793A
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TWI820678B (zh
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李資良
鄭柏賢
施伯錚
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台灣積體電路製造股份有限公司
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Abstract

一種結構包括：半導體區上方的閘極堆疊、閘極堆疊之一側上的源極/汲極區、源極/汲極區之一部分上方的觸點蝕刻終止層、觸點蝕刻終止層上方的層間介電質、源極/汲極區上方的矽化物區、矽化物區上方且接觸矽化物區的源極/汲極觸點栓塞，及包圍源極/汲極觸點栓塞的隔離層。在源極/汲極觸點栓塞的俯視圖中，源極/汲極觸點栓塞為狹長的，且隔離層包括源極/汲極觸點栓塞之末端處的末端部分及源極/汲極觸點栓塞之相對末端之間的中間部分。末端部分的末端部分厚度大於中間部分的中間部分厚度。

Description

用於減少觸點之間的洩漏之隔離層
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在積體電路之製造中，源極/汲極觸點栓塞用於連接至電晶體之源極及汲極區以及閘極。源極/汲極觸點栓塞通常連接至源極/汲極矽化物區，源極/汲極觸點栓塞之形成製程包括在層間介電質中形成觸點開口，沉積延伸至觸點開口中的金屬層且接著執行退火以使金屬層與源極/汲極區的矽/鍺反應。源極/汲極觸點栓塞接著形成於剩餘觸點開口中。
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以下揭示內容提供用於實施本揭露之不同特徵的許多不同實施例或實例。下文描述組件及配置之特定實例以簡化本揭露。當然，這些組件及配置僅為實例且並非意欲為限制性的。舉例而言，在以下描述中第一特徵於第二特徵上方或上的形成可包括第一及第二特徵直接接觸地形成的實施例，且亦可包括額外特徵可形成於第一特徵與第二特徵之間使得第一特徵及第二特徵可不直接接觸的實施例。此外，本揭露在各種實例中可重複參考數字及/或字母。此重複係出於簡單及清楚之目的，且本身並不指明所論述之各種實施例及/或組態之間的關係。
另外，空間相對術語，諸如「下伏」、「下方」、「下部」、「上覆」、「上部」及類似者本文中可出於易於描述而使用以描述如諸圖中圖示的一個元素或特徵與另一(些)元素或特徵之關係。空間相對術語意欲涵蓋裝置之使用或操作中除了諸圖中描繪之定向外的不同定向。設備可以其他方式定向(旋轉90度或處於其他定向)，且本文中使用之空間相對描述詞可同樣經因此解譯。
根據一些實施例，提供電晶體及形成電晶體的方法。隔離層經形成以減少相鄰源極/汲極觸點栓塞之間且觸點栓塞與閘極觸點栓塞之間的洩漏。根據一些實施例，鰭片場效電晶體(Fin Field-Effect Transistor，FinFET)的形成用作實例以解釋本揭露的概念。諸如平面電晶體之其他類型電晶體亦可採用本揭露的概念。本文中所論述之實施例用以提供實例以使得能夠製造或使用本揭露之標的，且熟習此項技術者將易於理解可進行同時保持在不同實施例之預期範疇內的修改。貫穿各種視圖及說明性實施例，類似參考數字用以指定類似元件。儘管方法實施例可論述為以特定次序執行，但其他方法實施例可以任何邏輯次序執行。
第1圖至第4圖、第5A圖、第5B圖、第6圖、第7圖、第8A圖、第8B圖、第9A圖、第9B圖、第10A圖、第10B圖、第10C圖、第11A圖、第11B圖、第12A圖、第12B圖、第13A圖、第13B圖、第14A圖、第14B圖、第15A圖、第15B圖、第15C圖、第16A圖、第16B圖、第17圖及第18圖圖示根據本揭露之一些實施例的形成FinFET及隔離層中中間階段的橫截面圖及透視圖。繪示於這些諸圖中的製程亦示意性地反映於如第19圖中所繪示的製程流程200中。
第1圖圖示形成於晶圓10上之初始結構的透視圖。晶圓10包括基板20。基板20可為半導體基板，該半導體基板可為矽基板、矽鍺基板，或由其他半導體材料形成的基板。基板20可摻雜有p型或n型雜質。諸如淺溝槽隔離(Shallow Trench Isolation，STI)區22之隔離區可經形成以自基板20之頂表面延伸至基板20中。各別製程圖示為如第19圖中繪示之製程流程200中的製程202。基板20的相鄰STI區22之間的數個部分被稱作半導體條帶24。根據一些實施例，半導體條帶24之頂表面及STI區22的頂表面可彼此實質上齊平。
根據本揭露之一些實施例，半導體條帶24為原始基板20的數個部分，且因此半導體條帶24的材料與基板20的材料相同。根據本揭露之替代性實施例，半導體條帶24為藉由蝕刻基板20的在STI區22之間的數個部分以形成凹座且執行磊晶製程以使另一半導體材料重新生長於凹座中形成的替換條帶。因此，半導體條帶24由不同於基板20之材料的半導體材料形成。根據一些實施例，半導體條帶24由矽鍺、碳化矽或III-V族化合物半導體材料形成。
STI區22可包括襯裡氧化物(圖中未示)，該襯裡氧化物可為經由基板20之表面層的熱氧化形成的熱氧化物。襯裡氧化物亦可為使用例如原子層沉積(Atomic Layer Deposition，ALD)、高密度電漿化學氣象沉積(High-Density Plasma Chemical Vapor Deposition，HDPCVD)、化學氣相沉積(Chemical Vapor Deposition，CVD)形成的經沉積氧化物層。STI區22亦可包括襯裡氧化物上方的介電材料，其中介電材料可使用可流動化學氣相沉積(Flowable Chemical Vapor Deposition，FCVD)、旋塗或類似者來形成。
參看第2圖，STI區22 經凹陷，使得半導體條帶24之頂部部分突出高於STI區22之剩餘部分的頂表面22T以形成突出半導體鰭片24’。各別製程圖示為如第19圖中繪示之製程流程200中的製程204。蝕刻可使用乾式蝕刻製程來執行，其中NF 3及NH 3用作蝕刻氣體。在蝕刻製程期間，可產生電漿。亦可包括氬。根據本揭露之替代性實施例，STI區22之凹陷使用濕式蝕刻製程執行。舉例而言，蝕刻化學物質可包括HF。
在上文圖示之實施例中，鰭片可由任何合適方法來圖案化。舉例而言，鰭片可使用一或多種光學微影製程，包括雙重圖案化或多重圖案化製程來圖案化。大體而言，雙重圖案化或多重圖案化製程組合光學微影及自對準製程，從而允許圖案被產生，該些圖案相較於使用單一直接光學微影製程以其他方式可獲得的圖案具有例如較小間距。舉例而言，在一個實施例中，犧牲層形成於基板上方，且使用光學微影製程來圖案化。間隔物使用自對準製程沿著經圖案化之犧牲層來形成。犧牲層接著經移除，且剩餘間隔物或心軸可接著用於使鰭片圖案化。
參看第3圖，虛設閘極堆疊30經形成以在(突出) 半導體鰭片24’之頂表面及側壁上延伸。各別製程圖示為如第19圖中繪示之製程流程200中的製程206。虛設閘極堆疊30可包括虛設閘極介電層32及虛設閘極介電層32上方的虛設閘極電極34。虛設閘極電極34可例如使用多晶矽來形成，且亦可使用其他材料。虛設閘極堆疊30中的每一者亦可包括虛設閘極電極34上方的一個(或複數個)硬式遮罩層36。硬式遮罩層36可由氮化矽、氧化矽、碳氮化矽形成或為其多層。虛設閘極堆疊30可橫跨單一一個或複數個突出半導體鰭片24’及/或STI區22。虛設閘極堆疊30亦具有垂直於突出半導體鰭片24’之縱向方向的縱向方向。
接著，閘極間隔物38形成於虛設閘極堆疊30的側壁上。各別製程亦圖示為如第19圖中所繪示之製程流程200中的製程206。根據本揭露之一些實施例，閘極間隔物38由諸如氮化矽、碳氮化矽或類似者的介電材料形成，且可具有單層結構或包括複數個介電層的多層結構。
蝕刻製程接著經執行以蝕刻突出半導體鰭片24’的並未由虛設閘極堆疊30與閘極間隔物38覆蓋的數個部分，從而導致繪示於第4圖中的結構。各別製程圖示為如第19圖中繪示之製程流程200中的製程208。凹陷可為各向異性，且因此突出半導體鰭片24’的直接下伏於虛設閘極堆疊30及閘極間隔物38的數個部分受到保護，且並不被蝕刻。根據一些實施例，凹陷半導體條帶24的頂表面可低於STI區22的頂表面22T。凹部40因此形成於STI區22之間。凹部40位於虛設閘極堆疊30之相對側上，且包括低於STI區22之頂表面的一些部分及高於STI區22之頂表面且在相鄰閘極堆疊30之間的一些部分。
接著，磊晶製程經執行以形成磊晶區42，該些磊晶區42自凹部40選擇性地生長，從而產生第5A圖中的結構。各別製程圖示為如第19圖中繪示之製程流程200中的製程210。在磊晶區42充分填充凹部40之後，磊晶區42開始水平地擴展，且可形成刻面。磊晶區42替代地被稱作源極/汲極區42，此係由於磊晶區42充當FinFET的源極/汲極區。
取決於所得FinFET為p型FinFET或是n型FinFET，p型或n型雜質可在磊晶進行之前經原位摻雜。舉例而言，當所得FinFET為p型FinFET時，可生長矽鍺硼(silicon germanium boron，SiGeB)、矽硼(silicon boron，SiB)或類似者。相反地，當所得FinFET為n型FinFET時，可生長磷化矽(silicon phosphorous，SiP)、碳磷化矽(silicon carbon phosphorous，SiCP)或類似者。根據本揭露之替代性實施例，磊晶區42包含III-V族化合物半導體，諸如GaAs、InP、GaN、InGaAs、InAlAs、GaSb、AlSb、AlAs、AlP、GaP、其組合物，或其多層。應瞭解，p型磊晶區42及n型磊晶區42可具有不同輪廓。舉例而言，p型磊晶區42可具有清楚刻面，如第5B圖中所繪示，而n型磊晶區42在橫截面圖中可具有圓形隅角。
第5B圖圖示繪示於第5A圖中之結構之橫截面圖，其中橫截面圖自第5A圖中含有線5B-5B的垂直平面獲得。根據一些實施例，在第5B圖中，突出半導體鰭片24’的位置，其並未在所圖示平面中中出現，是使用虛線來繪示，以圖示突出半導體鰭片24’與磊晶區42的相對位置。
繼續進行磊晶，自相鄰凹部生長之磊晶區42彼此合併以形成整合磊晶區42。可產生孔隙(氣隙) 43。根據本揭露之一些實例例，磊晶區42之形成在磊晶區42之頂表面仍為波狀時結束。根據本揭露之其他實例例，磊晶區42之形成在磊晶區42之頂表面變成平面時結束。
第6圖圖示結構在形成觸點蝕刻終止層(Contact Etch Stop Layer，CESL) 46及層間介電質(Inter-Layer Dielectric，ILD) 48之後的透視圖。各別製程圖示為如第19圖中繪示之製程流程200中的製程212。CESL 46可由氧化矽、氮化矽、碳氮化矽或類似者形成或包含氧化矽、氮化矽、碳氮化矽或類似者，且可使用CVD、ALD或類似者形成。ILD 48可包括使用例如FCVD、旋塗塗佈、CVD或另一沉積方法形成的介電材料。ILD 48可由含氧介電材料形成或包含含氧介電材料，該含氧介電材料可為氧化矽類材料，諸如氧化矽、硼矽酸鹽玻璃(Boro-Silicate Glass，BSG)、經硼摻雜的磷矽酸鹽玻璃(Boron-Doped Phospho-Silicate Glass，BPSG)或類似者。諸如化學機械拋光(Chemical Mechanical Polish，CMP)製程或機械研磨製程的平坦化製程可經執行以與ILD 48、虛設閘極堆疊30及閘極間隔物38的頂表面彼此齊平。
接著，虛設閘極堆疊30(包括硬式遮罩層36、虛設閘極電極34及虛設閘極介電層32)由替換閘極堆疊56替換，該些替換閘極堆疊56包括閘極電極54及閘極介電層52，如第7圖中所展示。各別製程圖示為如第19圖中繪示之製程流程200中的製程214。當形成替換閘極堆疊56時，如第6圖中繪示之虛設閘極堆疊30首先在複數個蝕刻製程中被移除，從而致使溝槽/開口形成於ILD 48的相鄰部分之間。突出半導體鰭片24’之頂表面(參照第5B圖)及側壁暴露至所得溝槽。根據一些實施例，在凹陷中，閘極間隔物38亦經凹陷。根據替代性實施例，閘極間隔物38不經凹陷。
根據本揭露之一些實施例，閘極介電層52中的每一者包括界面層(Interfacial Layer，IL)作為其下部部分，該下部部分接觸對應突出半導體鰭片24’的暴露表面。界面層可包括諸如氧化矽層的氧化物層，該氧化矽層經由突出半導體鰭片24’之熱氧化、化學氧化製程或沉積製程來形成。閘極介電層52亦可包括形成於界面層上方的高k介電層。高k介電層可包括高k介電材料，諸如氧化鉿、氧化鑭、氧化鋁、氧化鋯、氮化矽或類似者。高k介電材料的介電常數(k值)高於3.9，且可高於約7.0。高k介電層形成為保形層，且在突出半導體鰭片24’之側壁及閘極間隔物38之側壁上延伸。根據本揭露之一些實施例，高k介電層使用ALD或CVD形成。
進一步參看第7圖，閘極電極54形成於閘極介電層52上方，閘極電極54包括導電子層。子層並未分離地繪示，而是子層為彼此可區分的。子層之沉積可使用諸如ALD或CVD之保形沉積製程來執行。
堆疊導電層可包括擴散阻障層及擴散阻障層上方的一(或多個)功函數層。擴散阻障層可由氮化鈦(TiN)形成，氮化鈦可(或可能不)摻雜有矽。功函數層決定閘極的功函數，且包括至少一個層，或由不同材料形成的複數個層。功函數層之材料根據各別FinFET的導電類型來選擇。舉例而言，當FinFET為p型FinFET時，功函數層可包括TaN層、TaN層上方的TiN層，及TiN上方的TiAl層。當FinFET為n型FinFET時，功函數層可包括含鋁材料，諸如TiAl、TiAlC、TiAlN或類似者。在沉積功函數層之後，形成可為另一TiN層的阻障/頂蓋層。
用於形成替換閘極堆疊的所沉積閘極介電層及導電層形成為延伸至溝槽中的保形層，且包括ILD 48上方的一些部分。接著，金屬材料經沉積以填充閘極間隔物38之間的剩餘溝槽。舉例而言，金屬材料可由鎢或鈷形成或包含鎢或鈷。隨後，諸如CMP製程或機械研磨製程的平坦化製程經執行，使得閘極介電層、導電子層及ILD 48上方之金屬材料的額外部分被移除。因此，形成金屬閘極電極54及閘極介電層52。閘極電極54及閘極介電層52組合地被稱為替換閘極堆疊56。替換閘極堆疊56、閘極間隔物38、CESL 46及ILD 48的頂表面此時可為實質上共平面的。
第7圖亦圖示根據一些實施例的(自對準)硬式遮罩58的形成。各別製程圖示為如第19圖中繪示之製程流程200中的製程216。硬式遮罩58之形成可包括執行蝕刻製程以使替換閘極堆疊56凹陷。閘極間隔物38亦可(或可能並非)經凹陷，其中凹陷深度(若凹陷)小於替換閘極堆疊56。凹部因此形成於CESL 46的相對垂直部分之間。凹部接著填充有介電材料，繼之以諸如CMP製程或機械研磨製程的平坦化製程以移除介電材料的過量部分。介電材料之剩餘部分形成硬式遮罩58，該些硬式遮罩有時被成為自對準觸點(Self-Aligned Contact，SAC)遮罩。硬式遮罩58可由以下各者形成或包含以下各者：氮化矽、氮氧化矽或、氧碳氮化矽或類似者。取決於閘極間隔物38是否經凹陷，硬式遮罩58可能使頂表面與閘極間隔物38及ILD 48的頂表面齊平，或可具有與閘極間隔物38重疊的部分，如第7圖中所繪示。
第8A圖及第8B圖圖示結構在形成複數個層之後的橫截面圖。首先，介電層50沉積於介電層48的頂表面上。各別製程圖示為如第19圖中繪示之製程流程200中的製程218。在第8A圖及第8B圖以及後續圖中，具有後綴「A」之參考標記的圖代表這些圖繪示與第7圖中之橫截面A-A相同的橫截面，且具有後綴「B」之參考標記的圖代表這些圖繪示與第7圖中橫截面B-B相同的橫截面。介電層50可由選自與用於形成ILD 48之候選材料相同的材料來形成，且介電層50及ILD 48之材料可彼此相同或不同。
接著形成一個或複數個硬式遮罩。各別製程圖示為如第19圖中繪示之製程流程200中的製程220。根據一些實施例，硬式遮罩包括含金屬硬式遮罩152 (由例如經鎢摻雜之碳化物(tungsten doped carbide，WDC))、硬式遮罩154 (由例如氧化矽形成)及另一硬式遮罩156，該硬式遮罩156相對於硬式遮罩154具有高蝕刻選擇性值。根據一些實施例，硬式遮罩156由矽形成或包含矽。
接著形成可為三層的蝕刻遮罩158。蝕刻遮罩158可包括底部層158BL (有時亦被稱作下部層)、底部層158BL上方的中間層158ML，及中間層158ML上方的頂部層158TL(有時亦被稱作上部層)。頂部層158TL在其中具有開口60，該些開口60與磊晶區42重疊。根據一些實施例，底部層158BL由含碳材料(經由CVD)或交聯光阻劑形成，且頂部層158TL由光阻劑(經由旋轉塗佈)形成。中間層158ML可由無機含矽材料形成，該無機含矽材料可係氮化物(諸如，氮化矽)、氮氧化物(諸如，氮氧化矽)、氧化物(諸如氧化矽)或類似者。中間層158ML可經由CVD來沉積。
接著，蝕刻製程經執行以使開口60延伸至硬式遮罩156中。各別製程圖示為如第19圖中繪示之製程流程200中的製程222。蝕刻製程可終止於硬式遮罩154的頂表面上。在蝕刻製程之後，蝕刻遮罩158的剩餘部分可被移除。所得結構繪示於第9A圖及第9B圖中，其中硬式遮罩156經暴露。
在後續製程中，如第10A圖及第10B圖中所繪示，硬式遮罩156用以蝕刻下伏硬式遮罩154及152，繼之以介電層50的蝕刻以使開口60向下延伸。亦蝕刻ILD 48。各別製程圖示為如第19圖中繪示之製程流程200中的製程224。形成於ILD 48中之開口下文中被稱作源極/汲極觸點開口62。在硬式遮罩58之頂表面與閘極間隔物38之頂表面齊平的實施例中，閘極間隔物38在暴露時可終止蝕刻。根據一些實施例，蝕刻經各向異性地執行，且可經由乾式蝕刻製程執行。
根據一些實施例，第10A圖中側壁57之筆直部分的傾斜角α1及第10B中的α1’小於約15度，且可在約5度與約15度的範圍內。側壁57亦可為筆直且垂直的，其中傾斜角α1及α1’小於約5度，且可在約1度與約5度的範圍內。蝕刻氣體可包括NF 3與NH 3之混合物、HF及NH 3的混合物，或類似者。CESL 46接著經蝕刻以顯露磊晶區42。在蝕刻製程之後，硬式遮罩152、154及156的剩餘部分被移除。
第10C圖圖示第10A圖及第10B圖中所繪示的結構之透視圖，其中硬式遮罩152、154及156並未繪示。繪示於第10A圖中之橫截面圖自第10C圖中之橫截面A-A獲得，且繪示於第10B圖中之橫截面圖自第10C圖中的橫截面B-B獲得。
當磊晶區42用於形成p型FinFET時，p型雜質(摻雜劑)植入可經執行。舉例而言，可植入硼、鎵及/或銦。因此，磊晶區42之頂部部分經重度摻雜以形成重度摻雜區42’，如第11A圖及第11B圖中所繪示。n型磊晶區在p型植入中可經遮蔽。根據替代性實施例，跳過p型雜質(摻雜劑)植入製程。
第11A及第11B圖示用於修改開口60及源極/汲極觸點開口62之輪廓的回拉(pull-back)製程64。各別製程圖示為如第19圖中繪示之製程流程200中的製程226。回拉製程64使得在開口60及源極/汲極觸點開口62中後續形成特徵更容易。回拉製程64經由蝕刻製程執行，其中可執行乾式蝕刻或濕式蝕刻製程。根據一些實施例，蝕刻包括各向同性蝕刻，其中蝕刻氣體經選擇以攻擊介電層50、ILD 48，且可或可能不攻擊CESL 46。舉例而言，蝕刻氣體可包括C xF yH z、O 2、CO 2、Ar、NF 3、NH 3、HF、H 2及/或類似者。蝕刻亦可包括某各向異性效應外加各向同性效應。舉例而言，可施加低於約300瓦特的偏壓功率。
回拉製程64經控制，使得開口60及源極/汲極觸點開口62之上部部分相較於各別下部部分擴展得更多，使得開口60及源極/汲極觸點開口62之側壁57的筆直部分相較於回拉製程之前更傾斜(第10A圖及第10B圖)。舉例而言，第11A圖中的傾斜角α2及第11B中的α2’可小於約20度，且可在約5.5度與約20度的範圍內。傾斜角α2及第α2’亦可小於約5.5度，且可在約1.5度與約5.5度的範圍內。又，第11A圖中之傾斜角α2及第11B圖中的α2’大於第10A圖中之各別傾斜角α1及第10B圖中的α1’。根據一些實施例，差(α2 - α1)大於約0.5度，且可在約0.5度與約5.0度的範圍內。差(α2’ - α1’)亦可大於約5.0度，且可在約5.0度與約10.0度的範圍內。
應瞭解，傾斜角α1 (第10A圖)可等於或小於傾斜角α1’ (第10B圖)。另一方面，歸因於回拉製程64，傾斜角α2 (第11A圖)小於傾斜角α2’ (第11B圖)。差(α2’ – α2)可大於約1度，且可在約1度與約10度的範圍內。
為了使得開口60及源極/汲極觸點開口62之側壁57更傾斜，回拉製程64可經控制，例如以使得介電層50及ILD 48相較於各別較低部分在其上部部分處具有較大蝕刻速率。舉例而言，增大製程氣體的壓力可使得下部部分相較於上部部分蝕刻得較少。根據一些實施例，蝕刻腔室中之壓力可係在約0.001托與約1托的範圍內。此外，減少晶圓10之溫度可使得下部部分相較於上部部分蝕刻得較少。根據一些實施例，在回拉製程64期間，晶圓10之溫度可係在約0℃與約150℃的範圍內。應瞭解，回拉效應亦係關於諸如開口60及源極/汲極觸點開口62的側向大小及深度的其他因素，且這些因素亦可影響其他因素，諸如壓力及溫度的有效範圍。
在回拉製程64中，硬式遮罩58可經暴露，且硬式遮罩58可終止回拉。替代地，回拉可經執行，使得硬式遮罩58在暴露情況下以比介電層50及ILD 48小的蝕刻速率進行蝕刻，使得硬式遮罩58仍具有保護下伏特徵的功能，同時硬式遮罩58之隅角經修圓，且開口60及源極/汲極觸點開口62的側壁為更平滑且更筆直的。根據閘極間隔物38經暴露的替代性實施例，閘極間隔物38可充當蝕刻終止層，且可能經蝕刻或可能未經蝕刻。類似地，閘極間隔物38在經蝕刻時相較於介電層50及ILD 48以較慢蝕刻速率進行蝕刻。舉例而言，虛線38’(第11A圖)示意性地圖示經暴露之閘極間隔物38的部分。
第12A圖及第12B圖圖示隔離層66的沉積。各別製程圖示為如第19圖中繪示之製程流程200中的製程228。根據一些實施例，隔離層66可由以下各者形成或包含以下各者：氮化矽、氧化矽、氧碳氮化矽、碳氧化矽或類似者，或諸如氧化鋁、氮化鋁、氧化鉿或類似者的含金屬介電層。隔離層66之介電常數可低於約10，或低於約5。
沉積為非保形的，使得隔離層66在源極/汲極觸點開口62之底部處的厚度T2可小於在源極/汲極觸點開口62及開口60中隔離層66之上部部分的厚度。厚度T2亦可小於頂部水平厚度T1及T1’。舉例而言，T2/T1的比值可小於約2.5，且可在約1與約2.5的範圍內。厚度T1可係在約5Å與約30 Å的範圍內。此外，至少自源極/汲極觸點開口62的頂部部分至底部部分，隔離層66的厚度可逐漸減小。
沉積製程可包括ALD、電漿增強化學氣相沉積(Plasma Enhance Chemical Vapor Deposition，PECVD)、CVD或類似者。應瞭解，儘管ALD製程係保形沉積製程，但當開口60及源極/汲極觸點開口62之深寬比過高時，對於前驅體難以到達深溝槽的下部部分，且因此隔離層66在更深入至高深寬比溝槽時變得較薄。根據開口60及源極/汲極觸點開口62的深寬比並非足夠大的一些實施例，可使用其他非成形沉積方法，諸如PECVD。
根據一些實施例，當使用ALD時，晶圓溫度可係在約300℃與約450℃之間的範圍內。壓力可係在約0.1托與約100托之間的範圍內。前驅體可包括SiH 2I 2、SiH 2Cl 2、SiCl 4或類似者，或其組合。前驅體亦可包括NH 3、N 2、N 2與H 2之混合物，或類似者，或其組合。自NH 3或N 2與H 2之混合物產生電漿的功率可係在500與約700瓦特之間的範圍內。
第13A圖及第13B圖圖示隔離層66之蝕刻，使得隔離層66的水平部分經移除。各別製程圖示為如第19圖中繪示之製程流程200中的製程230。在源極/汲極觸點開口62的底部，隔離層66亦經移除以暴露磊晶區42，或經削薄，使得在磊晶區42的頂部存在隔離層66之薄的水平部分。舉例而言，隔離層66之薄的水平部分可具有小於約3 Å的厚度(若其剩餘)。蝕刻可經由各向異性蝕刻製程來執行。應瞭解，儘管隔離層66為傾斜的，但由於介電層50及ILD 48的側壁經傾斜，隔離層66在蝕刻之後的時間仍具有剩餘在介電層50及ILD 48之側壁上的部分。
植入製程可經執行從而在磊晶區42中形成預非晶化植入(pre-amorphization implantation，PAI)區42’。根據一些實施例，植入鍺。根據其他實施例，諸如矽之其他摻雜劑或諸如氖、氬、氙及氡的惰性物質經植入。植入可在隔離層66之水平部分經蝕刻之後來執行，如第13A圖及第13B圖中所繪示；或可在沉積之後且在蝕刻隔離層66之前執行。
預清洗製程可經執行以移除形成於磊晶區42之頂表面上的任何氧化物層，且製備磊晶區42用於矽化製程。在預清洗製程中，磊晶區42之頂表面上隔離層66的水平部分(若存在)被移除。介電層50及ILD 48之側壁上隔離層66的厚度可係在約8 Å與約10 Å之間的範圍內。
接著，如第14A及第14B圖中所繪示，矽化物區70形成於磊晶區42的頂表面上。各別製程圖示為如第19圖中繪示之製程流程200中的製程232。根據一些實施例，為了形成矽化物區70，金屬層(圖中未示)及金屬氮化物層例如使用保形沉積製程來沉積。根據一些實施例，金屬層包含鈦、鈷或類似者。金屬氮化物層可為氮化鈦層，且可使用ALD、CVD或類似者形成。金屬氮化物層亦可藉由使金屬層之頂部部分氮化且金屬層的底部部分不氮化形成。
接著，退火製程(其可為快速熱退火製程)經執行以使金屬層與源極/汲極區42的頂部部分反應以形成矽化物區70。ILD 48之側壁上金屬層的部分並不反應。在後續製程中，另一清洗製程可例如使用稀釋HF作為蝕刻劑來執行。介電層50及ILD 48之側壁上隔離層66的厚度可係在約5 Å與約10 Å之間的範圍內。
接著，先前形成之金屬氮化物層留下為未被移除，或先前形成之金屬氮化物層經移除或回拉，繼之以新金屬氮化物層(諸如氮化鈦層)的沉積。所得金屬氮化物層繪示為金屬氮化物層72。金屬材料74，諸如鎢、鈷或類似者接著填充至觸點開口60中。金屬材料74的形成製程可包括沉積晶種層(W、Co或類似者)及例如經由電化學電鍍(electrochemical plating，ECP)鍍敷諸如鎢、鈷或類似者的金屬。各別製程圖示為如第19圖中繪示之製程流程200中的製程234。
接著，平坦化製程經執行以移除金屬材料74及金屬氮化物層72的過量部分，從而產生源極/汲極觸點栓塞76。根據一些實施例，介電層50經移除，如第15A圖及第15B圖中所繪示。各別製程圖示為如第19圖中繪示之製程流程200中的製程236。根據替代性實施例，平坦化製程終止於介電層50之頂表面上。源極/汲極觸點栓塞76包括金屬層、金屬氮化物層72及金屬材料74的剩餘部分。因此形成FinFET 78。第15C圖圖示FinFET 78之透視圖，其中第15A圖及第15B圖圖示第15C圖中的橫截面15A-15A及15B-15B。
參看第16A圖及第16B圖，形成蝕刻終止層80及ILD 82。各別製程圖示為如第19圖中繪示之製程流程200中的製程238。蝕刻終止層80可由AlO、AlN、SiN、SiCN、SiC、SiOCN或類似者或其組合形成。形成方法可包括PECVD、ALD、CVD或類似者。接著，ILD 82形成於蝕刻終止層80上方。ILD 82之材料可選自與形成ILD 48相同的候選材料（及方法）。根據一些實施例，ILD 82使用PECVD、FCVD、旋塗塗佈或類似者來形成。
ILD 82及蝕刻終止層80接著經蝕刻以形成開口。蝕刻可使用例如反應性離子蝕刻(Reactive Ion Etch，RIE)來執行。在後續製程中，形成上部源極/汲極觸點栓塞86及閘極觸點栓塞88。各別製程圖示為如第19圖中繪示之製程流程200中的製程240。根據本揭露之一些實施例，上部源極/汲極觸點栓塞86及閘極觸點栓塞88包括阻障層及對應阻障層上方的含金屬材料。
如第16A圖中所繪示，源極/汲極觸點栓塞76逼近相鄰閘極觸點栓塞88，且可存在於其之間流動的洩漏電流。隔離層66阻斷洩漏電流，且減少洩漏電流。實驗結果已顯示，隔離層66可耐受高於6 MV/cm的擊穿電壓。當2 MV/cm之電場施加於隔離層66上時發生的洩漏電流發現為小於1E-6A/cm 2。
根據一些實施例，如第16A圖及第16B圖中所繪示，隔離層66之上部部分相較於各別下部部分較厚。此外，厚度改變可為連續的。隔離層66之底部可接觸各別矽化物區70，或可高於各別矽化物區70且可與矽化物區70隔開。
根據一些實施例，第17圖及第18圖圖示源極/汲極觸點栓塞76 (包括76A及76B)及對應隔離層66。在俯視圖中，每一隔離層66形成包圍對應源極/汲極觸點栓塞76的環。歸因於源極/汲極觸點開口62之狹長形狀(第13A圖及第13B圖)以及傾斜角α1’ (第10B圖)與α2’ (第11B圖)的差，隔離層66具有非均勻厚度。隔離層66之靠近狹長源極/汲極觸點栓塞76之末端的數個部分相較於狹長源極/汲極觸點栓塞76之中間部分處的隔離層66為較厚的。舉例而言，包圍源極/汲極觸點栓塞76A的隔離層66A具有中間厚度Tx1及末端厚度Ty1。包圍源極/汲極觸點栓塞76B的隔離層66B具有中間厚度Tx2及末端厚度Ty2。厚度Tx1及Tx2可係在約5Å與約30 Å之間的範圍內。Ty1/Tx1的比值及Ty1/Tx1的比值兩者大於1.0，且可係在1.0與約1.3之間的範圍內，且可係在1.0與約1.5之間，或係在約1.2與約1.5之間。
此外，包圍較長源極/汲極觸點栓塞的隔離層相較於包圍較短源極/汲極觸點栓塞的隔離層具有較大的Ty/Tx的比值。舉例而言，如第17圖及第18圖中所繪示，源極/汲極觸點栓塞76B的長度L2大於源極/汲極觸點栓塞76A的長度L1。因此， Ty2/Tx2的比值大於Ty1/Tx1的比值。此外，較長源極/汲極觸點栓塞(諸如76B)的俯視圖形狀相較於較短源極/汲極觸點栓塞(諸如76A)具有尖銳末端。如第17圖及第18圖中所繪示的厚度可為對應隔離層之頂部部分的厚度。
此外，如第17圖及第18圖中所繪示，隔離層90亦可形成，從而包圍閘極觸點栓塞88。對應形成製程可與隔離層66的形成相同或不同，例如包括蝕刻對應介電層。可執行(或不執行)回拉製程。此外，取決於不同形成製程，所得隔離層90可具有等於末端厚度Ty3的中間厚度Tx3，如第17圖中所繪示。替代地，如第18圖中所繪示，隔離層90可具有小於末端厚度Ty4的中間厚度Tx4。
本揭露之實施例具有一些優勢特徵。藉由形成隔離層，源極/汲極觸點栓塞及鄰近源極/汲極觸點栓塞及閘極觸點栓塞之間的洩漏被減少。此外，使得隔離層為傾斜的且隔離層之頂部部分的厚度大於下部部分的厚度，能夠改良洩漏隔離能力，此係由於頂部部分相較於下部部分更靠近鄰近金屬特徵，且遭受較大洩漏問題。
根據本揭露之一些實施例，一種方法包含：在一半導體區上形成一閘極堆疊；形成一源極/汲極區，其中閘極堆疊及源極/汲極區彼此相鄰；在源極/汲極區上方形成一觸點蝕刻終止層；在觸點蝕刻終止層上方形成一層間介電質；執行一第一蝕刻製程以蝕刻層間介電質及觸點蝕刻終止層以形成一觸點開口，其中源極/汲極區經暴露至觸點開口；在形成觸點開口之後，執行一第二蝕刻製程，其中在第二蝕刻製程之後，層間介電質之面向觸點開口的一側壁相較於第二蝕刻製程之前更傾斜；沉積一隔離層從而延伸至觸點開口中；蝕刻隔離層以移除隔離層的係在源極/汲極區上方的一部分；在源極/汲極區上形成一矽化物區；及藉由一源極/汲極觸點栓塞填充觸點開口。
在一實施例中，隔離層沉積為具有相較於上部部分較薄的下部部分。在一實施例中，第一蝕刻製程包含一各向異性蝕刻製程。在一實施例中，在觸點開口之一俯視圖中，觸點開口為狹長的，且隔離層包含在觸點開口之一末端處的一末端部分，及觸點開口之對置末端之間的一中間部分，且其中末端部分厚於中間部分。在一實施例中，第二蝕刻製程包含一各向同性蝕刻效應。在一實施例中，第二蝕刻製程包含一各向異性蝕刻效應。
在一實施例中，方法進一步包含在閘極堆疊上方形成一自對準硬式遮罩的步驟，其中在第二蝕刻製程之後，自對準硬式遮罩經暴露。在一實施例中，在第二蝕刻製程中，自對準硬式遮罩用作一蝕刻終止層之一部分。在一實施例中，方法進一步包含形成閘極間隔物的步驟，其中閘極堆疊係在閘極間隔物之間，且其中在第二蝕刻製程中，閘極間隔物中的一者經暴露。在一實施例中，在隔離層經蝕刻之後，隔離層之一薄層剩餘在源極/汲極區上方，且其中方法進一步包含執行一清洗製程以移除隔離層之薄層的步驟。
根據本揭露之一些實施例，一種結構包含：一半導體區上方的一閘極堆疊；閘極堆疊之一側上的一第一源極/汲極區；第一源極/汲極區之一部分上方的一觸點蝕刻終止層；觸點蝕刻終止層上方的一層間介電質；第一源極/汲極區上方的一第一矽化物區；第一矽化物區上方且接觸第一矽化物區的一第一源極/汲極觸點栓塞；及包圍第一源極/汲極觸點栓塞的一第一隔離層，其中第一源極/汲極觸點栓塞的一俯視圖中，第一源極/汲極觸點栓塞為狹長的，且第一隔離層包含第一源極/汲極觸點栓塞之一末端處的一末端部分；及第一源極/汲極觸點栓塞之相對末端之間的一中間部分，其中末端部分的一第一末端部分厚度大於中間部分的一第一中間部分厚度。
在一實施例中，第一末端部分厚度與第一中間部分厚度的比值係在約1.2與約1.5的一範圍內。在一實施例中，結構進一步包含與閘極堆疊重疊一硬式遮罩，其中第一隔離層接觸硬式遮罩。在一實施例中，結構進一步包含閘極堆疊之對置側上的閘極間隔物，且其中硬式遮罩與閘極間隔物重疊。在一實施例中，結構進一步包含一第二源極/汲極區；第二源極/汲極觸點區上方且電連接至第二源極/汲極區的一第二源極/汲極觸點；及包圍第二源極/汲極觸點栓塞的一第二隔離層，其中在第二源極/汲極觸點栓塞的一俯視圖中，第二源極/汲極觸點栓塞為狹長的且長於第一源極/汲極觸點栓塞，且其中第一末端部分厚度與第一中間部分厚度的一第一比值小於第二隔離層之一第二末端部分厚度與一第二中間部分厚度的一第二的比值。
根據本揭露之一些實施例，一種結構包含：一半導體區上方的一閘極堆疊；閘極堆疊之相對側上的閘極間隔物；一硬式遮罩，硬式遮罩包含閘極間隔物中之一者上方的一第一部分及在閘極間隔物之間延伸的一第二部分；閘極堆疊之一側上的一源極/汲極觸點栓塞；及一隔離層，隔離層包圍源極/汲極觸點栓塞，其中在結構的一俯視圖中，隔離層具有一非均勻厚度。在一實施例中，結構進一步包含下伏且接觸源極/汲極觸點栓塞的一矽化物區，其中隔離層與矽化物區隔開。在一實施例中，隔離層包含具有一第一厚度的一上部部分，及低於上部部分的一下部部分，其中下部部分具有小於第一厚度的一第二厚度。
前述內容概述若干實施例之特徵，使得熟習此項技術者可更佳地理解本揭露之態樣。熟習此項技術者應瞭解，其可易於使用本揭露作為用於設計或修改用於實施本文中引入之實施例之相同目的及/或達成相同優勢之其他製程及結構的基礎。熟習此項技術者亦應認識到，此類等效構造並不偏離本揭露之精神及範疇，且此類等效構造可在本文中進行各種改變、取代及替代而不偏離本揭露的精神及範疇。
10:晶圓 20:基板 22:隔離區/淺溝槽隔離(STI)區 22T:頂表面 24:半導體條帶 24’:突出半導體鰭片 30:虛設閘極堆疊 32:虛設閘極介電層 34:虛設閘極電極 36:硬式遮罩層 38:閘極間隔物 38’:虛線 40:凹部 42:磊晶區 42’:重度摻雜區/PAI區 43:孔隙(氣隙) 46:觸點蝕刻終止層(CESL) 48:層間介電質(ILD) 52:閘極介電層 54:閘極電極 56:替換閘極堆疊 57:側壁 58:硬式遮罩 60:開口 62:源極/汲極觸點開口 64:回拉製程 66:隔離層 66A:隔離層 66B:隔離層 70:矽化物區 72:金屬氮化物層 74:金屬材料 76:源極/汲極觸點栓塞 76:源極/汲極觸點栓塞 76A:源極/汲極觸點栓塞 76B:源極/汲極觸點栓塞 78:鰭片場效電晶體(FinFET) 80:蝕刻終止層 82:層間介電質(ILD) 86:上部源極/汲極觸點栓塞 88:閘極觸點栓塞 90:隔離層 152:金屬硬式遮罩 154:硬式遮罩 156:硬式遮罩 158:蝕刻遮罩 158BL:底部層 158ML:中間層 158TL:頂部層 200:製程流程 202:製程 204:製程 206:製程 208:製程 210:製程 212:製程 214:製程 216:製程 218:製程 220:製程 222:製程 224:製程 226:製程 228:製程 230:製程 232:製程 234:製程 236:製程 238:製程 240:製程 5B-5B:線 A-A:橫截面 L1:長度 L2:長度 α1:傾斜角 α1’:傾斜角 α2:傾斜角 α2’:傾斜角 T2:厚度 T1:頂部水平厚度 T1’:頂部水平厚度 Tx1:中間厚度 Tx2:中間厚度 Tx3:中間厚度 Tx4:中間厚度 Ty1:末端厚度 Ty2:末端厚度 Ty3:末端厚度 Ty4:末端厚度
本揭露之態樣在與隨附圖式一起研讀時自以下詳細描述內容來最佳地理解。應注意，根據行業中之標準慣例，各種特徵未按比例繪製。實際上，各種特徵之尺寸可為了論述清楚經任意地增大或減小。 第1圖至第4圖、第5A圖、第5B圖、第6圖、第7圖、第8A圖、第8B圖、第9A圖、第9B圖、第10A圖、第10B圖、第10C圖、第11A圖、第11B圖、第12A圖、第12B圖、第13A圖、第13B圖、第14A圖、第14B圖、第15A圖、第15B圖、第15C圖、第16A圖、第16B圖、第17圖及第18圖圖示根據一些實施例的形成鰭片場效電晶體(Fin Field-Effect Transistor，FinFET)中中間階段的橫截面圖、透視圖及俯視圖。 第19圖圖示根據一些實施例的用於形成FinFET的製程流程。
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240:製程

Claims (20)

  1. 一種方法，包含以下步驟： 在一半導體區上形成一閘極堆疊； 形成一源極/汲極區，其中該閘極堆疊及該源極/汲極區彼此相鄰； 在該源極/汲極區上方形成一觸點蝕刻終止層； 在該觸點蝕刻終止層上方形成一層間介電質； 執行一第一蝕刻製程以蝕刻該層間介電質及該觸點蝕刻終止層以形成一觸點開口，其中該源極/汲極區經暴露至該觸點開口； 在形成該觸點開口的步驟之後，執行一第二蝕刻製程，其中在該第二蝕刻製程之後，該層間介電質之面向該觸點開口的一側壁相較於該第二蝕刻製程之前更傾斜； 沉積延伸至該觸點開口中的一隔離層； 蝕刻該隔離層以移除該隔離層的係在該源極/汲極區上的一部分； 在該源極/汲極區上形成一矽化物區；及 藉由一源極/汲極觸點栓塞填充該觸點開口。
  2. 如請求項1所述之方法，其中該隔離層沉積為具有相較於上部部分較薄的下部部分。
  3. 如請求項1所述之方法，其中該第一蝕刻製程包含一各向異性蝕刻製程。
  4. 如請求項1所述之方法，其中在該觸點開口之一俯視圖中，該觸點開口為狹長的，且該隔離層包含在該觸點開口之一末端處的一末端部分，及該觸點開口之對置末端之間的一中間部分，且其中該末端部分厚於該中間部分。
  5. 如請求項4所述之方法，其中該第二蝕刻製程包含一各向同性蝕刻效應。
  6. 如請求項5所述之方法，其中該第二蝕刻製程進一步包含一各向異性蝕刻效應。
  7. 如請求項1所述之方法，進一步包含以下步驟：在該閘極堆疊上方形成一自對準硬式遮罩，其中在該第二蝕刻製程之後，該自對準硬式遮罩經暴露。
  8. 如請求項7所述之方法，其中在該第二蝕刻製程中，該自對準硬式遮罩用作一蝕刻終止層之一部分。
  9. 如請求項7所述之方法，進一步包含以下步驟：形成複數個閘極間隔物，其中該閘極堆疊係在該些閘極間隔物之間，且其中在該第二蝕刻製程中，該些閘極間隔物中的一者經暴露。
  10. 如請求項1所述之方法，其中在該第二蝕刻製程之後，該層間介電質的該側壁具有大於約5.5度的一傾角。
  11. 如請求項1所述之方法，其中在該隔離層經蝕刻之後，該隔離層之一薄層剩餘在該源極/汲極區上方，且其中該方法進一步包含以下步驟：執行一清洗製程以移除該隔離層之該薄層。
  12. 一種結構，包含： 一半導體區上方的一閘極堆疊； 該閘極堆疊之一側上的一第一源極/汲極區； 該第一源極/汲極區之一部分上方的一觸點蝕刻終止層； 該觸點蝕刻終止層上方的一層間介電質； 該第一源極/汲極區上方的一第一矽化物區； 該第一矽化物區上方且接觸該第一矽化物區的一第一源極/汲極觸點栓塞；及 包圍該第一源極/汲極觸點栓塞的一第一隔離層，其中在該第一源極/汲極觸點栓塞的一俯視圖中，該第一源極/汲極觸點栓塞為狹長的，且該第一隔離層包含： 該第一源極/汲極觸點栓塞之一末端處的一末端部分；及 該第一源極/汲極觸點栓塞之相對末端之間的一中間部分，其中該末端部分的一第一末端部分厚度大於該中間部分的一第一中間部分厚度。
  13. 如請求項12所述之結構，其中該第一末端部分厚度與該第一中間部分厚度的一比值係在約1.2與約1.5之間的一範圍內。
  14. 如請求項12所述之結構，其中該第一隔離層具有大於約5.0度的一傾斜角。
  15. 如請求項12所述之結構，進一步包含與該閘極堆疊重疊的一硬式遮罩，其中該第一隔離層接觸該硬式遮罩。
  16. 如請求項15所述之結構，進一步包含該閘極堆疊之對置側上的複數個閘極間隔物，且其中該硬式遮罩與該些閘極間隔物重疊。
  17. 如請求項12所述之結構，進一步包含： 一第二源極/汲極區； 該第二源極/汲極區上方且電連接至該第二源極/汲極區的一第二源極/汲極觸點栓塞；及 包圍該第二源極/汲極觸點栓塞的一第二隔離層，其中在該第二源極/汲極觸點栓塞的一俯視圖中，該第二源極/汲極觸點栓塞為狹長的且長於該第一源極/汲極觸點栓塞，且其中該第一末端部分厚度與該第一中間部分厚度的一第一比值小於該第二隔離層之一第二末端部分厚度與一第二中間部分厚度的一第二比值。
  18. 一種結構，包含： 一半導體區上方的一閘極堆疊； 該閘極堆疊之相對側上的複數個閘極間隔物； 一硬式遮罩，該硬式遮罩包含該些閘極間隔物中之一者上方的一第一部分及在該些閘極間隔物之間延伸的一第二部分； 該閘極堆疊之一側上的一源極/汲極觸點栓塞；及 一隔離層，該隔離層包圍該源極/汲極觸點栓塞，其中在該結構的一俯視圖中，該隔離層具有一非均勻厚度。
  19. 如請求項18所述之結構，進一步包含下伏且接觸該源極/汲極觸點栓塞的一矽化物區，其中該隔離層與該矽化物區隔開。
  20. 如請求項18所述之結構，其中該隔離層包含具有一第一厚度的一上部部分，及低於該上部部分的一下部部分，其中該下部部分具有小於該第一厚度的一第二厚度。
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