CN115763373A - 晶体管结构及其形成方法 - Google Patents

晶体管结构及其形成方法 Download PDF

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Publication number
CN115763373A
CN115763373A CN202210669320.0A CN202210669320A CN115763373A CN 115763373 A CN115763373 A CN 115763373A CN 202210669320 A CN202210669320 A CN 202210669320A CN 115763373 A CN115763373 A CN 115763373A
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China
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source
drain
over
layer
isolation layer
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CN202210669320.0A
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李资良
郑柏贤
施伯铮
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明的实施例提供了晶体管结构及其形成方法。该晶体管结构包括位于半导体区上方的栅极堆叠件、位于栅极堆叠件一侧的源极/漏极区、位于源极/漏极区的部分上方的接触蚀刻停止层、位于接触蚀刻停止层上方的层间电介质、位于源极/漏极区上方的硅化物区、位于硅化物区上方并且接触硅化物区的源极/漏极接触插塞、以及环绕源极/漏极接触插塞的隔离层。在源极/漏极接触插塞的俯视图中，源极/漏极接触插塞是细长的，隔离层包括位于所述第一源极/漏极接触插塞的端处的端部和位于所述第一源极/漏极接触插塞的相对端之间的中间部分。端部的端部厚度大于中间部分的中间部分厚度。

Description

晶体管结构及其形成方法
技术领域
本发明的实施例涉及晶体管结构及其形成方法。
背景技术
在集成电路的制造中，源极/漏极接触插塞用于连接晶体管的源极/漏极区和栅极。源极/漏极接触插塞通常连接到源极/漏极硅化物区，源极/漏极硅化物区的形成过程包括在层间电介质中形成接触开口，沉积延伸到接触开口中的金属层，然后进行退火以使金属层与源极/漏极区的硅/锗反应。然后在剩余的接触开口中形成源极/漏极接触插塞。
发明内容
根据本发明的实施例的一个方面，提供了一种形成晶体管结构的方法，包括：在半导体区上形成栅极堆叠件；形成源极/漏极区，其中，栅极堆叠件与源极/漏极区彼此相邻；在源极/漏极区上方形成接触蚀刻停止层；在接触蚀刻停止层上方形成层间电介质；执行第一蚀刻工艺以蚀刻层间电介质和接触蚀刻停止层以形成接触开口，其中，源极/漏极区暴露于接触开口；在形成接触开口之后，执行第二蚀刻工艺，其中，在第二蚀刻工艺之后，层间电介质的面向接触开口的侧壁比第二蚀刻工艺之前更倾斜；沉积延伸到接触开口中的隔离层；刻蚀隔离层以去除位于源极/漏极区上的隔离层的部分；在源极/漏极区上形成硅化物区；以及用源极/漏极接触插塞填充接触开口。
根据本发明的实施例的另一个方面，提供了一种晶体管结构，包括：栅极堆叠件，位于半导体区上方；第一源极/漏极区，位于栅极堆叠件的一侧；接触蚀刻停止层，位于第一源极/漏极区的部分上方；层间电介质，位于接触蚀刻停止层上方；第一硅化物区，位于第一源极/漏极区上方；第一源极/漏极接触插塞，位于第一硅化物区上方并且接触第一硅化物区；以及第一隔离层，环绕第一源极/漏极接触插塞，其中，在第一源极/漏极接触插塞的俯视图中，第一源极/漏极接触插塞是细长的，并且第一隔离层包括：端部部分，位于第一源极/漏极接触插塞的端部处；和中间部分，位于第一源极/漏极接触插塞的相对端部之间，其中，端部部分的第一端部部分厚度大于中间部分的第一中间部分厚度。
根据本发明的实施例的又一个方面，提供了一种晶体管结构，包括：栅极堆叠件，位于半导体区上方；栅极间隔件，位于栅极堆叠件的相对侧；硬掩模，包括位于栅极间隔件中的一个上方的第一部分以及在栅极间隔件之间延伸的第二部分；源极/漏极接触插塞，位于栅极堆叠件的一侧；以及隔离层，环绕源极/漏极接触插塞，其中，在结构的俯视图中，隔离层具有不均匀的厚度。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳理解本发明的各个方面。应该强调，根据工业中的标准实践，各个部件未按比例绘制并且仅用于说明的目的。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1-图4、图5A、图5B、图6、图7、图8A、图8B、图9A、图9B、图10A、图10B、图10C、图11A、图11B、图12A、图12B、图13A、图13B、图14A、图14B、图15A、图15B、图15C、图16A、图16B、图17和图18示出了根据一些实施例的形成鳍式场效应晶体管(FinFET)的中间阶段的截面图、透视图和俯视图。
图19示出了根据一些实施例的形成FinFET的工艺流程。
具体实施方式
以下公开内容提供了许多用于实现本发明的不同特征不同的实施例或实例。下面描述了组件和布置的具体实施例或实例以简化本发明。当然，这些仅是实例而不旨在限制。例如，在以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。此外，本发明可以在各个示例中重复参考数字和/或字母。该重复是为了简单和清楚的目的，并且其本身不指示讨论的各个实施例和/或配置之间的关系。
此外，为了便于描述，本文中可以使用诸如“在…下方”、“在…下面”、“下部”、“在…上面”、“上部”等的间隔关系术语，以描述如图中所示的一个元件或部件与另一元件或部件的关系。除了图中所示的方位外，间隔关系术语旨在包括器件在使用或操作工艺中的不同方位。装置可以以其它方式定位(旋转90度或在其它方位)，并且在本文中使用的间隔关系描述符可以同样地作相应地解释。
根据一些实施例提供了晶体管及其形成方法。形成隔离层以减少相邻源极/漏极接触插塞之间以及接触插塞和栅极接触插塞之间的泄漏。根据一些实施例，使用鳍式场效应晶体管(FinFET)的形成作为示例来解释本公开的概念。其他类型的晶体管，诸如平面晶体管，也可以采用本发明的概念。本文讨论的实施例是为了提供示例以实现或使用本公开的主题，并且本领域普通技术人员将容易理解在保持在不同实施例的预期范围内的同时可以进行的修改。在各个视图和说明性实施例中，相同的附图标记用于表示相同的元件。尽管可以将方法实施例讨论为以特定顺序执行，但是其他方法实施例可以以任何逻辑顺序执行。
图1-图4、图5A、图5B、图6、图7、图8A、图8B、图9A、图9B、图10A、图10B、图10C、图11A、图11B、图12A、图12B、图13A、图13B、图14A、图14B、图15A、图15B、图15C、图16A、图16B、图17和图18示出了根据本公开的一些实施例的形成FinFET和隔离层的中间阶段的截面图和透视图。这些图中所示的工艺也示意性地反映在图19所示的工艺流程200中。
图1示出了在晶圆10上形成的初始结构的透视图。晶圆10包括衬底20。衬底20可以是半导体衬底，其可以是硅衬底、硅锗衬底或由其他半导体材料。衬底20可以掺杂有p型杂质或n型杂质。诸如浅沟槽隔离(STI)区的隔离区22可以形成为从衬底20的顶面延伸到衬底20中。对应的工艺在图19所示的工艺流程200中被示为工艺202。相邻STI区22之间的衬底20被称为半导体带24。根据一些实施例，半导体带24的顶面和STI区22的顶面可以基本上彼此齐平。
根据本公开的一些实施例，半导体带24是原始衬底20的部分，因此半导体带24的材料与衬底20的材料相同。根据本公开的可选实施例，半导体带24是通过蚀刻STI区22之间的衬底20的部分以形成凹槽并执行外延工艺以在凹槽中再生长另一种半导体材料而形成的替换带。因此，半导体带24由不同于衬底20的半导体材料形成。根据一些实施例，半导体带24由硅锗、硅碳或III-V化合物半导体材料形成。
STI区22可以包括衬垫氧化物(未示出)，衬垫氧化物可以是通过衬底20的表面层的热氧化而形成的热氧化物。衬垫氧化物也可以是使用例如原子层沉积(ALD)、高密度等离子化学气相沉积(HDPCVD)或化学气相沉积(CVD)形成的沉积氧化硅层。STI区22还可以包括在衬垫氧化物上方的电介质材料，其中可以使用可流动化学气相沉积(FCVD)、旋涂等来形成电介质材料。
参考图2，STI区22是凹进的，使得半导体带24的顶部突出高于STI区22的其余部分的顶面22T，以形成突出的半导体鳍24'。对应的工艺在图19所示的工艺流程200中被示为工艺204。可以使用干蚀刻工艺来执行蚀刻，其中NF3和NH3被用作蚀刻气体。在蚀刻工艺期间，可以产生等离子体。也可以包括氩气。根据本公开的可选实施例，STI区22的凹进是使用湿蚀刻工艺来执行的。例如，蚀刻化学品可以包括HF。
在上述实施例中，可以通过任何合适的方法对鳍进行图案化。例如，可以使用包括双重图案化或多重图案化工艺的一个或多个光刻工艺来图案化鳍。通常，双重图案化或多重图案化工艺结合了光刻和自对准工艺，从而允许创建具有例如比使用单个直接光刻工艺可获得的节距更小的节距的图案。例如，在一个实施例中，牺牲层形成在衬底上方并使用光刻工艺来图案化。使用自对准工艺在图案化牺牲层旁边形成间隔件。然后去除牺牲层，然后可以使用剩余的间隔件或心轴来对鳍进行图案化。
参考图3，伪栅极堆叠件30形成为在(突出的)鳍24'的顶面和侧壁上延伸。对应的工艺在图19所示的工艺流程200中被示为工艺206。伪栅极堆叠件30可以包括伪栅极电介质32和伪栅极电介质32上方的伪栅电极34。例如，可以使用多晶硅形成伪栅电极34，也可以使用其他材料。每个伪栅极堆叠件30还可以包括在伪栅电极34上方的一个(或多个)硬掩模层36。硬掩模层36可以由氮化硅、氧化硅、碳氮化硅或其多层形成。伪栅极堆叠件30可以跨过单个或多个突出的鳍24'和/或STI区22。伪栅极堆叠件30还具有垂直于突出鳍24'的纵长方向的纵长方向。
接下来，在伪栅极堆叠件30的侧壁上形成栅极间隔件38。对应的工艺在图19所示的工艺流程200中被示为工艺206。根据本公开的一些实施例，栅极间隔件38由诸如氮化硅、碳氮化硅等的电介质材料形成，并且可以具有单层结构或者具有包括多个电介质层的多层结构。
然后执行蚀刻工艺以蚀刻未被伪栅极堆叠件30和栅极间隔件38覆盖的突出的鳍24'的部分，从而得到图4中所示的结构。对应的工艺在图19所示的工艺流程200中被示为工艺208。凹进可以是各向异性的，因此直接位于伪栅极堆叠件30和栅极间隔件38下方的鳍24'的部分受到保护，并且未被蚀刻。根据一些实施例，凹进的半导体带24的顶面可以低于STI区22的顶面22T。相应地，在STI区22之间形成凹槽40。凹槽40位于伪栅极堆叠件30的相对侧，并且包括低于STI区22的顶面的一些部分，以及高于STI区22的顶面且在相邻的栅极堆叠件30之间的一些部分。
接下来，执行外延工艺以形成外延区42，外延区42从凹槽40中选择性地生长，从而得到图5A中的结构。对应的工艺在图19所示的工艺流程200中被示为工艺210。在外延区42完全填充凹槽40之后，外延区42开始水平扩展，并且可以形成小平面。外延区42可以可选地称为源极/漏极区42，因为它们充当FinFET的源极/漏极区。
根据所得FinFET是p型FinFET还是n型FinFET，可以在进行外延的同时原位掺杂p型杂质或n型杂质。例如，当所得FinFET是p型FinFET时，可以生长硅锗硼(SiGeB)、硅硼(SiB)等。相反，当所得FinFET是n型FinFET时，可以生长硅磷(SiP)、硅碳磷(SiCP)等。根据本公开的可选实施例，外延区42包括III-V族化合物半导体，注入GaAs、InP、GaN、InGaAs、InAlAs、GaSb、AlSb、AlAs、AlP、GaP、它们的组合或它们的多层。可以理解，p型外延区42和n型外延区42可以具有不同的轮廓。例如，p型外延区42可以具有清晰的小平面，如图5B所示，而n型外延区42在截面图中可以具有圆角。
图5B示出了图5A所示结构的截面图，其中截面图是从图5A中包含线5B-5B的垂直平面获得的。在图5B中，根据一些实施例，使用虚线示出了不在图示平面中的突出的鳍24'的位置，以说明突出的鳍24'和外延区42的相对位置。
随着外延的进行，从相邻的凹槽生长的外延区42彼此合并以形成集成的外延区42。可能会产生空隙(气隙)43。根据本发明的一些实施例，当外延区42的顶面仍为波浪形时，完成外延区42的形成。根据本发明的其他实施例，当外延区42的顶面变得平坦时，完成外延区42的形成。
图6示出了在形成接触蚀刻停止层(CESL)46和层间电介质(ILD)48之后的结构的透视图。对应的工艺在图19所示的工艺流程200中被示为工艺212。CESL 46可以由氧化硅、氮化硅、碳氮化硅等形成或者包括氧化硅、氮化硅、碳氮化硅等，并且可以使用CVD、ALD等形成。ILD 48可以包括使用例如FCVD、旋涂、CVD或其他沉积方法形成的电介质材料。ILD 48可由含氧电介质材料形成或包含含氧电介质材料，含氧电介质材料可为基于氧化硅的材料，诸如氧化硅、磷硅玻璃(PSG)、硼硅玻璃(BSG)、硼掺杂磷硅酸盐玻璃(BPSG)等。可以执行诸如化学机械抛光(CMP)工艺或机械研磨工艺的平坦化工艺以使ILD 48、伪栅极堆叠件30和栅极间隔件38的顶面彼此齐平。
接下来，伪栅极堆叠件30(包括硬掩模层36、伪栅电极34和伪栅极电介质32)被替换栅极堆叠件56替换，替换栅极堆叠件56包括栅电极54和栅极电介质52，如图7所示。对应的工艺在图19所示的工艺流程200中被示为工艺214。当形成替换栅极堆叠件56时，首先在多个蚀刻工艺中去除如图6所示的伪栅极堆叠件30，从而得到要在ILD 48的相邻部分之间形成的沟槽/开口。突出的半导体鳍24'的顶面和侧壁暴露于所得的沟槽。根据一些实施例，在凹进中，也凹进栅极间隔件38。根据可选实施例，没有凹进栅极间隔件38。
根据本公开的一些实施例，每个栅极电介质层52包括作为其下部部分的界面层(IL)，界面层接触对应的突出鳍24'的暴露表面。IL可以包括诸如氧化硅层的氧化物层，氧化物层通过突出鳍24'的热氧化、化学氧化工艺或沉积工艺形成。栅极电介质层52还可以包括IL上方的高k电介质层。高k电介质层可以包括高k电介质材料，诸如氧化铪、氧化镧、氧化铝、氧化锆、氮化硅等。高k电介质材料的电介质常数(k值)高于3.9，并且可以高于约7.0。高k电介质层形成为共形层，并在突出鳍24'的侧壁和栅极间隔件38的侧壁上延伸。根据本公开的一些实施例，使用ALD或CVD形成高k电介质层。
进一步参考图7，栅电极54形成在栅极电介质52上方，栅电极54包括导电子层。子层未单独显示，而子层是可相互区分的。可以使用诸如ALD或CVD的共形沉积工艺来执行子层的沉积。
堆叠的导电层可以包括扩散阻挡层和在扩散阻挡层上方的一个(或多个)功函层。扩散阻挡层可由可以(或可以不)掺杂有硅的氮化钛(TiN)形成。功函层决定栅极的功函，功函层包括至少一个层或由不同材料形成的多个层。根据各个FinFET的导电类型选择功函层的材料。例如，当FinFET是p型FinFET时，功函层可以包括TaN层、在TaN层上的TiN层和在TiN层上的TiAl层。当FinFET为n型FinFET时，功函层可以包括含铝材料，诸如TiAl、TiAlC、TiAlN等。在沉积功函层之后，形成阻挡/覆盖层，阻挡/覆盖层可以是另一TiN层。
用于形成替换栅极堆叠件的沉积的栅极电介质层和导电层形成为延伸到沟槽中的共形层，并且包括ILD 48上方的一些部分。接下来，沉积金属材料以填充栅极间隔件38之间的剩余沟槽。例如，金属材料可以由钨或钴形成或者包括钨或钴。随后，进行平坦化工艺，诸如CMP工艺或机械研磨工艺，从而去除栅极电介质层、导电子层和ILD 48上方的金属材料的过量部分。结果，形成金属栅电极54和栅极电介质52。栅电极54和栅极电介质52被组合称为替换栅极堆叠件56。此时替换栅极堆叠件56、栅极间隔件38、CESL 46和ILD 48的顶面可以基本上共面。
图7还示出了根据一些实施例的(自对准的)硬掩模58的形成。对应的工艺在图19所示的工艺流程200中被示为工艺216。硬掩模58的形成可以包括执行蚀刻工艺以凹进栅极堆叠件56。栅极间隔件38也可以(或可以不)被凹进，具有比栅极堆叠件56更小的凹进深度(如果被凹进)。因此在CESL 46的相对的垂直部分之间形成凹槽。然后用电介质材料填充凹槽，随后进行平坦化工艺(诸如CMP工艺或机械研磨)，以去除电介质材料的过量部分。电介质材料的剩余部分形成硬掩模58，硬掩模58有时被称为自对准接触(SAC)掩模。硬掩模58可以由氮化硅、氧氮化硅、氧碳氮化硅等形成或者包括氮化硅、氧氮化硅、氧碳氮化硅等。根据栅极间隔件38是否被凹进，硬掩模58可以具有与栅极间隔件38和ILD 48的顶面齐平的顶面，或者可以具有与栅极间隔件38重叠的部分，如图7所示。
图8A和图8B示出了在形成多个层之后的结构的截面图。首先，将电介质层50沉积在电介质层48的顶面上。对应的工艺在图19所示的工艺流程200中被示为工艺218。在图8A和图8B以及随后的附图中，附图的参考标号带有后缀“A”表示这些附图显示的截面与图7中的截面A-A相同，并且附图的参考标号带有后缀“B”表示这些附图显示的截面与图7中的截面B-B相同。电介质层50可以由选自形成ILD 48的相同候选材料的材料形成，并且电介质层50和ILD 48的材料可以彼此相同或不同。
然后形成一个或多个硬掩模。对应的工艺在图19所示的工艺流程200中被示为工艺220。根据一些实施例，硬掩模包括含金属的硬掩模152(例如，由钨掺杂碳化物(WDC)形成)、硬掩模154(例如由氧化硅形成)和相对于硬掩模154具有高蚀刻选择性值的另一硬掩模156。根据一些实施例，硬掩模156由硅形成或者包括硅。
然后形成蚀刻掩模158，蚀刻掩模158可以是三层。蚀刻掩模158可包括底层158BL(有时也称为下层)、位于底层158BL上方的中间层158ML和位于中间层158ML上方的顶层158TL(有时也称为上层)。顶层158TL在其中具有与外延区42重叠的开口60。根据一些实施例，底层158BL由含碳材料(通过CVD)或交联光刻胶形成，顶层158TL由光刻胶(通过旋涂)形成。中间层158ML可由无机含硅材料形成，无机含硅材料可以为氮化物(诸如氮化硅)、氮氧化物(诸如氮氧化硅)、氧化物(诸如氧化硅)等。中间层158ML可以通过CVD沉积。
接下来，执行蚀刻工艺以将开口60延伸到硬掩模156中。对应的工艺在图19所示的工艺流程200中被示为工艺222。蚀刻工艺可以在硬掩模154的顶面上停止。在蚀刻工艺之后，可以去除蚀刻掩模158的剩余部分。得到的结构如图9A和图9B所示，其中暴露了硬掩模156。
在随后的工艺中，如图10A和图10B所示，使用硬掩模156蚀刻下面的硬掩模154和152，然后蚀刻电介质层50以向下延伸开口60。ILD 48也被蚀刻。对应的工艺在图19所示的工艺流程200中被示为工艺224。在ILD 48中形成的开口在下文中被称为源极/漏极接触开口62。在硬掩模58的顶面与栅极间隔件38的顶面齐平的实施例中，当暴露栅极间隔件38时可以停止蚀刻。根据一些实施例，各向异性地执行蚀刻，并且可以通过干蚀刻工艺来执行蚀刻。
根据一些实施例，图10A中的侧壁57的直线部分的倾斜角α1和图10B中的α1'小于约15度，并且可以在约5度和约15度之间的范围内。侧壁57也可以是直的并且是垂直的，倾斜角α1和α1'小于约5度，并且可以在约1度和约5度之间的范围内。蚀刻气体可以包括NF3和NH3的混合物、HF和NH3的混合物等。然后蚀刻CESL 46以露出外延区42。在蚀刻工艺之后，去除硬掩模152、154和156的剩余部分。
图10C示出了图10A和图10B中所示结构的透视图，其中未示出硬掩模152、154和156。图10A所示的截面图是从图10C的截面A-A获得的，图10B所示的截面图是从图10C的截面B-B获得的。
当外延区42用于形成p型FinFET时，可以执行p型杂质(掺杂剂)注入。例如，可以注入硼、镓和/或铟。结果，外延区42的顶部被重掺杂以形成重掺杂区42'，如图11A和图11B所示。在p型注入中可以掩蔽n型外延区。根据可选实施例，跳过p型杂质(掺杂剂)注入工艺。
图11A和图11B示出了用于修改开口60和源极/漏极接触开口62的轮廓的回拉(pull-back)工艺64。对应的工艺在如图19所示的工艺流程200中被示为工艺226。回拉工艺使得后续更容易在开口60和源极/漏极接触开口62中形成部件。回拉工艺通过蚀刻工艺来执行，其中可以执行干蚀刻或湿蚀刻工艺。根据一些实施例，蚀刻包括各向同性蚀刻，其中蚀刻气体被选择为攻击电介质层50、ILD 48，并且可以攻击CESL 46或者可以不攻击CESL46。例如，蚀刻气体可以包括CxFyHz、O2、CO2、Ar、NF3、NH3、HF、H2等。除了各向同性效应之外，蚀刻还可以包括一些各向异性效应。例如，可以施加低于约300瓦的偏置功率。
控制回拉工艺64使得开口60和62的上部部分比相应的下部部分扩展得更多，从而使开口60和62的侧壁57的直线部分比在回拉工艺之前(图10A和图10B)更倾斜。例如，图11A中的倾斜角α2和图11B中的α2'可以小于约20度，并且可以在约5.5度和约20度之间的范围内。倾斜角α2和α2'也可以小于约5.5度，并且可以在约1.5度和约5.5度之间的范围内。此外，图11A中的倾斜角α2和图11B中的α2'大于相应的图10A中的倾斜角α1和图10B中的α1'。根据一些实施例，差(α2-α1)大于约0.5度，并且可以在约0.5度和约5.0度之间的范围内。差(α2'-α1')也可以大于约5.0度，并且可以在约5.0度和约10.0度之间的范围内。
可以理解，倾斜角α1(图10A)可以等于或小于倾斜角α1'(图10B)。另一方面，由于回拉工艺，倾斜角α2(图11A)小于倾斜角α2'(图11B)。差(α2'-α2)可以大于约1度，并且可以在约1度和约10度之间的范围内。
为了使开口60和62的侧壁57更倾斜，可以控制回拉工艺64，例如以使电介质层50和ILD 48在其上部部分处具有比在其对应的下部部分处具有更大的蚀刻速率。例如，增加工艺气体的压力可以导致下部部分比上部部分被蚀刻得更少。根据一些实施例，蚀刻室中的压力可以在约0.001托和约1托之间的范围内。此外，降低晶圆10的温度可以导致下部部分比上部部分被蚀刻得更少。根据一些实施例，在回拉工艺64期间，晶圆10的温度可以在约0℃和约150℃之间的范围内。可以理解，回拉效应还与开口60和源极/漏极开口62的横向尺寸和深度等其他因素有关，并且这些因素也可能影响其他因素(诸如压力和温度等)的效应范围。
在回拉工艺64中，可以暴露硬掩模58，并且硬掩模58可以停止回拉。可选地，可以执行回拉，使得硬掩模58(如果暴露)以比电介质层50和ILD 48更小的蚀刻速率被蚀刻，使得硬掩模58仍然具有保护下面部件的功能，同时硬掩模58的角部是圆角的，并且开口60和62的侧壁更平滑并且更直。根据其中暴露栅极间隔件38的可选实施例，栅极间隔件38可以用作蚀刻顶层，并且可以被蚀刻或可以不被蚀刻。类似地，栅极间隔件38如果被蚀刻，则以比电介质层50和ILD 48更小的蚀刻速率被蚀刻。例如，虚线38'(图11A)示意性地示出了暴露的栅极间隔件38的部分。
图12A和图12B示出了隔离层66的沉积。对应的工艺在图19所示的工艺流程200中被示为工艺228。根据一些实施例，隔离层66可以由氮化硅、氧化硅、氮氧化硅、氧碳氮化硅、碳氧化硅等形成或者包括氮化硅、氧化硅、氮氧化硅、氧碳氮化硅、碳氧化硅等，或者隔离层66可以可以是含金属电介质层，诸如氧化铝、氮化铝、氧化铪等。隔离层66的电介质常数可以低于约10，或低于约5。
沉积是非共形的，使得隔离层66在开口62的底部处的厚度T2可以小于隔离层66在开口62和60的上部部分的厚度。厚度T2也可以是小于顶部水平厚度T1和T1'。例如，比率T2/T1可以小于约2.5，并且可以在约1和约2.5之间的范围内。厚度T1可以在约
Figure BDA0003692667300000111
和约
Figure BDA0003692667300000112
之间的范围内。此外，至少从开口62的顶部部分到底部部分，隔离层66的厚度可以逐渐减小。
沉积工艺可以包括ALD、等离子体增强化学气相沉积(PECVD)、CVD等。可以理解的是，虽然ALD工艺是共形沉积工艺，但是当开口62和60的深宽比过高时，前体很难到达深沟槽的下部部分，并且因此当更深的进入到高深宽比沟槽中时，隔离层66变得更薄。根据其中开口62和源极/漏极接触开口60的深宽比不足够大的一些实施例，可以使用诸如PECVD的其他非整齐(non-formal)沉积方法。
根据一些实施例，当使用ALD时，晶圆温度可以在约300℃和约450℃之间的范围内。压力可以在约0.1托和约100托之间的范围内。前体可以包括SiH2I2、SiH2Cl2、SiCl4等或它们的组合。前体还可以包括NH3，N2，N2和H2的混合物等或它们的组合。从NH3或N2和H2的混合物产生的等离子体的功率可以在约500瓦和约700瓦之间的范围内。
图13A和图13B示出了隔离层66的蚀刻，从而去除了隔离层66的水平部分。对应的工艺在图19所示的工艺流程200中被示为工艺230。在源极/漏极接触开口62的底部处，隔离层66也被去除以暴露外延区42，或者隔离层66被减薄使得有隔离层66的薄的水平部分在外延区42顶部上。例如，隔离层66的薄的水平部分可以具有小于约
Figure BDA0003692667300000121
的厚度(如果保留它们)。蚀刻可以通过各向异性蚀刻工艺来执行。可以理解，尽管由于电介质层50和ILD 48的侧壁是倾斜的使得隔离层66是倾斜的，但是在蚀刻之后的时间，隔离层66仍然有部分保留在电介质层50和ILD 48的侧壁上。
可以执行注入工艺以在外延区42中形成PAI区42'。根据一些实施例，注入锗。根据其他实施例，注入其他掺杂剂，诸如硅或者诸如氖、氩、氙和氡的惰性物质。可以在隔离层66的水平部分被蚀刻之后执行注入，如图13A和图13B所示，或者可以在沉积隔离层66之后和蚀刻隔离层66之前执行注入。
可以执行预清洁工艺以去除形成在外延区42的顶面上的任何氧化物层，并准备外延区42以进行硅化工艺。在预清洁工艺中，去除外延区42顶面上的隔离层66的水平部分(如果存在)。电介质层50和ILD 48的侧壁上的隔离层66的厚度可以在约
Figure BDA0003692667300000122
和约
Figure BDA0003692667300000123
之间的范围内。
接下来，如图14A和图14B所示，在外延区42的顶面上形成硅化物区70。对应的工艺在图19所示的工艺流程200中被示为工艺232。根据一些在实施例中，为了形成硅化物区70，例如使用共形沉积工艺沉积金属层(未示出)和金属氮化物层。根据一些实施例，金属层包括钛、钴等。金属氮化物层可以是氮化钛层，并且可以使用ALD、CVD等形成。金属氮化物层也可以通过对金属层的顶部进行氮化来形成，并且留下金属层的底部部分不被氮化。
接下来，执行退火工艺(可以是快速热退火工艺)以使金属层与源极/漏极区42的顶部反应，以形成硅化物区70。在ILD 48的侧壁上的金属层的部分的没有反应。在随后的工艺中，可以执行另外的清洁工艺，例如，使用稀释的HF作为蚀刻剂。电介质层50和ILD 48的侧壁上的隔离层66的厚度可以在约
Figure BDA0003692667300000131
和约
Figure BDA0003692667300000132
之间的范围内。
接下来，或者将先前形成的金属氮化物层保留为未被去除，或者将先前形成的金属氮化物层去除或回拉，然后沉积新的金属氮化物层(例如氮化钛层)。所得的金属氮化物层被示为金属氮化物层72。然后将诸如钨、钴等的金属材料74填充到接触开口60中。金属材料74的形成工艺可以包括沉积晶种层(W、Co等)，并且例如通过电化学镀(ECP)镀覆诸如钨、钴等的金属。对应的工艺在如图19所示的工艺流程200中被示为工艺234。
接下来，执行平坦化工艺以去除金属材料74和金属氮化物层72的过量部分，从而得到源极/漏极接触插塞76。根据一些实施例，去除电介质层50，如图15A和图15B所示。对应的工艺在图19所示的工艺流程200中被示为工艺236。根据可选实施例，平坦化工艺在电介质层50的顶面上停止。源极/漏极接触插塞76包括金属层、金属氮化物层72和金属材料74的剩余部分。因此形成FinFET 78。图15C示出了FinFET 78的透视图，其中图15A和图15B示出了图15C中的截面A-A和B-B。
参考图16A和图16B，形成蚀刻停止层80和ILD 82。对应的工艺在图19所示的工艺流程200中被示为工艺238。蚀刻停止层80可以由AlO、AlN、SiN、SiCN、SiC、SiOCN等或其组合形成。形成方法可以包括PECVD、ALD、CVD等。接下来，在蚀刻停止层80上方形成ILD 82。ILD82的材料可以是选自形成ILD 48的相同候选材料(和方法)。根据一些实施例，使用PECVD、FCVD、旋涂等形成ILD 82。
然后蚀刻ILD 82和蚀刻停止层80以形成开口。可以使用例如反应离子蚀刻(RIE)来执行蚀刻。在随后的工艺中，形成上源极/漏极接触插塞86和栅极接触插塞88。对应的工艺在图19所示的工艺流程200中被示为工艺240。根据本公开的一些实施例，源极/漏极接触插塞86和栅极接触插塞88包括阻挡层和相应的阻挡层上方的含金属材料。
如图16A所示，源极/漏极接触插塞76靠近相邻的栅极接触插塞88，并且在它们之间可能存在泄漏电流流动。隔离层66阻断了泄漏路径，并减少了泄漏电流。实验结果表明隔离层66可以承受高于6MV/cm的击穿电压。发现当在隔离层66上施加2MV/cm的电场时发生的泄漏电流小于1E-6A/cm2。
根据一些实施例，如图16A和图16B所示，隔离层66的上部部分比相应的下部部分厚。此外，厚度的变化可以是连续的。隔离层66的底部可以接触对应的硅化物区70，或者可以高于对应的硅化物区70，并且可以与对应的硅化物区70间隔开。
图17和图18示出了根据一些实施例的源极/漏极接触插塞76(包括76A和76B)和相应的隔离层66的俯视图。在俯视图中，每个隔离层66形成环绕相应的源极/漏极接触插塞76的环。由于开口62的细长形状(图13A和图13B)以及倾斜角α1'(图10B)和α2'的差(图11B)，隔离层66具有不均匀的厚度。靠近细长源极/漏极接触插塞76的端部的隔离层66的部分比在细长的源极/漏极接触插塞76的中间部分处的隔离层66更厚。例如，围绕源极/漏极接触插塞76A的隔离层66A具有中间厚度Tx1和端部厚度Ty1。围绕源极/漏极接触插塞76B的隔离层66B具有中间厚度Tx2和端部厚度Ty2。厚度Tx1和Tx2可以在约
Figure BDA0003692667300000141
和约
Figure BDA0003692667300000142
之间的范围内。比率Ty1/Tx1和比率Ty1/Tx1均大于1.0，并且可以在1.0和约1.3之间的范围内，并且可以在1.0和约1.5之间的范围内，或者在约1.2和约1.5之间的范围内。
此外，围绕较长的源极/漏极接触插塞的隔离层具有比较较短的源极/漏极接触插塞更大的Ty/Tx值。例如，如图17和图18所示，源极/漏极接触插塞76B的长度L2大于源极/漏极接触插塞76A的长度L1。因此，比率Ty2/Tx2大于比率Ty1/Tx1。此外，较长的源极/漏极接触插塞(例如76B)的俯视图形状比较短的源极/漏极接触插塞(例如76A)具有更尖锐的端部。如图17和图18所示的厚度可以是相应隔离层的顶部部分的厚度。
此外，如图17和图18所示，隔离层90也可以形成在栅极接触插塞88周围。相应的形成工艺可以与隔离层66的形成相同或不同，例如，包括蚀刻对应的电介质层。可以执行(或不执行)回拉工艺。结果，根据不同的形成工艺，得到的隔离层90可以具有等于端部厚度Ty3的中间厚度Tx3，如图17所示。可选地，如图18所示，隔离层90可以具有小于端部厚度Ty4的中间厚度Tx4。
本公开的实施例具有一些有利特征。通过形成隔离层，减少了源极/漏极接触插塞与附近的源极/漏极接触插塞和栅极接触插塞之间的泄漏。此外，使隔离层倾斜，并且由于顶部部分更靠近附近的金属部件并且比下部部分遭受了更大于的泄漏问题，所以隔离层顶部部分的厚度大于下部部分的厚度提高了泄漏隔离能力。
根据本公开的一些实施例，一种形成晶体管结构的方法包括：在半导体区上形成栅极堆叠件；形成源极/漏极区，其中，栅极堆叠件与源极/漏极区彼此相邻；在源极/漏极区上方形成接触蚀刻停止层；在接触蚀刻停止层上方形成层间电介质；进行第一蚀刻工艺以蚀刻层间电介质和接触蚀刻停止层以形成接触开口，其中，源极/漏极区暴露于接触开口；在形成接触开口之后，进行第二蚀刻工艺，其中，在第二蚀刻工艺之后，层间电介质的面向接触开口的侧壁比第二蚀刻工艺之前更倾斜；沉积延伸到接触开口中的隔离层；刻蚀隔离层以去除源极/漏极区上的隔离层的部分；在源极/漏极区上形成硅化物区；以及用源极/漏极接触插塞填充接触开口。
在一个实施例中，隔离层被沉积为具有比上部部分更薄的下部部分。在一个实施例中，第一蚀刻工艺包括各向异性蚀刻工艺。在一个实施例中，在接触开口的俯视图中，在接触开口的俯视图中，接触开口是细长的，并且隔离层包括位于接触开口的端部处的端部部分以及位于接触开口的相对端部之间的中间部分，并且其中，端部部分比中间部分更厚。在一个实施例中，第二蚀刻工艺包括各向同性蚀刻效应。在一个实施例中，第二蚀刻工艺还包括各向异性蚀刻效应。
在一个实施例中，该方法还包括在栅极堆叠件上方形成自对准硬掩模，其中，在第二蚀刻工艺之后，暴露自对准硬掩模。在一个实施例中，在第二蚀刻工艺中，自对准硬掩模用作蚀刻停止层的部分。在一个实施例中，该方法还包括形成栅极间隔件，其中，栅极堆叠件位于栅极间隔件之间，并且其中，在第二蚀刻工艺中，暴露栅极间隔件中的一个。在一个实施例中，在第二蚀刻工艺之后，层间电介质的侧壁具有大于5.5度的倾斜角。在一个实施例中，在蚀刻隔离层之后，在源极/漏极区上方留下隔离层的薄层，并且其中，方法还包括，执行清洁工艺以去除隔离层的薄层。
根据本公开的一些实施例，一种结构包括：栅极堆叠件，位于半导体区上方；第一源极/漏极区，位于栅极堆叠件的一侧；接触蚀刻停止层，位于第一源极/漏极区的部分上方；层间电介质，位于接触蚀刻停止层上方；第一硅化物区，位于第一源极/漏极区上方；第一源极/漏极接触插塞，位于第一硅化物区上方并且接触第一硅化物区；以及第一隔离层，环绕第一源极/漏极接触插塞，其中，在第一源极/漏极接触插塞的俯视图中，第一源极/漏极接触插塞是细长的，并且第一隔离层包括：端部部分，位于第一源极/漏极接触插塞的端部处；和中间部分，位于第一源极/漏极接触插塞的相对端部之间，其中，端部部分的第一端部部分厚度大于中间部分的第一中间部分厚度。
在一个实施例中，第一端部部分厚度与第一中间部分厚度的比率在1.2和1.5之间的范围内。在一个实施例中，第一隔离层具有大于5.0度的倾斜角。在一个实施例中，该结构还包括与栅极堆叠件重叠的硬掩模，其中，第一隔离层接触硬掩模。在一个实施例中，还包括在栅极堆叠件的相对侧的栅极间隔件，并且其中，硬掩模与栅极间隔件重叠。在一个实施例中，该结构还包括：第二源极/漏极区；第二源极/漏极接触插塞，位于第二源极/漏极区上方并且电连接到第二源极/漏极区；和第二隔离层，环绕第二源极/漏极接触插塞，其中，在第二源极/漏极接触插塞的俯视图中，第二源极/漏极接触插塞是细长的并且比第一源极/漏极接触插塞更长，并且其中，第一端部部分厚度与第一中间部分厚度的第一比率小于第二隔离层的第二端部部分厚度与第二中间部分厚度的第二比率。
根据本公开的一些实施例，一种结构包括：栅极堆叠件，位于半导体区上方；栅极间隔件，位于栅极堆叠件的相对侧；硬掩模，包括位于栅极间隔件中的一个上方的第一部分以及在栅极间隔件之间延伸的第二部分；源极/漏极接触插塞，位于栅极堆叠件的一侧；以及隔离层，环绕源极/漏极接触插塞，其中，在结构的俯视图中，隔离层具有不均匀的厚度。在一个实施例中，该结构还包括位于源极/漏极接触插塞下方并且接触源极/漏极接触插塞的硅化物区，其中，隔离层与硅化物区间隔开。在一个实施例中，隔离层包括具有第一厚度的上部部分和低于上部部分的下部部分，其中，下部部分具有小于第一厚度的第二厚度。
上述概述了几个实施例的特征，以便本领域技术人员可以更好地理解本公开的各个方面。本领域技术人员应当理解，他们可以容易地使用本公开作为设计或修改用于实现本文所介绍的实施例的相同目的和/或实现其相同优点的其它过程和结构的基础。本领域技术人员还应当认识到，此类等效结构不背离本发明的精神和范围，并且它们可以在不背离本发明的精神和范围的情况下在本发明中进行各种改变、替代以及改变。

Claims (10)

1.一种形成晶体管结构的方法，包括：
在半导体区上形成栅极堆叠件；
形成源极/漏极区，其中，所述栅极堆叠件与所述源极/漏极区彼此相邻；
在所述源极/漏极区上方形成接触蚀刻停止层；
在所述接触蚀刻停止层上方形成层间电介质；
执行第一蚀刻工艺以蚀刻所述层间电介质和所述接触蚀刻停止层以形成接触开口，其中，所述源极/漏极区暴露于所述接触开口；
在形成所述接触开口之后，执行第二蚀刻工艺，其中，在所述第二蚀刻工艺之后，所述层间电介质的面向所述接触开口的侧壁比所述第二蚀刻工艺之前更倾斜；
沉积延伸到所述接触开口中的隔离层；
刻蚀所述隔离层以去除位于所述源极/漏极区上的所述隔离层的部分；
在所述源极/漏极区上形成硅化物区；以及
用源极/漏极接触插塞填充所述接触开口。
2.根据权利要求1所述的方法，其中，所述隔离层被沉积为具有比上部部分更薄的下部部分。
3.根据权利要求1所述的方法，其中，所述第一蚀刻工艺包括各向异性蚀刻工艺。
4.根据权利要求1所述的方法，其中，在所述接触开口的俯视图中，所述接触开口是细长的，并且所述隔离层包括位于所述接触开口的端部处的端部部分以及位于所述接触开口的相对端部之间的中间部分，并且其中，所述端部部分比所述中间部分更厚。
5.根据权利要求4所述的方法，其中，所述第二蚀刻工艺包括各向同性蚀刻效应。
6.根据权利要求5所述的方法，其中，所述第二蚀刻工艺还包括各向异性蚀刻效应。
7.根据权利要求1所述的方法，还包括在所述栅极堆叠件上方形成自对准硬掩模，其中，在所述第二蚀刻工艺之后，暴露所述自对准硬掩模。
8.根据权利要求7所述的方法，其中，在所述第二蚀刻工艺中，所述自对准硬掩模用作蚀刻停止层的部分。
9.一种晶体管结构，包括：
栅极堆叠件，位于半导体区上方；
第一源极/漏极区，位于所述栅极堆叠件的一侧；
接触蚀刻停止层，位于所述第一源极/漏极区的部分上方；
层间电介质，位于所述接触蚀刻停止层上方；
第一硅化物区，位于所述第一源极/漏极区上方；
第一源极/漏极接触插塞，位于所述第一硅化物区上方并且接触所述第一硅化物区；以及
第一隔离层，环绕所述第一源极/漏极接触插塞，其中，在所述第一源极/漏极接触插塞的俯视图中，所述第一源极/漏极接触插塞是细长的，并且所述第一隔离层包括：
端部部分，位于所述第一源极/漏极接触插塞的端部处；和
中间部分，位于所述第一源极/漏极接触插塞的相对端部之间，其中，所述端部部分的第一端部部分厚度大于所述中间部分的第一中间部分厚度。
10.一种晶体管结构，包括：
栅极堆叠件，位于半导体区上方；
栅极间隔件，位于所述栅极堆叠件的相对侧；
硬掩模，包括位于所述栅极间隔件中的一个上方的第一部分以及在所述栅极间隔件之间延伸的第二部分；
源极/漏极接触插塞，位于所述栅极堆叠件的一侧；以及
隔离层，环绕所述源极/漏极接触插塞，其中，在所述结构的俯视图中，所述隔离层具有不均匀的厚度。
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