TWI713122B - 半導體裝置的形成方法 - Google Patents

半導體裝置的形成方法 Download PDF

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TWI713122B
TWI713122B TW108136235A TW108136235A TWI713122B TW I713122 B TWI713122 B TW I713122B TW 108136235 A TW108136235 A TW 108136235A TW 108136235 A TW108136235 A TW 108136235A TW I713122 B TWI713122 B TW I713122B
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Taiwan
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layer
trench
dielectric
gate stack
forming
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TW108136235A
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TW202036730A (zh
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張書維
蔡雅怡
陳嘉仁
魏安祺
古淑瑗
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台灣積體電路製造股份有限公司
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Abstract

半導體裝置的形成方法包含蝕刻閘極堆疊物以形成延伸至閘極堆疊物中的溝槽，在閘極堆疊物的側壁上形成介電層，側壁暴露於溝槽，並蝕刻介電層以移除在溝槽的底部的介電層的第一部分。在蝕刻介電層之後，保留在閘極堆疊物的側壁上的介電層的第二部分。在移除介電層的第一部分之後，移除介電層的第二部分以露出閘極堆疊物的側壁。以介電區填充溝槽，介電區接觸閘極堆疊物的側壁。

Description

半導體裝置的形成方法
本發明實施例係有關於半導體技術，且特別是有關於半導體裝置的形成方法。
在積體電路(integrated circuit，IC)材料和設計上的技術進步產生了數代積體電路，每一代都比前一代具有更小且更複雜的電路。在積體電路的發展史中，功能密度(即每一晶片區互連的裝置數目)增加，同時幾何尺寸縮小。此元件尺寸微縮化的製程一般來說具有增加生產效率與降低相關費用的益處。
元件尺寸微縮化也增加了加工和製造積體電路的複雜性，且為了實現這些進步，需要在積體電路的加工和製造中進行相似的發展。舉例來說，已引入鰭式場效電晶體(Fin Field-Effect Transistors，FinFETs)來取代平面電晶體，發展鰭式場效電晶體的結構及鰭式場效電晶體的製造方法。
在一些實施例中，提供半導體裝置的形成方法，此方法包含蝕刻閘極堆疊物以形成延伸至閘極堆疊物中的溝槽；在閘極堆疊物的側壁上形成介電層，側壁暴露於溝槽；蝕刻介電層以移除在溝槽的底部的介電層的第一部分，其中在蝕刻介電層之後，保留在閘極堆疊物的側壁上的介電層的第二部分；在移除介電層的第一部分之後，移除介電層的第二部分以露出閘極堆疊物的側壁；以及以介電材料填充溝槽以形成介電區，其中介電區接觸閘極堆疊物的側壁。
在一些其他實施例中，提供半導體裝置的形成方法，此方法包含在半導體鰭上形成虛設閘極堆疊物；形成接觸蝕刻停止層；在接觸蝕刻停止層上方形成層間介電質，其中虛設閘極堆疊物在層間介電質和接觸蝕刻停止層中；以取代閘極堆疊物取代虛設閘極堆疊物；蝕刻取代閘極堆疊物以形成穿過取代閘極堆疊物的溝槽；在取代閘極堆疊物的側壁上沉積氧化層，其中側壁暴露於溝槽；進一步蝕刻取代閘極堆疊物，其中氧化層保護取代閘極堆疊物的側壁免於被進一步蝕刻；從溝槽移除氧化層；在溝槽中沉積介電材料；以及將介電材料平坦化，以在溝槽中留下介電區。
在另外一些實施例中，提供半導體裝置的形成方法，此方法包含蝕刻導電區，以形成溝槽；在溝槽的側壁上沉積氧化矽層；將氧化矽層與HF和氨反應，以形成固體層；將固體層加熱以將固體層昇華，使得導電區的側壁暴露於溝槽；以及在溝槽中填充介電區。
要瞭解的是以下的揭露內容提供許多不同的實施例或範例，以實施提供之主體的不同部件。以下敘述各個構件及其排列方式的特定範例，以求簡化揭露內容的說明。當然，這些僅為範例並非用以限定本發明。例如，以下的揭露內容敘述了將一第一部件形成於一第二部件之上或上方，即表示其包含了所形成的上述第一部件與上述第二部件是直接接觸的實施例，亦包含了尚可將附加的部件形成於上述第一部件與上述第二部件之間，而使上述第一部件與上述第二部件可能未直接接觸的實施例。此外，揭露內容中不同範例可能使用重複的參考符號及/或用字。這些重複符號或用字係為了簡化與清晰的目的，並非用以限定各個實施例及/或所述外觀結構之間的關係。
再者，為了方便描述圖式中一元件或部件與另一(複數)元件或(複數)部件的關係，可使用空間相關用語，例如“在...之下”、“下方”、“下部”、“上方”、“上部”及類似的用語。除了圖式所繪示的方位之外，空間相關用語也涵蓋裝置在使用或操作中的不同方位。所述裝置也可被另外定位(例如，旋轉90度或者位於其他方位)，並對應地解讀所使用的空間相關用語的描述。
依據一些實施例提供採用切割金屬製程形成的鰭式場效電晶體(FinFET)及其形成方法。依據一些實施例顯示形成電晶體的中間階段。討論一些實施例的一些變化。在各種視圖和顯示的實施例中，使用相同的參考符號標記相同的元件。依據一些實施例，在形成介電隔離區之前，移除形成於切割金屬製程中的氧化層。
第1-5、6A、6B、7A、7B、8A、8B、9、10A、10B、10C、11A、11B、11C、12A、12B、12C、13-18、19A、19B、19C、20A、20B、20C和21圖顯示依據一些實施例之形成鰭式場效電晶體的中間階段的剖面示意圖、上視圖、和透視圖。這些製程也示意性地反映於第25圖中的製程流程200。
第1圖顯示初始結構的透視圖。初始結構包含晶圓10，晶圓10更包含基底20。基底20可為半導體基底，半導體基底可為矽基底、矽鍺基底或由其他半導體材料形成的基底。基底20可摻雜p型雜質或n型雜質。隔離區22(例如淺溝槽隔離(Shallow Trench Isolation，STI)區，因此有時也被稱為淺溝槽隔離區)可從基底20的頂表面延伸至基底20中形成。相鄰隔離區22之間的基底20的部分被稱為半導體條帶24。依據一些實施例，半導體條帶24的頂表面可與隔離區22的頂表面大致彼此齊平。依據本發明一些實施例，半導體條帶24為原始基底20的一部分，且半導體條帶24的材料與基底20的材料相同。依據本發明其他實施例，透過蝕刻基底20在隔離區22之間的部分以形成凹口，並進行磊晶以在凹口中再成長另一半導體材料，以形成半導體條帶24。因此，半導體條帶24的材料不同於基底20的材料。依據一些實施例，半導體條帶24由矽鍺、矽碳或第III-V族半導體材料形成。
隔離區22可包含襯墊氧化物(未顯示)。襯墊氧化物可由熱氧化物形成，熱氧化物透過將基底20的表面層的熱氧化形成。襯墊氧化物也可為沉積的氧化矽層，舉例來說，氧化矽層透過使用原子層沉積(Atomic Layer Deposition，ALD)、高密度電漿化學氣相沉積(High-Density Plasma Chemical Vapor Deposition，HDPCVD)或化學氣相沉積(Chemical Vapor Deposition，CVD)形成。隔離區22也可包含在襯墊氧化物上方的介電材料，其中介電材料可透過流動式化學氣相沉積(Flowable Chemical Vapor Deposition，FCVD)、旋塗或類似方法形成。
請參照第2圖，將隔離區22凹陷，使得半導體條帶24的頂部突出高於隔離區22的剩下部分的頂表面22A，以形成突出鰭24’。對應的製程顯示於第25圖所示的製程流程200中的製程202。可透過使用乾蝕刻製程進行凹陷，其中使用HF 3和NH 3作為蝕刻氣體。依據本發明其他實施例，可透過使用濕蝕刻製程進行將隔離區22凹陷的步驟。舉例來說，蝕刻化學品可包含HF溶液。
在上述顯示的實施例中，可透過任何合適的方法將鰭圖案化。舉例來說，鰭可透過使用一個或多個光微影製程(包含雙重圖案化或多重圖案化製程)來圖案化。一般來說，雙重圖案化或多重圖案化製程結合了光微影和自對準製程，以創造具有較小間距的圖案，舉例來說，此圖案具有比使用單一直接光微影製程可獲得的間距更小的圖案。舉例來說，在一實施例中，犧牲層形成於基底上方並透過使用光微影製程圖案化。間隔物透過使用自對準製程形成於圖案化犧牲層旁邊。接著，移除犧牲層，且可接著使用剩下的間隔物或心軸(mandrel)將鰭圖案化。
請參照第3圖，在突出鰭24’的頂表面和側壁上形成虛設閘極堆疊物30。對應的製程顯示於第25圖所示的製程流程200中的製程204。虛設閘極堆疊物30可包含虛設閘極介電質32和在虛設閘極介電質32上方的虛設閘極電極34。舉例來說，虛設閘極電極34可透過使用多晶矽形成，且也可使用其他材料。每個虛設閘極堆疊物30可包含在虛設閘極電極34上方的一個(或複數個)硬遮罩層36。硬遮罩層36可由氮化矽、氧化矽、氮碳化矽或前述之多層形成。虛設閘極堆疊物30可橫跨單一個或複數個突出鰭24’及/或隔離區22。虛設閘極堆疊物30也可具有垂直於突出鰭24’的長度方向的長度方向。
接著，閘極間隙壁38形成於虛設閘極堆疊物30的側壁上。依據本發明的一些實施例，閘極間隙壁38由介電材料形成，例如氮化矽、氧化矽、氮碳化矽、氮氧化矽、氮碳氧化矽或類似物，且可具有單層結構或包含複數個介電層的多層結構。
依據本發明一些實施例，進行蝕刻步驟(以下稱為鰭凹陷)以蝕刻突出鰭24’未被虛設閘極堆疊物30和閘極間隙壁38覆蓋的部分，以得到第4圖的結構。此凹陷可為非等向性，因此保護突出鰭24’在虛設閘極堆疊30和閘極間隙壁38正下方的部分不被蝕刻。依據一些實施例，凹陷的半導體條帶24的頂表面可低於隔離區22的頂表面22A。因此，凹口40形成於突出鰭24’中，並延伸於隔離區22之間。凹口40位於虛設閘極堆疊30物的兩側上。
接著，透過在凹口40中選擇性地成長半導體材料來形成磊晶區(源極/汲極區)42，以得到第5圖的結構。對應的製程顯示於第25圖所示的製程流程200中的製程206。依據一些實施例，磊晶區42包含矽鍺、矽或矽碳。依據最終的鰭式場效電晶體為p型鰭式場效電晶體或n型鰭式場效電晶體，隨著磊晶的進行，可原位摻雜p型雜質或n型雜質。舉例來說，當最終的鰭式場效電晶體為p型鰭式場效電晶體，可成長矽硼(SiB)、矽鍺硼(SiGeB)、GeB或類似物。相反地，當最終的鰭式場效電晶體為n型鰭式場效電晶體，可成長矽磷(SiP)、矽碳磷(SiCP)、矽或類似物。依據本發明其他實施例，磊晶區42可由第III-V族化合物半導體形成，例如GaAs、InP、GaN、InGaAs、InAlAs、GaSb、AlSb、AlAs、AlP、GaP、前述之組合或前述之多層。在磊晶區42完全填充凹口40之後，磊晶區42開始水平地擴展，且可形成刻面(facets)。相鄰的磊晶區42可彼此合併。
在磊晶步驟之後，磊晶區42可進一步植入p型雜質或n型雜質，以形成源極/汲極區(因此磊晶區42也可被稱為源極/汲極區)。依據本發明其他實施例，當磊晶區42在磊晶期間原位摻雜p型雜質或n型雜質，省略佈植步驟。磊晶區42包含形成於隔離區22中的下部和形成於隔離區22頂表面上方的上部。
第6A圖顯示形成接觸蝕刻停止層(Contact Etch Stop Layer，CESL)46和層間介電質(Inter-Layer Dielectric，ILD)48的結構之後的透視圖。對應的製程顯示於第25圖所示的製程流程200中的製程208。接觸蝕刻停止層46可由氧化矽、氮化矽、氮碳化矽或類似物。接觸蝕刻停止層46可透過使用順應性沉積方法形成，舉例來說，例如原子層沉積或化學氣相沉積。層間介電質48可包含介電材料，舉例來說，介電材料透過使用流動式化學氣相沉積、旋塗、化學氣相沉積或其他沉積方法形成。層間介電質48也可由含氧介電材料形成，其可為氧化矽基介電質，例如四乙氧基矽烷(Tetra Ethyl Ortho Silicate，TEOS)氧化物、電漿輔助化學氣相沉積(Plasma-Enhanced CVD，PECVD)氧化物(包含SiO 2)、磷矽酸鹽玻璃(Phospho-Silicate Glass，PSG)、硼矽酸鹽玻璃(Boro-Silicate Glass，BSG)、硼摻雜磷矽酸鹽玻璃(Boron-Doped Phospho-Silicate Glass，BPSG)或類似物。可進行化學機械研磨(Chemical Mechanical Polish，CMP)製程或機械研磨製程使層間介電質48、虛設閘極堆疊物30和閘極間隙壁38的頂表面彼此齊平。
第6A圖顯示的結構的剖面示意圖顯示於第6B圖。此剖面示意圖由第6A圖中包含線6B-6B的垂直平面得到。如第6B圖所示，顯示其中一個虛設閘極堆疊物30。
接著，以取代閘極堆疊物取代包含硬遮罩層36、虛設閘極電極34和虛設閘極介電質32的虛設閘極堆疊物30。取代閘極堆疊物包含金屬閘極和取代閘極介電質，如第7A和7B圖所示。第7B圖顯示由第7A圖中包含線7B-7B的垂直平面得到的剖面示意圖。依據本發明一些實施例，取代製程包含在一個或複數個蝕刻步驟中蝕刻如第6A和6B圖所示的硬遮罩層36、虛設閘極電極34和虛設閘極介電質32，以得到形成於閘極間隙壁38的兩側部分之間的開口。
接著，請參照第7A和7B圖，形成(取代)閘極堆疊物60，閘極堆疊物60包含閘極介電層52和閘極電極56。對應的製程顯示於第25圖所示的製程流程200中的製程210。第7B圖顯示閘極堆疊物60的剖面示意圖。剖面示意圖由第7A圖中包含線7B-7B的垂直平面得到。閘極堆疊物60的形成包含形成/沉積複數層，且接著進行平坦化製程，例如化學機械研磨製程或機械研磨製程。閘極介電層52延伸至由虛設閘極堆疊物移除所留下溝槽中。依據本發明一些實施例，每個閘極介電層52包含界面層(Interfacial Layer，IL)(未顯示)作為其下部。界面層形成於突出鰭24’暴露的表面上。每個界面層可包含氧化物層，例如氧化矽層，其透過突出鰭24’的熱氧化、化學氧化製程或沉積製程形成。閘極介電層52也可包含形成於界面層上方的高介電常數介電層。高介電常數介電層可包含高介電常數介電材料，例如HfO 2、ZrO 2、HfZrO x、HfSiO x、HfSiON、ZrSiO x、HfZrSiO x、Al 2O 3、HfAlO x、HfAlN、ZrAlO x、La 2O 3、TiO 2、Yb 2O 3、氮化矽或類似物。高介電常數介電材料的介電常數(k值)大於3.9，且可大於7.0。高介電常數介電層形成為順應性層，且延伸於突出鰭24’的側壁上和閘極間隙壁38的側壁上。依據本發明的一些實施例，高介電常數介電層透過使用原子層沉積或化學氣相沉積形成。
請參照第7A和7B圖，閘極電極56形成於閘極介電層52的頂部上，並填充由移除的虛設閘極堆疊物所留下的溝槽的剩下部分。閘極電極56的子層未個別顯示於第7A圖中，然而實際上，由於子層之間組成的差異，因此子層之間彼此為可區分的。至少下部子層的沉積可透過使用例如原子層沉積或化學氣相沉積的順應性沉積方法進行，使得閘極電極56(及每個子層)的垂直部分和水平部分的厚度彼此大致相同。
閘極電極56可包含複數層，其包含氮化鈦矽(TSN)層、氮化鉭(TaN)層、氮化鈦(TiN)層、鈦鋁(TiAl)層、額外的TiN及/或TaN層以及填充金屬。這些層的一些定義了對應鰭式場效電晶體的功函數。再者，p型鰭式場效電晶體的金屬層和n型鰭式場效電晶體的金屬層可彼此不同，因此金屬層的功函數適用於對應的p型鰭式場效電晶體或n型鰭式場效電晶體。填充金屬可包含鋁、鎢或鈷。
接著，如第8A和8B圖所示，形成硬遮罩62。硬遮罩62的材料可相同於或不同於接觸蝕刻停止層46、層間介電質48及/或閘極間隙壁38中的一些的材料。依據一些實施例，硬遮罩62由氮化矽、氮氧化矽、碳氧化矽、氮碳氧化矽或類似物形成。硬遮罩62的形成可包含透過蝕刻將閘極堆疊物60凹陷以形成凹口，填充介電材料於凹口中，並進行平坦化以移除介電材料的多餘部分。介電材料的剩下部分為硬遮罩62。第8B圖顯示第8A圖顯示的結構的剖面示意圖，此剖面示意圖由第8A圖中包含線8B-8B的平面得到。
第9、10A、10B、10C、11A、11B、11C、12A、12B、12C、13-18、19A、19B、19C、20A、20B和20C圖顯示切割金屬閘極製程。後續製程的圖號可包含字母“A”、“B”或“C”。除非另有說明，具有字母“A”的圖式相同於第9圖中包含線A-A的垂直平面得到。具有字母“B”的圖式相同於第9圖中包含線B-B的垂直平面得到。具有字母“C”的圖式相同於第9圖中包含線C-C的垂直平面得到。
第9、10A、10B和10C圖顯示墊層64、硬遮罩層66和圖案化光阻68的形成。底部抗反射塗層(Bottom Anti-Reflective Coating，BARC)(未顯示)也可形成於硬遮罩層66與圖案化光阻68之間。第10A、10B和10C圖分別顯示由第9圖中包含線A-A、B-B和C-C的垂直平面得到的剖面示意圖。依據一些實施例，墊層64由含金屬材料形成，例如TiN、TaN或類似物。墊層64也可由介電材料形成，例如氧化矽。硬遮罩層66可由SiN、SiON、SiCN、SiOCN或類似物形成。形成方法可包含原子層沉積、電漿輔助化學氣相沉積或類似方法。圖案化光阻68塗佈於硬遮罩層66上方，且開口70形成於圖案化光阻68中。開口70具有長度方向(從頂部來看)垂直於閘極堆疊物60的長度方向，且閘極堆疊物60的一部分在開口70的一部分正下方，如第9、10A和10B圖所示。開口70也可延伸至層間介電質48的一些部分，如第10A和10C圖所示。
第11A、11B和11C圖顯示硬遮罩層66的蝕刻，其中將圖案化光阻68(請參照第10A、10B和10C圖)用作蝕刻遮罩。開口70進而延伸至硬遮罩層66中。對應的製程顯示於第25圖所示的製程流程200中的製程212。墊層64的頂表面進而暴露於開口70中。接著，移除圖案化光阻68。
第12A、12B和12C圖顯示依據一些實施例之硬遮罩層72的形成，其使開口72變窄。對應的製程顯示於第25圖所示的製程流程200中的製程214。依據本發明一些實施例，硬遮罩層72由相同於硬遮罩層66的材料形成，其可例如為SiN。硬遮罩層72也可由不同於硬遮罩層66的材料形成。硬遮罩層72透過使用例如原子層沉積或化學氣相沉積的順應性形成，因此硬遮罩層72的垂直部分和水平部分的厚度彼此大致相同。舉例來說，硬遮罩層72的垂直部分和水平部分的厚度差異小於水平部分的厚度的約10%。形成硬遮罩層72以縮小開口70的水平寬度，因此縮小了後續形成的隔離區的寬度。依據本發明其他實施例，省略硬遮罩層72的形成。
第13-18圖顯示移除開口70中的硬遮罩層72的底部，並形成溝槽74。第13-18圖的剖面示意圖由第9圖中的參考剖面B-B得到。硬遮罩層72的底部可在非等向性蝕刻製程中移除，直到暴露出墊層64。硬遮罩層72的垂直部分留在開口70中，且開口70的寬度透過硬遮罩層72的剩下部分而減少。接著，蝕刻墊層64和下方的硬遮罩層62和閘極電極56，以形成溝槽74，溝槽74延伸至閘極電極56的中間水平高度。對應的製程顯示於第25圖所示的製程流程200中的製程216。也蝕刻閘極間隙壁38和層間介電質48的暴露部分(為顯示於第13圖，可見於第21圖)。
依據本發明一些實施例，此蝕刻透過使用選自Cl 2、BCl 3、Ar、CH 4、CF 4和前述之組合的製程氣體進行，但不限於此。閘極電極56的蝕刻可以壓力在約2.5mTorr與約25mTorr之間的範圍中進行。射頻功率應用於主要蝕刻中，且射頻功率可在約250W與約2500W之間的範圍中。也可應用偏壓電壓在約25V與約750V之間的範圍中。此蝕刻可在溝槽74的底表面在閘極電極56的頂表面與底表面之間的中間水平高度時停止。
第14-16圖顯示沉積-蝕刻循環。請參照第14圖，進行沉積製程，其導致介電層76的沉積。對應的製程顯示於第25圖所示的製程流程200中的製程218。介電層76包含在溝槽74的側壁上的側壁部分以保護側壁，因此當溝槽74向下延伸時，溝槽74的上部不會橫向擴展。依據本發明一些實施例，介電層76的沉積透過使用包含SiCl­ 4、O 2、Ar和類似物的製程氣體進行。得到的介電層76包含SiO 2於其中，其可與或可不與其他元素(例如碳)混合。
接著，請參照第15圖，進行介電質分斷製程，使得在溝槽74的底部處的介電層76的底部在非等向性蝕刻/轟擊製程中移除。對應的製程顯示於第25圖所示的製程流程200中的製程220。依據一些實施例，使用碳氟氣體(例如C 4F 6)以蝕刻介電層76的底部。可在蝕刻製程期間縮小介電層76在硬遮罩層66的頂表面上的部分的厚度。在蝕刻製程期間也可縮小介電層76在溝槽74的側壁上的部分的厚度。
請參照第16圖，進行另一蝕刻製程使溝槽74更延伸深入閘極電極56中。對應的製程顯示於第25圖所示的製程流程200中的製程222。此蝕刻透過使用合適的蝕刻氣體進行，蝕刻氣體取決於閘極電極56的被蝕刻部分的材料。依據一些實施例，聚合物(例如C xH y，x和y為整數)可形成於開口的底部。聚合物示意性地以符號75顯示。接著，可例如使用氧(O 2)移除聚合物。
依據一些實施例閘極電極56的蝕刻包含複數個沉積-蝕刻循環，每個循環包含介電質沉積製程、介電質分斷製程、將溝槽74向下延伸的蝕刻製程以及可能的聚合物移除製程。複數個沉積-蝕刻循環以迴圈製程顯示於第25圖中的製程流程200。舉例來說，第17圖顯示進行額外的沉積製程以進一步形成介電層76。顯示的介電層76也包含介電層在先前的沉積製程形成的部分。在後續的製程中，在介電質分斷製程中蝕刻介電層76，並進一步蝕刻閘極電極56。每個沉積-蝕刻循環導致溝槽74進一步向下延伸，直到蝕刻通過閘極電極56和閘極介電層52，且溝槽74延伸至隔離區22中。得到的結構顯示於第18圖。溝槽74可停止於隔離區22中，或可進一步延伸至基底20在隔離區22正下方的塊狀部分中。在最後的蝕刻製程之後，不再沉積介電層，因此在第18圖中，介電層76的底端高於溝槽74的底部。移除如在溝槽74中的任何聚合物層。
在後續的製程中，移除介電層76，且得到的結構顯示於第19B圖中。對應的製程顯示於第25圖所示的製程流程200中的製程224。依據一些實施例，介電層76包括氧化矽，且介電層76的移除可透過使用HF和氨(NH 3)氣體進行。可添加稀釋氣體，例如Ar、He、N 2或類似物或前述之組合。介電層76與HF和氨反應以形成固體層，此反應可在第一製程腔體中達成。接著，將包含固體層的晶圓轉移至第二製程腔體，其中烘烤晶圓10，使得固體層昇華為氣體，並將氣體排出。反應式可如以下如示: SiO 2(s)+ 4HF (g)+ 4NH 3(g)à SiF 4(g)+ 2H 2(g)O (g)+ 4NH 3[反應式1] SiF 4(g)+ 2HF (g)+ 2NH 3(g)à (NH 4) 2SiF 6(s)[反應式2] (NH 4) 2SiF 6(s)à SiF 4(g)+ 2HF (g)+ 2NH 3(g)[反應式3]
在以上反應式中，字母“s”表示固態，而字母“g”表示氣態。反應式1和反應式2為發生於第一製程腔體中的反應，而反應式3發生於第二製程腔體中，其中將晶圓加熱至溫度大於約100°C以將(NH 4) 2SiF 6(s)昇華。形成的(NH 4) 2SiF 6(s)比介電層76更厚。舉例來說，每1nm的介電層76發生反應，可產生3.5nm的(NH 4) 2SiF 6(s)。
實驗結果顯示最終電晶體的臨界電壓受介電層76影響，且受介電層76的移除製程影響。再者，最終溝槽74的寬度可受移除製程影響，其可因為移除閘極電極56暴露於溝槽74的表面部分。在整個晶圓10中，可不均勻地移除晶圓10的不同部分(例如邊緣部分或中央部分)。舉例來說，反應氣體HF和NH 3­可從晶圓10的頂部引入第一腔體中，且氣體的出口可在第一腔體的側壁上。此可導致在晶圓10的不同部分上的氣體的有效流量不一致。舉例來說，介電層76靠近晶圓10的中央部分可具有比介電層76靠近晶圓10的邊緣部分更小的移除速率。
為了達成介電層76的更均勻的移除，可調整各種製程條件。依據本發明一些實施例，當介電層76與HF和氨反應時，可提供晶圓10在中央部分比邊緣部分有著更低的溫度。舉例來說，第22圖顯示靜電夾盤80的上視圖，其中晶圓10固定於靜電夾盤80上。晶圓10可包含中央部分10A和環繞中央部分10A的邊緣部分10B。中央部分10A的半徑R1在晶圓10的半徑R2的約50%與約80%之間的範圍中。在移除介電層76期間，中央部分10A維持在第一溫度T1，第一溫度T1低於邊緣部分10B的第二溫度T2。由於介電層76的移除可為放熱反應，因此較低的溫度導致較高的反應速率，故增加在中央部分10A中的介電層76的部分的移除速率，以補償其較低的反應速率。溫度差(T2-T1)不能太大或太小。如果溫度差太大(例如大於15°C)，因為中央部分和邊緣部分會彼此影響，因此溫度差會難以維持。如果溫度差太小，由溫度差導致的反應速率差異不夠大以補償晶圓10的中央部分10A與邊緣部分10B之間的移除速率差異。依據一些實施例，溫度差(T2-T1)小於約15°C，且可在約5°C與約15°C之間的範圍中。溫度差可透過調整靜電夾盤80的中央部分的溫度低於靜電夾盤80的邊緣部分的溫度來達到。在移除介電層76時，晶圓10的整體溫度可在約25°C與約90°C之間的範圍中。
介電層76的移除速率的一致性也與第一製程腔體(其中發生反應式1和2)的壓力和第一製程腔體中的稀釋氣體(例如Ar、N 2、He或類似物)的流量相關。舉例來說，第23圖顯示晶圓10中的介電層76的移除速率的一致性值與壓力之間的關係。第23圖顯示隨著壓力增加，一致性增加(改善)並在約85Torr至約100Torr達到最大值。當壓力進一步增加，一致性降低。因此，晶圓10的所期望壓力可透過實驗找到。舉例來說，透過使用不同壓力從具有相同結構的複數個晶圓樣品移除介電層76，可找到所期望的壓力。接著，可透過使用與最高一致性相關之找到的所期望的壓力形成產品晶圓。
介電層76的移除速率的一致性也與稀釋氣體(例如Ar、N 2、He或類似物)的流量相關。舉例來說，第23圖顯示晶圓10中的介電層76的移除速率的一致性值與氬(其被採用作為稀釋氣體)的流量之間的關係。第24圖顯示隨著氬的流量增加，一致性增加(改善)並當載氣氬具有流量在約200sccm與約250sccm之間的範圍中時達到最大值。當氬的流量進一步增加，一致性降低。因此，氬的所期望流量可透過實驗找到。舉例來說，透過使用不同流量的稀釋氣體從具有相同結構的複數個晶圓樣品移除介電層76，可找到所期望的稀釋氣體的流量。接著，可透過使用與最高一致性相關之找到的所期望的稀釋氣體的流量形成產品晶圓。
透過調整例如晶圓溫度分佈、壓力和稀釋氣體的流量的製程條件，介電層76的移除可為大致均勻的。
依據一些實施例，介電層76的移除在一個反應及昇華循環中達成，其中將晶圓10放置於第一製程腔體中用於發生反應式1和2，且接著將晶圓10放置於第二製程腔體中用於發生反應式3。依據其他實施例，介電層76的移除包含複數個反應及昇華循環，每個循環移除介電層76的一部分。
第19B圖顯示晶圓10，其中已完全移除介電層76(請參照第18圖)。第19A和19C圖顯示第19B圖所示的晶圓10，除了第19A和19C圖中的剖面示意圖由與第9圖中含有線A-A和C-C的相同平面得到(而第19B圖的剖面示意圖由第9圖中的線B-B得到)。依據本發明一些實施例，在蝕刻閘極堆疊物60(請參照第19B圖)的同時，也蝕刻層間介電質48和接觸蝕刻停止層46(請參照第19A和19C圖)。層間介電質48的蝕刻速率可小於閘極堆疊物60的蝕刻速率。因此，透過蝕刻閘極堆疊物60形成的溝槽74的部分可具有深度D1(請參照第19A圖)大於透過蝕刻層間介電質48形成的溝槽74的部分的深度D2。
第20A、20B和20C圖顯示隔離區82(有時也被稱為介電區)的形成。對應的製程顯示於第25圖所示的製程流程200中的製程226。隔離區82的形成可包含在溝槽74(請參照第19A、19B和19C圖)中填充介電材料，並進行平坦化(例如化學機械研磨製程或機械研磨製程)以移除介電材料的多餘部分。填充方法可包含原子層沉積、電漿輔助化學氣相沉積、化學氣相沉積、旋塗或類似方法。填充材料可包含氮化矽、氧化矽、碳化矽、氮氧化矽、碳氧化矽或類似物。隔離區82進而直接接觸層間介電質48、接觸蝕刻停止層46、隔離區22和基底20，且沒有介電層76於其間。再者，隔離區82可具有包含多於一層(由不同材料形成)的複合結構，或可具有包含由同質材料形成的單一層的同質結構。
第21圖顯示晶圓10和隔離區82的透視圖，隔離區82將原本連續的閘極堆疊物60、硬遮罩62和閘極間隙壁38切割為隔開的部分。
本發明實施例具有一些優點特徵。透過在溝槽中形成隔離區之前，移除溝槽的介電層，改善了整體晶圓的臨界電壓的一致性。實驗結果指出切割金屬閘極製程不利地導致臨界電壓偏移。實驗結果也指出如果在不移除溝槽中的介電層的情況下形成隔離區82，靠近隔離區的鰭式場效電晶體的臨界電壓的偏移可為約60mV或更大。隨著在填充隔離區之前移除介電層，靠近隔離區的鰭式場效電晶體的臨界電壓的偏移可降低至約30mV。
依據本發明一些實施例，半導體裝置的形成方法包含蝕刻閘極堆疊物以形成延伸至閘極堆疊物中的溝槽；在閘極堆疊物的側壁上形成介電層，側壁暴露於溝槽；蝕刻介電層以移除在溝槽的底部的介電層的第一部分，其中在蝕刻介電層之後，保留在閘極堆疊物的側壁上的介電層的第二部分；在移除介電層的第一部分之後，移除介電層的第二部分以露出閘極堆疊物的側壁；以及以介電材料填充溝槽以形成介電區，其中介電區接觸閘極堆疊物的側壁。在一實施例中，形成介電層的步驟包括形成氧化矽層。在一實施例中，介電層透過使用包括SiCl 4­­和O 2的製程氣體形成。在一實施例中，填充溝槽的介電區包括氮化矽。在一實施例中，當介電區填充溝槽時，已從溝槽完全移除介電層。在一實施例中，移除介電層的第二部分的步驟包括:將介電層的第二部分與製程氣體反應，以形成固體層；以及將固體層昇華。在一實施例中，當介電層的第二部分與製程氣體反應時，對應晶圓的中央部分在第一溫度，第一溫度低於對應晶圓的邊緣部分的第二溫度。在一實施例中，第二溫度高於第一溫度小於15°C的溫度差。
依據本發明一些實施例，半導體裝置的形成方法包含在半導體鰭上形成虛設閘極堆疊物；形成接觸蝕刻停止層；在接觸蝕刻停止層上方形成層間介電質，其中虛設閘極堆疊物在層間介電質和接觸蝕刻停止層中；以取代閘極堆疊物取代虛設閘極堆疊物；蝕刻取代閘極堆疊物以形成穿過取代閘極堆疊物的溝槽；在取代閘極堆疊物的側壁上沉積氧化層，其中側壁暴露於溝槽；進一步蝕刻取代閘極堆疊物，其中氧化層保護取代閘極堆疊物的側壁免於被進一步蝕刻；從溝槽移除氧化層；在溝槽中沉積介電材料；以及將介電材料平坦化，以在溝槽中留下介電區。在一實施例中，此方法更包括在移除氧化層之前，從溝槽移除聚合物層。在一實施例中，聚合物層透過使用氧移除。在一實施例中，移除氧化層的步驟包括:將氧化層與HF和氨反應以形成固體層；以及將固體層昇華。在一實施例中，當氧化層與HF和氨反應時，包含氧化層於其中的對應晶圓具有中央部分，中央部分的溫度低於環繞中央部分的對應晶圓的邊緣部分的溫度。在一實施例中，在溝槽中形成介電區之後，介電區接觸取代閘極堆疊物的側壁。在一實施例中，當蝕刻取代閘極堆疊物以形成溝槽時，也蝕刻層間介電質，使得溝槽穿過層間介電質。在一實施例中，此方法更包括:形成圖案化硬遮罩，圖案化硬遮罩具有開口於其中；以及形成順應性硬遮罩層延伸至開口中，其中使用圖案化硬遮罩和順應性硬遮罩層作為蝕刻遮罩來蝕刻取代閘極堆疊物。
依據本發明一些實施例，半導體裝置的形成方法包含蝕刻導電區，以形成溝槽；在溝槽的側壁上沉積氧化矽層；將氧化矽層與HF和氨反應，以形成固體層；將固體層加熱以將固體層昇華，使得導電區的側壁暴露於溝槽；以及在溝槽中填充介電區。在一實施例中，氧化矽層透過使用包括SiCl 4­­和O 2的製程氣體形成。在一實施例中，此方法更包括在將氧化矽層反應之前，從溝槽移除所有的聚合物。在一實施例中，溝槽穿過導電區。
前述內文概述了許多實施例的特徵，使本技術領域中具有通常知識者可以從各個方面更加了解本發明實施例。本技術領域中具有通常知識者應可理解，且可輕易地以本發明實施例為基礎來設計或修飾其他製程及結構，並以此達到相同的目的及/或達到與在此介紹的實施例等相同之優點。本技術領域中具有通常知識者也應了解這些相等的結構並未背離本發明的發明精神與範圍。在不背離本發明的發明精神與範圍之前提下，可對本發明實施例進行各種改變、置換或修改。
10 晶圓 10A 中央部分 10B 邊緣部分 20 基底 22、82 隔離區 22A 頂表面 24 半導體條帶 24’ 突出鰭 30 虛設閘極堆疊物 32 虛設閘極介電質 34 虛設閘極電極 36、66、72 硬遮罩層 38 閘極間隙壁 40 凹口 42 磊晶區 46 接觸蝕刻停止層 48 層間介電質 52 閘極介電層 56 閘極電極 60 閘極堆疊物 62 硬遮罩 64 墊層 68 圖案化光阻 70 開口 74 溝槽 75 聚合物 76 介電層 80 靜電夾盤 200 製程流程 202、204、206、208、210、212、214、216、218、220、222、224、226 製程 D1、D2 深度 R1、R2 半徑
根據以下的詳細說明並配合所附圖式可以更加理解本發明實施例。應注意的是，根據本產業的標準慣例，圖示中的各種部件並未必按照比例繪製。事實上，可能任意的放大或縮小各種部件的尺寸，以做清楚的說明。 第1-5、6A、6B、7A、7B、8A、8B、9、10A、10B、10C、11A、11B、11C、12A、12B、12C、13-18、19A、19B、19C、20A、20B、20C和21圖顯示依據一些實施例之形成鰭式場效電晶體(FinFETs)和切割金屬閘極製程的中間階段的透視圖、上視圖和剖面示意圖。 第22圖顯示依據一些實施例之晶圓在移除產生於切割金屬閘極製程中的介電層時的溫度分布。 第23圖顯示依據一些實施例之晶圓上的介電層的蝕刻量的一致性與壓力的關係。 第24圖顯示依據一些實施例之晶圓上的介電層的蝕刻量的一致性與稀釋氣體的流量的關係。 第25圖顯示依據一些實施例之形成鰭式場效電晶體和切割金屬閘極製程的製程流程。
200 製程流程 202、204、206、208、210、212、214、216、218、220、222、224、226 製程

Claims (15)

  1. 一種半導體裝置的形成方法，包括：蝕刻一閘極堆疊物以形成延伸至該閘極堆疊物中的一溝槽；在該閘極堆疊物的一側壁上形成一介電層，該側壁暴露於該溝槽；蝕刻該介電層以移除在該溝槽的底部的該介電層的一第一部分，其中在蝕刻該介電層之後，保留在該閘極堆疊物的該側壁上的該介電層的一第二部分；在移除該介電層的該第一部分之後，移除該介電層的該第二部分以露出該閘極堆疊物的該側壁；以及以一介電材料填充該溝槽以形成一介電區，其中該介電區接觸該閘極堆疊物的該側壁。
  2. 如申請專利範圍第1項所述之半導體裝置的形成方法，其中當該介電區填充該溝槽時，已從該溝槽完全移除該介電層。
  3. 如申請專利範圍第1或2項所述之半導體裝置的形成方法，其中移除該介電層的該第二部分的步驟包括：將該介電層的該第二部分與一製程氣體反應，以形成一固體層；以及將該固體層昇華。
  4. 如申請專利範圍第3項所述之半導體裝置的形成方法，其中當該介電層的該第二部分與該製程氣體反應時，一對應晶圓的一中央部分在一第一溫度，該第一溫度低於該對應晶圓的一邊緣部分的一第二溫度。
  5. 一種半導體裝置的形成方法，包括：在一半導體鰭上形成一虛設閘極堆疊物；形成一接觸蝕刻停止層； 在該接觸蝕刻停止層上方形成一層間介電質，其中該虛設閘極堆疊物在該層間介電質和該接觸蝕刻停止層中；以一取代閘極堆疊物取代該虛設閘極堆疊物；蝕刻該取代閘極堆疊物以形成穿過該取代閘極堆疊物的一溝槽；在該取代閘極堆疊物的一側壁上沉積一氧化層，其中該側壁暴露於該溝槽；進一步蝕刻該取代閘極堆疊物，其中該氧化層保護該取代閘極堆疊物的該側壁免於被進一步蝕刻；從該溝槽移除該氧化層；在該溝槽中沉積一介電材料；以及將該介電材料平坦化，以在該溝槽中留下一介電區。
  6. 如申請專利範圍第5項所述之半導體裝置的形成方法，更包括在移除該氧化層之前，從該溝槽移除一聚合物層。
  7. 如申請專利範圍第6項所述之半導體裝置的形成方法，其中該聚合物層透過使用氧移除。
  8. 如申請專利範圍第5項所述之半導體裝置的形成方法，其中移除該氧化層的步驟包括：將該氧化層與HF和氨反應以形成一固體層；以及將該固體層昇華。
  9. 如申請專利範圍第8項所述之半導體裝置的形成方法，其中當該氧化層與HF和氨反應時，包含該氧化層於其中的一對應晶圓具有一中央部分，該中央部分的溫度低於環繞該中央部分的該對應晶圓的一邊緣部分的溫度。
  10. 如申請專利範圍第5至8項中任一項所述之半導體裝置的形成方 法，其中在該溝槽中形成該介電區之後，該介電區接觸該取代閘極堆疊物的該側壁。
  11. 如申請專利範圍第5至8項中任一項所述之半導體裝置的形成方法，其中當蝕刻該取代閘極堆疊物以形成該溝槽時，也蝕刻該層間介電質，使得該溝槽穿過該層間介電質。
  12. 如申請專利範圍第5至8項中任一項所述之半導體裝置的形成方法，更包括：形成一圖案化硬遮罩，該圖案化硬遮罩具有一開口於其中；以及形成一順應性硬遮罩層延伸至該開口中，其中使用該圖案化硬遮罩和該順應性硬遮罩層作為一蝕刻遮罩來蝕刻該取代閘極堆疊物。
  13. 一種半導體裝置的形成方法，包括：蝕刻一導電區，以形成一溝槽；在該溝槽的一側壁上沉積一氧化矽層；將該氧化矽層與HF和氨反應，以形成一固體層；將該固體層加熱以將該固體層昇華，使得該導電區的側壁暴露於該溝槽；以及在該溝槽中填充一介電區。
  14. 如申請專利範圍第13項所述之半導體裝置的形成方法，更包括在將該氧化矽層反應之前，從該溝槽移除所有的聚合物。
  15. 如申請專利範圍第13或14項所述之半導體裝置的形成方法，其中該溝槽穿過該導電區。
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