CN103579175A - 具有阻挡层的铜接触插塞 - Google Patents

具有阻挡层的铜接触插塞 Download PDF

Info

Publication number
CN103579175A
CN103579175A CN201210390173.XA CN201210390173A CN103579175A CN 103579175 A CN103579175 A CN 103579175A CN 201210390173 A CN201210390173 A CN 201210390173A CN 103579175 A CN103579175 A CN 103579175A
Authority
CN
China
Prior art keywords
layer
aluminous
conductive layer
sidewall sections
contact
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201210390173.XA
Other languages
English (en)
Other versions
CN103579175B (zh
Inventor
苏莉玲
谢静华
陈煌明
曹学文
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN103579175A publication Critical patent/CN103579175A/zh
Application granted granted Critical
Publication of CN103579175B publication Critical patent/CN103579175B/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28088—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a composite, e.g. TiN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76847—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned within the main fill metal
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/495—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a simple metal, e.g. W, Mo
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53214—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being aluminium
    • H01L23/53223—Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H01L23/53295—Stacked insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Composite Materials (AREA)
  • Materials Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

本发明公开了具有阻挡层的铜接触插塞，其中，一种器件包括导电层，导电层包括底部以及位于底部上方的侧壁部分，其中侧壁部分连接至底部的端部。含铝层与导电层的底部重叠，其中含铝层的顶面与导电层的侧壁部分的顶部边缘基本平齐。氧化铝层覆盖在含铝层之上。含铜区域位于氧化铝层上方并通过氧化铝层与含铝层隔开。含铜区域通过导电层的侧壁部分的顶部边缘电连接至含铝层。

Description

具有阻挡层的铜接触插塞
技术领域
本发明总的来说涉及半导体领域，更具体地，涉及具有阻挡层的铜接触插塞。
背景技术
半导体处理持续的进步使得最小部件尺寸和工艺定标进一步减小。随着半导体工艺节点发展为更小的最小部件尺寸，例如28纳米、22纳米以及更小，减小了器件部件(诸如栅极和相应衬底)上接触插塞的可用面积。此外，随着半导体工艺中所使用材料的发展，观察到由于使用这些先进材料而对接触阻抗产生的附加影响。因此，正在研究用于减小相应影响的方法。
接触插塞用于在集成电路结构的诸如第一层金属(被称为M1)的导电层与形成在该层下方的衬底区域或栅极区域之间形成垂直电连接件。通常使用的接触插塞包括钨插塞。
发明内容
根据本发明的一个方面，提供了一种器件，包括：导电层，导电层包括底部以及位于底部上方的侧壁部分，其中侧壁部分连接至底部的端部；含铝层，与导电层的底部重叠，含铝层的顶面与导电层的侧壁部分的顶部边缘基本平齐；氧化铝层，覆盖在含铝层之上；以及含铜区，位于氧化铝层上方并通过氧化铝层与含铝层隔开，含铜区通过导电层的侧壁部分的顶部边缘与含铝层电连接。
优选地，该器件还包括金属氧化物半导体(MOS)器件，其中，MOS器件包括：栅电极，包括含铝层和导电层；以及栅极接触插塞，包括含铜区。
优选地，栅电极形成替换栅极的一部分。
优选地，该器件还包括润湿层，润湿层包括：位于含铝层的底部的下方并与其接触的底部；以及位于含铝层的侧壁和导电层的侧壁部分之间并与它们接触的侧壁部分。
优选地，润湿层包括接触含铝层的基本纯钛层。
优选地，该器件还包括阻挡层，阻挡层包括：位于含铜区的底部的下方并与其接触的底部，其中，底部包括接触导电层的侧壁部分的顶部边缘的第一底面；以及接触含铜区的侧壁的侧壁部分。
优选地，阻挡层的底部还包括接触氧化铝层的顶面的第二底面。
优选地，阻挡层包括基本纯钛层。
根据本发明的另一方面，提供了一种器件，包括：润湿层，包括第一底部和位于第一底部上方并连接至第一底部的端部的第一侧壁部分；含铝层，与第一底部重叠，含铝层的侧壁接触所述润湿层的第一侧壁部分；阻挡层，包括位于含铝层上方并与其接触第二底部和位于第二底部上方并连接至第二底部的端部第二侧壁部分；以及含铜区，与润湿层的第二底部重叠并与阻挡层的第二侧壁部分平齐，其中，润湿层和阻挡层中的至少一个包括基本纯钛层。
优选地，润湿层包括基本纯钛层，并且基本纯钛层接触含铝层的底面和侧壁。
优选地，阻挡层包括基本纯钛层。
优选地，该器件还包括金属氧化物半导体(MOS)器件，其中，MOS器件包括：栅电极，包括含铝层和润湿层；以及栅极接触插塞，包括含铜区和阻挡层。
优选地，MOS器件还包括：源极/漏极区，与栅电极相邻；以及上部源极/漏极接触插塞，电连接至源极/漏极区，其中上部源极/漏极接触插塞包括：附加阻挡层，附加阻挡层的底面与含铝层的顶面基本平齐；和附加含铜区，位于附加阻挡层上方，附加含铜区的顶面与含铜区的顶面基本平齐。
优选地，该器件还包括连接在上部源极/漏极接触插塞和源极/漏极区之间的下部接触插塞，下部接触插塞包括钨。
优选地，含铝层的铝原子百分比高于约90％，其中含铜区的铜原子百分比高于约90％。
根据本发明的又一方面，提供了一种方法，包括：形成导电层，导电层包括底部以及位于底部上方的侧壁部分，其中，侧壁部分连接至底部的端部；在导电层的底部上方形成含铝层，氧化铝层形成在含铝层的顶面；在含铝层上方形成介电层；在介电层中形成开口以暴露导电层的侧壁部分的顶部边缘以及氧化铝层的一部分；利用阻挡层和位于阻挡层上方的含铜材料填充所述开口；以及去除阻挡层和含铜材料的过量部分，开口中剩余的阻挡层的部分和含铜材料的部分形成接触插塞，并且阻挡层包括接触氧化铝层的顶面的第一底面以及接触导电层的顶部边缘的第二底面。
优选地，在形成接触插塞之后，通过开口露出的氧化铝层的一部分保持未去除。
优选地，该方法还包括：从层间介电层(ILD)中去除伪栅极以在ILD中形成开口；在开口中沉积栅极介电层；在栅极介电层上方沉积导电层；在导电层上方沉积含铝层；以及在形成介电层的步骤之前，对栅极介电层、导电层以及含铝层执行平面化。
优选地，形成阻挡层的步骤包括沉积基本纯钛层。
优选地，该方法还包括：在形成导电层的步骤之后和形成含铝层的步骤之前，沉积基本纯钛层，其中含铝层接触基本纯钛层。
附图说明
为了更加完整地理解本实施例及其优点，现在结合附图作为参考进行下面的描述，其中：
图1至8是根据一些示例性实施例的金属氧化物半导体(MOS)器件和上覆结构制造的中间阶段的截面图和俯视图。
图9至11是根据可选示例性实施例的MOS器件和上覆结构制造的中间阶段的截面图和俯视图。
具体实施方式
下面详细讨论本发明实施例的制造和使用。然而，应该理解，实施例提供许多可以在各种具体环境中具体化的可应用发明概念。所讨论的具体实施例是说明性的而不限制本发明的范围。
根据各种示例性实施例，提供了包括含铝栅电极和含铜接触插塞的金属氧化物半导体(MOS)器件及其形成方法。示出形成MOS器件的中间阶段。讨论实施例的变化和操作。在各附图和说明性实施例中，类似的参考标号用于指定类似的元件。在一些说明实施例中，利用后栅极方法来形成含铝栅电极。然而，根据可选实施例，也可以利用前栅极方法形成含铝栅电极。
图1至8是根据一些示例性实施例的MOS器件和上覆结构制造的中间阶段的截面图和俯视图。参照图1，提供了晶圆10。晶圆10包括衬底20，其可由诸如硅、硅锗、碳化硅、III-V化合物半导体材料等的半导体材料形成。衬底20是体硅或绝缘体上半导体(SOI)衬底。在衬底20中形成源极和漏极区域(下文也称为源极/漏极区域)22。在衬底20之上形成层间介电层(ILD，下文称为ILD0)24。ILD0 24可以由诸如磷硅玻璃(PSG)、硼硅玻璃(BSG)、掺硼磷硅玻璃(BPSG)、正硅酸乙酯(TEOS)氧化物等的氧化物形成。
在ILD0 24中形成伪栅极结构26。伪栅极结构26包括伪栅电极28，例如其可由多晶硅形成，尽管也可以使用其它材料。在一些实施例中，伪栅极结构26还包括伪隔离件30和/或伪栅极介电层32。在可选实施例中，不形成伪隔离件30和/或伪栅极介电层32。伪栅极结构26的顶面与ILD0 24的顶面平齐。
参照图2，通过蚀刻去除伪栅极结构26。因此，在ILD0 24中形成开口34。结果，在一些示例性实施例中，通过开口34露出衬底20的顶面。接下来，参照图3，沉积作为介电层的栅极介电层36。在栅极介电层36之上还沉积作为导电层的栅电极层44。栅极介电层36和栅电极层44均包括覆盖ILD0 24的一部分和覆盖开口34(图2)的一部分。在一些实施例中，栅极介电层36和栅电极层44是共形层，它们的水平部分具有与相应的垂直部分基本相同的厚度。
栅极介电层36可以是单层或包括多层的复合层。例如，栅极介电层36可包括氧化层和位于氧化层上方的高k介电层。氧化层可以是通过沉积形成的氧化硅层。高k介电层可包括氧化铪、氧化锆等。在一些示例性实施例中，例如由氮化钛形成的阻挡层(未示出)形成在高k介电层上方。
在一些实施例中，栅电极层44包括导电层38、位于导电层38上方的润湿层(wetting layer)40以及位于润湿层40上方的含铝层42。导电层38可包括多晶硅、TaSiN、WN、TiAlN、TaC等。在可选实施例中，栅电极层44包括位于导电层38上方的润湿层40和位于润湿层40上方的含铝层42。然而，在这些实施例中不形成导电层38。导电层38的厚度可以在大约1nm到大约10nm之间，尽管还可以使用更厚或更薄的厚度。根据层38、40、42的材料，含铝层42、润湿层40和导电层38的形成可包括物理汽相沉积(PVD)、金属有机汽相沉积(MOCVD)和/或其它可应用方法。
在一些示例性实施例中，含铝层42的铝原子百分比大于约90％，或者大于约95％。然而，应当理解，说明书中的值仅仅是实例，并且可以变为不同值。例如。含铝层42位于开口34(图2)内的部分可具有大约25nm到大约1μm之间的横向尺寸W1。例如，润湿层40用于增强含铝层42和导电层38之间的粘附力，并且可具有约1nm到大约10nm之间的厚度。润湿层40的钛原子百分比大于约60％。例如，润湿层40还可以是基本纯钛层，其钛原子百分比大于约95％。基本纯钛层(如果有的话)可与上面的含铝层42物理接触。纯钛层可帮助防止含铝层42和上覆含铜区域56B(图7A)之间的铝和铜的相互扩散。其原因在于钛与上覆含铝层42形成良好的接合，因此，对于含铝层42中良好接合的铝原子来说更加难以向上迁移到含铜区域56B。在可选实施例中，润湿层40是单层或者包括Ti、TiN、Ta、TaN、和/或类似材料的复合层。
参照图4，执行诸如化学机械抛光(CMP)的平面化以去除栅极介电层36和栅电极层44的过量部分，其中过量部分位于ILD0 24的上方。所得到的结构包括替换栅极叠层45。栅极介电层36和栅电极层44的剩余部分在下文中被称为栅极介电质36和栅电极44。在所示实施例中，栅极介电质36、导电层38和润湿层40均包括底部以及位于底部的相对端上方并与其连接的侧壁部分。在CMP之后，可以在含铝层42的顶面上方形成氧化铝层46并且氧化铝层46与含铝层42的顶面接触。
图5示出了下文称为M0_OD1 48的下部源极/漏极接触插塞48的形成，其中，术语“OD”表示接触插塞48连接至有源区域。下面简要讨论示例性形成工艺。形成工艺可包括蚀刻ILD0 24以形成开口(被接触插塞48占用)，从而暴露源极和漏极区域22。然后，穿过开口执行自对准硅化以在开口的底部形成硅化物区域50。导电材料填充在开口中，随后通过CMP步骤去除过量的导电材料。导电材料的剩余部分形成接触插塞48。在一些实施例中，M0_OD1 48包括粘附/阻挡层48A以及位于粘附/阻挡层48A上方的钨插塞48B。粘附/阻挡层48A可包含选自钛、氮化钛、钽、氮化钽、它们的组合或它们的多层的材料。例如，钨插塞48B可由钨或钨合金形成。
参照图6，蚀刻终止层52形成在栅极结构45和ILD0 24的上方并与它们物理接触。在一些实施例中，蚀刻终止层52由氮化硅形成。可选地，可以使用诸如碳化硅、氮氧化硅等的其他介电材料。在形成蚀刻终止层52之后，被称为ILD1 54的另一ILD形成在蚀刻终止层52上方。ILD1 54可由PSG、BSG、BPSG、TEOS氧化物等形成。
图7A示出了栅极接触插塞56以及源极/漏极接触插塞58的形成，它们可以同时形成或者在不同的工艺步骤中形成。源极/漏极接触插塞58在下文也被称为M0_OD2或上部源极/漏极接触插塞。源极/漏极接触插塞58与相应下方的源极/漏极接触插塞M0_OD1 48(其为下部源极/漏极接触插塞)对齐并与其接触。栅极接触插塞56电连接至栅电极44。栅极接触插塞56和M0_OD2 58均包括被称为56A或58A的阻挡层以及被称为56B或58B的含铜区域。形成工艺可包括蚀刻ILD1 54以及蚀刻终止层52以形成开口，并用阻挡层和含铜层填充开口。然后，执行CMP以去除阻挡层和含铜层过量部分。阻挡层的剩余部分形成阻挡层56A和58A，而含铜层的剩余部分形成含铜区域56B和58B。
在一些实施例中，阻挡层56A包括从包含Ti层、TiN层、Ta层、TaN层和它们的多层的组中选择的层。当阻挡层56A(或58A)是基本纯钛层时，基本纯钛层可以与含铜区域56B(或58A)的底面和侧壁物理接触或者不与其物理接触。基本纯钛层位于含铜区域56B和含铝层42之间，因此形成了防止含铜区域56B中的铜与含铝层42中的铝相互扩散的良好阻挡。例如，阻挡层56A的厚度可在大约2nm到大约20nm之间。含铜区域56B和58B的铜原子百分比可大于约80％或者大于约100％。
栅极接触插塞56(以及相应的阻挡层56A)包括与导电层38的顶部边缘接触(以及可能的润湿层40的顶部边缘)的部分。在一些实施例中，当开口(填充栅极接触插塞56)暴露时，氧化铝层46的暴露部分没有被蚀刻。因此，栅极接触插塞56(以及相应的阻挡层56A)可进一步包括位于氧化铝层46的顶面上方并与其接触的部分，其是不导电的。结果，栅电极44和栅极接触插塞56之间的电连接通过导电层38和/或润湿层的顶部边缘而不是通过含铝层42的顶面实现的。
图7B和7C示出了图7A所示结构的一些示例性俯视图。参照图7B，栅极接触插塞56可以不与氧化铝层46的中心对齐。相反，栅极接触插塞56与栅电极44的一侧对齐以接触导电层38和/或润湿层40的顶部边缘。图7C示出了两个栅极接触插塞56电连接至同一栅电极44，其中一个栅极接触插塞56比栅电极44宽，使得可与位于氧化铝层46相对侧的部分层38/40接触。其它栅极接触插塞56也不与氧化铝层46对齐以接触层38/40。
参照图8，在随后的工艺中，蚀刻终止层59、M0通孔62以及金属线64形成在底部金属层M1中。例如，M0通孔62和金属线64形成在介电层60中，其中介电层60可由k值小于约3.0或小于约2.5的低k介电材料形成。在一些实施例中，M0通孔62和金属线64使用双镶嵌工艺形成，因此在M0通孔62和相应的上覆金属线64之间没有明显的界面。在可选实施例中，M0通孔62可使用单镶嵌工艺形成，并且金属线64也可以使用单镶嵌工艺形成。在其他实施例中，不形成M0通孔62，而金属线64与接触插塞56和58接触。M0通孔62和金属线64可包括扩散阻挡层和位于扩散阻挡层上方的含铜层。在随后的工艺中，更多的金属层(未示出)可形成在金属层M1上方。
图9至11示出了根据可选实施例的MOS器件和上覆结构制造的中间阶段的截面图。除另有指定，否则这些实施例中的部件的材料和形成方法都与图1至8所示实施例中的部件相同并且用类似的参考标号来表示。因此，可以在图1至图8所示实施例的讨论中找到关于图9至11所示部件的形成工艺和材料的细节。
这些实施例的初始步骤与图1至6所示步骤基本相同。接下来，如图9所示，蚀刻ILD1 54和下方的蚀刻终止层52，并形成开口70和72。当形成氧化铝层46时，也蚀刻通过开口70暴露的部分氧化铝层46，并且下方的含铝层42暴露于开口70。接下来，如图10A所示，栅极接触插塞56和M0_OD2 58分别形成在开口70和72中。栅极接触插塞56(以及阻挡层56A)与含铝层42接触，并穿透氧化铝层46。图10A所示结构的相应俯视图如图10B和图10C所示。如图10B所示，栅极接触插塞可以与氧化铝层46对齐或不对齐。当栅极接触插塞56不与氧化铝层46对齐时，阻挡层56A的底面可与导电层38和润湿层40的顶部边缘接触。如图10C所示，栅极接触插塞56还可以宽于含铝层42，因此可与含铝层42的顶面以及层38和40的顶部边缘接触。图11示出了形成金属层M1后的结构。
在图8和图11的实施例中，阻挡层56A包含钛层(根据一些实施例其基本可以是纯的)，或者润湿层40包含钛层。当润湿层40包括钛层时，钛层可与含铝层42的底面和侧壁接触。在可选实施例中，钛层形成在阻挡层56A和润湿层40中。钛层帮助减少含铜区域56B中的铜和含铝层42中的铝的相互扩散。此外，在图8所示的实施例中，氧化铝层46还助减少相互扩散。
尽管在实施例中，含铝栅电极和含铜接触插塞被用作实例来解释实施例的概念，但实施例的概念可用于减少其它含铝区域和含铜区域之间的相互扩散，包括但不限于例如含铝金属焊盘和上方的含铜钝化后互连(PPI)结构。在这些实施例中，含铝金属焊盘和含铜PPI结构形成在所有低k介电层上方，其中含铜PPI结构进一步形成在钝化层上方。
根据实施例，一种器件包括：导电层，包括底部和底部上方的侧壁部分，其中侧壁部分连接至底部的端部。含铝层与导电层的底部重叠，含铝层的顶面基本上与导电层的侧壁部分的顶部边缘平齐。氧化铝层覆盖在含铝层之上。含铜区域位于氧化铝层上方并通过氧化铝层与含铝层隔开。含铜区域通过导电层的侧壁部分的顶部边缘电连接至含铝层。
根据其它实施例，一种器件包括：润湿层，包括第一底部以及位于第一底部上方并连接至第一底部的端部的第一侧壁部分。含铝层与第一底部重叠，其中含铝层的侧壁接触润湿层的第一侧壁部分。阻挡层包括位于含铝层上方并与其接触的第二底部以及位于第二底部上方并连接至第二底部部分的端部的第二侧壁部分。含铜区域与润湿层的第二底部重叠，并与阻挡层的第二侧壁部分平齐。润湿层和阻挡层中的至少一个是基本纯钛层。
根据其它实施例，一种方法包括：形成导电层，导电层包括底部以及位于底部上方的侧壁部分，其中侧壁部分连接至底部的端部。含铝层形成在导电层的底部上方，其中，氧化铝层形成在含铝层的顶面。介电层形成在含铝层的上方，随后在介电层中形成开口以暴露导电层的侧壁部分的顶部边缘以及氧化铝层的一部分。用阻挡层和位于阻挡层上方的含铜材料填充开口。去除阻挡层和含铜材料的过量部分。开口中剩余的阻挡层的一部分和含铜材料的一部分形成接触插塞，其中阻挡层包括接触氧化铝层的顶面的第一底面以及接触导电层的顶部边缘的第二底面。
尽管已经详细描述了实施例及其优点，但应该理解，可以进行各种改变、替换和更改而不背离所附权利要求限定的实施例的精神和范围。此外，本申请的范围不旨在限于说明书中描述的工艺、机械装置、制造以及物质组成、工具、方法和步骤的特定实施例。本领域技术人员很容易理解，根据本公开可以利用与本文描述的对应实施例进行基本相同功能或实现基本相同结果的目前现有或即将开发的工艺、机械装置、制造、物质组成、工具、方法或步骤。因此，所附权利要求旨在包括在这种工艺、机械装置、制造、物质组成、工具、方法、或步骤的范围内。此外，每个权利要求都构成独立的实施例，并且各种权利要求和实施例的组合均在公开的范围内。

Claims (10)

1.一种器件，包括：
导电层，所述导电层包括底部以及位于所述底部上方的侧壁部分，其中所述侧壁部分连接至所述底部的端部；
含铝层，与所述导电层的底部重叠，所述含铝层的顶面与所述导电层的侧壁部分的顶部边缘基本平齐；
氧化铝层，覆盖在所述含铝层之上；以及
含铜区，位于所述氧化铝层上方并通过所述氧化铝层与所述含铝层隔开，所述含铜区通过所述导电层的侧壁部分的顶部边缘与所述含铝层电连接。
2.根据权利要求1所述的器件，还包括金属氧化物半导体(MOS)器件，其中，所述MOS器件包括：
栅电极，包括所述含铝层和所述导电层；以及
栅极接触插塞，包括所述含铜区。
3.根据权利要求1所述的器件，还包括阻挡层，所述阻挡层包括：
位于所述含铜区的底部的下方并与其接触的底部，其中，所述底部包括接触所述导电层的侧壁部分的顶部边缘的第一底面；以及
接触所述含铜区的侧壁的侧壁部分。
4.一种器件，包括：
润湿层，包括：
第一底部；和
第一侧壁部分，位于所述第一底部上方并连接至所述第一底部的端部；
含铝层，与所述第一底部重叠，所述含铝层的侧壁接触所述润湿层的第一侧壁部分；
阻挡层，包括：
第二底部，位于所述含铝层上方并与其接触；和
第二侧壁部分，位于所述第二底部上方并连接至所述第二底部的端部；以及
含铜区，与所述润湿层的第二底部重叠并与所述阻挡层的第二侧壁部分平齐，其中，所述润湿层和所述阻挡层中的至少一个包括基本纯钛层。
5.根据权利要求4所述的器件，其中，所述润湿层包括所述基本纯钛层，并且所述基本纯钛层接触所述含铝层的底面和侧壁。
栅极接触插塞，包括所述含铜区和所述阻挡层。
6.一种方法，包括：
形成导电层，所述导电层包括底部以及位于所述底部上方的侧壁部分，其中，所述侧壁部分连接至所述底部的端部；
在所述导电层的底部上方形成含铝层，氧化铝层形成在所述含铝层的顶面；
在所述含铝层上方形成介电层；
在所述介电层中形成开口以暴露所述导电层的侧壁部分的顶部边缘以及所述氧化铝层的一部分；
利用阻挡层和位于所述阻挡层上方的含铜材料填充所述开口；以及
去除所述阻挡层和所述含铜材料的过量部分，所述开口中剩余的所述阻挡层的部分和所述含铜材料的部分形成接触插塞，并且所述阻挡层包括接触所述氧化铝层的顶面的第一底面以及接触所述导电层的顶部边缘的第二底面。
7.根据权利要求6所述的方法，其中，在形成所述接触插塞之后，通过所述开口露出的所述氧化铝层的一部分保持未去除。
8.根据权利要求6所述的方法，还包括：
从层间介电层(ILD)中去除伪栅极以在所述ILD中形成开口；
在所述开口中沉积栅极介电层；
在所述栅极介电层上方沉积所述导电层；
在所述导电层上方沉积所述含铝层；以及
在形成介电层的步骤之前，对所述栅极介电层、所述导电层以及所述含铝层执行平面化。
9.根据权利要求6所述的方法，其中，形成所述阻挡层的步骤包括沉积基本纯钛层。
10.根据权利要求6所述的方法，还包括：在形成所述导电层的步骤之后和形成所述含铝层的步骤之前，沉积基本纯钛层，其中所述含铝层接触所述基本纯钛层。
CN201210390173.XA 2012-07-25 2012-10-15 具有阻挡层的铜接触插塞 Expired - Fee Related CN103579175B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/557,592 2012-07-25
US13/557,592 US9136206B2 (en) 2012-07-25 2012-07-25 Copper contact plugs with barrier layers

Publications (2)

Publication Number Publication Date
CN103579175A true CN103579175A (zh) 2014-02-12
CN103579175B CN103579175B (zh) 2017-05-03

Family

ID=49994053

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201210390173.XA Expired - Fee Related CN103579175B (zh) 2012-07-25 2012-10-15 具有阻挡层的铜接触插塞

Country Status (3)

Country Link
US (4) US9136206B2 (zh)
CN (1) CN103579175B (zh)
TW (1) TWI557864B (zh)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105336724A (zh) * 2014-07-18 2016-02-17 中芯国际集成电路制造(上海)有限公司 半导体器件
CN106206690A (zh) * 2014-12-19 2016-12-07 台湾积体电路制造股份有限公司 具有互连结构的半导体器件及其形成方法
CN107452712A (zh) * 2016-05-31 2017-12-08 台湾积体电路制造股份有限公司 半导体结构
CN108695319A (zh) * 2017-04-10 2018-10-23 三星电子株式会社 具有异质接触件的集成电路
CN108807160A (zh) * 2017-04-28 2018-11-13 台湾积体电路制造股份有限公司 具有减小的电阻率的晶体管的金属栅极
CN110379710A (zh) * 2019-07-25 2019-10-25 上海华力集成电路制造有限公司 金属栅极的制造方法及半导体器件
US10985061B2 (en) 2017-04-20 2021-04-20 Taiwan Semiconductor Manufacturing Company, Ltd. Methods for forming contact plugs with reduced corrosion
CN113629136A (zh) * 2020-05-06 2021-11-09 中芯国际集成电路制造(北京)有限公司 半导体结构及其形成方法

Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DK2409575T3 (en) 2008-10-17 2017-04-03 Nestec Sa Process for Preparation of Whey Protein Compositions
US10043706B2 (en) * 2013-01-18 2018-08-07 Taiwan Semiconductor Manufacturing Company Limited Mitigating pattern collapse
KR20140110146A (ko) * 2013-03-04 2014-09-17 삼성전자주식회사 반도체 소자
US9059166B2 (en) * 2013-05-09 2015-06-16 International Business Machines Corporation Interconnect with hybrid metallization
GB201319079D0 (en) * 2013-10-29 2013-12-11 Univ St Andrews Random Wavelength Meter
US9252053B2 (en) * 2014-01-16 2016-02-02 International Business Machines Corporation Self-aligned contact structure
US10062762B2 (en) * 2014-12-23 2018-08-28 Stmicroelectronics, Inc. Semiconductor devices having low contact resistance and low current leakage
US9466685B2 (en) * 2015-02-23 2016-10-11 Globalfoundries Inc. Semiconductor structure including at least one electrically conductive pillar, semiconductor structure including a contact contacting an outer layer of an electrically conductive structure and method for the formation thereof
US9431343B1 (en) * 2015-03-11 2016-08-30 Samsung Electronics Co., Ltd. Stacked damascene structures for microelectronic devices
KR20160148795A (ko) * 2015-06-16 2016-12-27 삼성전자주식회사 반도체 소자 및 이의 제조 방법
DE102015110437B4 (de) * 2015-06-29 2020-10-08 Infineon Technologies Ag Halbleitervorrichtung mit einer Metallstruktur, die mit einer leitfähigen Struktur elektrisch verbunden ist und Verfahren zur Herstellung
TWI650804B (zh) * 2015-08-03 2019-02-11 聯華電子股份有限公司 半導體元件及其製作方法
CN107564850B (zh) * 2016-07-01 2020-07-07 中芯国际集成电路制造(北京)有限公司 互连结构及其制造方法
US10269706B2 (en) 2016-07-26 2019-04-23 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
US10121873B2 (en) * 2016-07-29 2018-11-06 Taiwan Semiconductor Manufacturing Company, Ltd. Metal gate and contact plug design and method forming same
US9929271B2 (en) * 2016-08-03 2018-03-27 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
US10510598B2 (en) * 2016-11-29 2019-12-17 Taiwan Semiconductor Manufacturing Company, Ltd. Self-aligned spacers and method forming same
US10008416B2 (en) 2016-11-30 2018-06-26 Taiwan Semiconductor Manufacturing Co., Ltd. Forming a protective layer to prevent formation of leakage paths
US10950728B2 (en) 2017-11-16 2021-03-16 Taiwan Semiconductor Manufacturing Co., Ltd. Fin field effect transistor (FinFET) device structure with isolation layer and method for forming the same
US10438846B2 (en) * 2017-11-28 2019-10-08 Taiwan Semiconductor Manufacturing Co., Ltd. Physical vapor deposition process for semiconductor interconnection structures
US20190229173A1 (en) * 2018-01-23 2019-07-25 Int Tech Co., Ltd. Light emitting device and manufacturing method thereof
US11018053B2 (en) * 2018-06-29 2021-05-25 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure with material modification and low resistance plug
KR102612592B1 (ko) * 2018-10-15 2023-12-12 삼성전자주식회사 반도체 소자
US11101175B2 (en) * 2018-11-21 2021-08-24 International Business Machines Corporation Tall trenches for via chamferless and self forming barrier
US10964792B1 (en) 2019-11-22 2021-03-30 Taiwan Semiconductor Manufacturing Co., Ltd. Dual metal capped via contact structures for semiconductor devices
US11393718B2 (en) * 2020-01-30 2022-07-19 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure and method for forming the same
US12094816B2 (en) * 2021-08-30 2024-09-17 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structure having deep metal line and method for forming the semiconductor structure
US20230268408A1 (en) * 2022-02-22 2023-08-24 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device structure and method for forming the same

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1253376A (zh) * 1998-11-06 2000-05-17 日本电气株式会社 制造半导体器件的方法
US20070099414A1 (en) * 2005-10-31 2007-05-03 Kai Frohberg Semiconductor device comprising a contact structure based on copper and tungsten
US20070290347A1 (en) * 2006-06-19 2007-12-20 Texas Instruments Incorporated Semiconductive device having resist poison aluminum oxide barrier and method of manufacture
US20100270627A1 (en) * 2009-04-22 2010-10-28 Taiwan Semiconductor Manufacturing Company, Ltd. Method for protecting a gate structure during contact formation

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6483142B1 (en) 2001-05-14 2002-11-19 Silicon Integrated Systems Corp. Dual damascene structure having capacitors
JP2003203973A (ja) * 2002-01-08 2003-07-18 Mitsubishi Electric Corp 半導体装置及び半導体装置の製造方法
US20050266679A1 (en) * 2004-05-26 2005-12-01 Jing-Cheng Lin Barrier structure for semiconductor devices
TWI242797B (en) * 2004-06-01 2005-11-01 Nanya Technology Corp Method for forming self-aligned contact of semiconductor device
US7381608B2 (en) * 2004-12-07 2008-06-03 Intel Corporation Method for making a semiconductor device with a high-k gate dielectric and a metal gate electrode
JP2008060243A (ja) * 2006-08-30 2008-03-13 Nec Electronics Corp 半導体装置およびその製造方法
US8120114B2 (en) * 2006-12-27 2012-02-21 Intel Corporation Transistor having an etch stop layer including a metal compound that is selectively formed over a metal gate
US8048790B2 (en) * 2009-09-17 2011-11-01 Globalfoundries Inc. Method for self-aligning a stop layer to a replacement gate for self-aligned contact integration
DE102009046260B4 (de) * 2009-10-30 2020-02-06 GLOBALFOUNDRIES Dresden Module One Ltd. Liability Company & Co. KG Halbleiterbauelement und Verfahren zur Herstellung eines Halbleiterbauelements
US8093117B2 (en) * 2010-01-14 2012-01-10 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming a metal gate
US8728908B2 (en) * 2011-08-08 2014-05-20 Globalfoundries Inc. Methods of forming a dielectric cap layer on a metal gate structure

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1253376A (zh) * 1998-11-06 2000-05-17 日本电气株式会社 制造半导体器件的方法
US20070099414A1 (en) * 2005-10-31 2007-05-03 Kai Frohberg Semiconductor device comprising a contact structure based on copper and tungsten
US20070290347A1 (en) * 2006-06-19 2007-12-20 Texas Instruments Incorporated Semiconductive device having resist poison aluminum oxide barrier and method of manufacture
US20100270627A1 (en) * 2009-04-22 2010-10-28 Taiwan Semiconductor Manufacturing Company, Ltd. Method for protecting a gate structure during contact formation

Cited By (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105336724B (zh) * 2014-07-18 2018-10-23 中芯国际集成电路制造(上海)有限公司 半导体器件
CN105336724A (zh) * 2014-07-18 2016-02-17 中芯国际集成电路制造(上海)有限公司 半导体器件
CN106206690A (zh) * 2014-12-19 2016-12-07 台湾积体电路制造股份有限公司 具有互连结构的半导体器件及其形成方法
CN106206690B (zh) * 2014-12-19 2020-04-17 台湾积体电路制造股份有限公司 具有互连结构的半导体器件及其形成方法
CN107452712A (zh) * 2016-05-31 2017-12-08 台湾积体电路制造股份有限公司 半导体结构
CN107452712B (zh) * 2016-05-31 2021-07-27 台湾积体电路制造股份有限公司 半导体结构
CN108695319A (zh) * 2017-04-10 2018-10-23 三星电子株式会社 具有异质接触件的集成电路
CN108695319B (zh) * 2017-04-10 2023-11-14 三星电子株式会社 具有异质接触件的集成电路
US10985061B2 (en) 2017-04-20 2021-04-20 Taiwan Semiconductor Manufacturing Company, Ltd. Methods for forming contact plugs with reduced corrosion
US12068197B2 (en) 2017-04-20 2024-08-20 Taiwan Semiconductor Manufacturing Company, Ltd. Methods for forming contact plugs with reduced corrosion
US10825727B2 (en) 2017-04-28 2020-11-03 Taiwan Semiconductor Manufacturing Company, Ltd. Metal gates of transistors having reduced resistivity
CN108807160B (zh) * 2017-04-28 2021-03-16 台湾积体电路制造股份有限公司 半导体器件及其形成方法
US11430694B2 (en) 2017-04-28 2022-08-30 Taiwan Semiconductor Manufacturing Company, Ltd. Metal gates of transistors having reduced resistivity
US11810819B2 (en) 2017-04-28 2023-11-07 Taiwan Semiconductor Manufacturing Company, Ltd. Metal gates of transistors having reduced resistivity
CN108807160A (zh) * 2017-04-28 2018-11-13 台湾积体电路制造股份有限公司 具有减小的电阻率的晶体管的金属栅极
CN110379710A (zh) * 2019-07-25 2019-10-25 上海华力集成电路制造有限公司 金属栅极的制造方法及半导体器件
CN113629136A (zh) * 2020-05-06 2021-11-09 中芯国际集成电路制造(北京)有限公司 半导体结构及其形成方法
CN113629136B (zh) * 2020-05-06 2024-02-27 中芯国际集成电路制造(北京)有限公司 半导体结构及其形成方法

Also Published As

Publication number Publication date
US10700010B2 (en) 2020-06-30
TW201405751A (zh) 2014-02-01
US9136206B2 (en) 2015-09-15
US20160064517A1 (en) 2016-03-03
US9614052B2 (en) 2017-04-04
US20170207167A1 (en) 2017-07-20
TWI557864B (zh) 2016-11-11
US20140027822A1 (en) 2014-01-30
CN103579175B (zh) 2017-05-03
US11251131B2 (en) 2022-02-15
US20200321279A1 (en) 2020-10-08

Similar Documents

Publication Publication Date Title
CN103579175A (zh) 具有阻挡层的铜接触插塞
JP5754825B2 (ja) 改善された信頼性のためにフローティング導電性プレートを備える３ｄビア・コンデンサ
JP2022140451A (ja) 半導体デバイスの空隙スペーサを形成する方法および半導体デバイス
EP2345069B1 (en) Method of manufacturing a biocompatible electrode
US8125049B2 (en) MIM capacitor structure in FEOL and related method
TWI515827B (zh) 可靠度提升的內連線結構及其形成方法
CN104425715A (zh) 可变电阻存储器结构及其形成方法
CN103715353B (zh) 可变电阻存储结构及其形成方法
CN112786527B (zh) 半导体结构及其制造方法
CN103811656A (zh) 可变电阻存储结构及其形成方法
US20120100689A1 (en) Mim capacitor and associated production method
JP5799504B2 (ja) 半導体装置及びその製造方法
US20050266679A1 (en) Barrier structure for semiconductor devices
US7745280B2 (en) Metal-insulator-metal capacitor structure
US20120193755A1 (en) Copper-based metallization system including an aluminum-based terminal layer
US20200058593A1 (en) Replacement metal cap by an exchange reaction
US11764145B2 (en) Wiring structure having double capping structure, manufacturing method thereof, and integrated circuit chip having the same
US20170125341A1 (en) Integrated circuit structure and method of forming the same
EP3817038A1 (en) A method for producing self-aligned gate and source/drain via connections for contacting a fet transistor
KR20210076831A (ko) 2d 반데르발스 재료를 사용하여 3d 트랜지스터를 형성하는 방법
CN115706081A (zh) 半导体结构及其制作方法
TW200822291A (en) Damascene metal-insulator-metal (MIM) device with improved scaleability
JP2005175328A (ja) 半導体装置及びその製造方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20170503