TWI557864B - 銅接觸插塞裝置及其形成方法 - Google Patents

銅接觸插塞裝置及其形成方法 Download PDF

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TWI557864B
TWI557864B TW102121681A TW102121681A TWI557864B TW I557864 B TWI557864 B TW I557864B TW 102121681 A TW102121681 A TW 102121681A TW 102121681 A TW102121681 A TW 102121681A TW I557864 B TWI557864 B TW I557864B
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layer
aluminum
copper
contact
sidewall
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TW201405751A (zh
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蘇莉玲
謝靜華
陳煌明
曹學文
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台灣積體電路製造股份有限公司
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Description

銅接觸插塞裝置及其形成方法
本發明係有關於銅接觸插塞，且特別是有關於一種具有阻障層的銅接觸插塞。
半導體製程持續地進步，使得最小元件尺寸下降及製程微縮化。隨著半導體製程節點演進至更小的最小元件尺寸，例如，28奈米、22奈米、以及更小，裝置元件上之接觸插塞可用的面積也隨之下降，其中裝置元件例如：閘極及個別的基板。此外，隨著半導體製程材料的演進，使用先進材料對接觸電阻也產生了額外的衝擊。因此，已著手研究用以降低個別衝擊之方法。
接觸插塞已用來形成導電層例如第一層金屬(亦稱為M1)與其下之基板區域或閘極區域間的垂直電連接。常用的接觸插塞包括鎢插塞。
根據一些實施例，本發明提供一種裝置，其包括一導電層，此導電層包括：一底部及位於底部上方之一側壁部分，其中側壁部分與底部之一端連接；一含鋁層，與導電層之底部重疊，其中含鋁層之一頂表面大致上與導電層之側壁部分之一頂邊緣齊平；一氧化鋁層，位於含鋁層之上；一含銅區域， 位於氧化鋁層上方，並藉由氧化鋁層與含鋁層隔離；含銅區域透過導電層之側壁部分之頂邊緣與含鋁層電耦合。
根據另一些實施例，本發明提供一種裝置，其包括一潤濕層，此潤濕層包括：一第一底部以及一第一側壁部分，位於第一底部上方，並與第一底部之一端連接；一含鋁層，與第一底部重疊，其中含鋁層之一側壁與潤濕層之第一側壁部分接觸；一阻障層，其包括一第二底部，位於含鋁層上方，並與其接觸，以及一第二側壁部分，位於第二底部上方，並與第二底部之一端連接；一含銅區域，與潤濕層之第二底部重疊，並與阻障層之第二側壁部分齊平；潤濕層與阻障層中至少一層包括一實質上的純鈦層。
又根據其他實施例，本發明提供一種方法，其包括形成一導電層，此導電層包括一底部及位於底部上方之一側壁部分，其中側壁部分與底部之一端連接；形成一含鋁層，位於導電層之底部上方，其中一氧化鋁層形成於含鋁層之一頂表面上；形成一介電層，位於含鋁層上方；接著形成一開口，位於介電層中以露出導電層之一側壁部分之一頂邊緣及氧化鋁層之一部分；以一阻障層及位於阻障層上方之一含銅材料填充開口；移除阻障層及含銅材料之多餘部份，阻障層之一部分及含銅材料之一部分留在開口中以形成一接觸插塞，且其中阻障層包括一第一底表面，與氧化鋁層之一頂表面接觸，及一第二底表面，與導電層之一頂邊緣接觸。
為讓本發明之上述和其他目的、特徵、和優點能更明顯易懂，下文特舉出較佳實施例，並配合所附圖式，作詳 細說明如下：
10‧‧‧晶圓
20‧‧‧基板
22‧‧‧源極及汲極區域
24‧‧‧層間介電層(ILD0)
26‧‧‧虛設閘極結構
28‧‧‧虛設閘極電極
30‧‧‧虛設間隔物
32‧‧‧虛設閘極介電質
34‧‧‧開口
36‧‧‧閘極介電層
38‧‧‧導電層
40‧‧‧潤濕層
42‧‧‧含鋁層
44‧‧‧閘極電極(層)
45‧‧‧閘極結構(閘極堆疊)
46‧‧‧氧化鋁層
48‧‧‧接觸插塞(M0_OD1s)
48A‧‧‧附著/阻障層
48B‧‧‧鎢插塞
50‧‧‧矽化區域
52、59‧‧‧蝕刻停止層
54‧‧‧層間介電層(ILD1)
56‧‧‧閘極接觸插塞
56A、58A‧‧‧阻障層
56B、58B‧‧‧含銅區域
58‧‧‧源/汲極接觸插塞(M0_OD2)
60‧‧‧介電層
62‧‧‧M0導孔
64‧‧‧金屬線路
70、72‧‧‧開口
M1‧‧‧金屬層
W1‧‧‧尺寸
第1-6、7A-7C、8圖為根據本發明一些實施例顯示金氧半(Metal-oxide-Semiconductor；MOS)裝置及其上方構造於中間製程之一系列剖面圖及俯視圖。
第9、10A-10C、11圖為根據本發明另一些實施例顯示金氧半(Metal-oxide-Semiconductor；MOS)裝置及其上方構造於中間製程之一系列剖面圖及俯視圖。
以下將詳述本發明實施例之製造與使用。應了解的是，該些實施例提供許多可用之發明慨念可廣泛地應用在各種特定範疇。該特定的實施例僅是用來範例性的說明特定實施例之製造與使用，並非用以限定本發明。
根據各個實施例，本發明提供一種金氧半(Metal-Oxide-Semiconductor；MOS)裝置，其包括含鋁閘極電極、含銅接觸插塞及其製造方法。同時說明金氧半(MOS)裝置製程之中間階段並揭露各個實施例的變化及其操作。在各種視圖及實施例中，其中類似的元件利用類似的數字表示。在所示的實施例中，採用後閘極(gate-last)製程形成含鋁閘極電極。然而，根據其他實施例，含鋁閘極電極也可藉由前閘極(gate-first)製程形成。
第1圖到第8圖為根據本發明一些實施例顯示金氧半(MOS)裝置及其下方構造於中間製程之一系列剖面圖及俯 視圖。請參照第1圖，本發明提供一晶圓10，其包括以半導體材料像是矽、鍺化矽、碳化矽、Ⅲ~V族化合物半導體材料、或其他類似的材料所形成之基板20。基板20可為一塊材基板或一絕緣體上覆半導體(Semiconductor-On-Insulator；SOI)基板。源極及汲極區域(此後也稱為源/汲極區域)22形成於基板20之中。層間介電層(Inter-Layer Dielectric；ILD)(此後稱為ILD0)24形成於基板20上方。ILD0 24可由氧化物像是磷-矽玻璃(Phospho-Silicate Glass；PSD)、硼-矽玻璃(Boro-Silicate Glass；BSG)、硼摻雜磷-矽玻璃(Boron-Doped Phospho-Silicate Glass；BPSG)、四乙氧基矽烷(Tetra Ethyl Ortho Silicate；TEOS)氧化物、或其他類似的材料形成。
虛設閘極結構26形成於ILD0 24之中。虛設閘極結構26包括可利用像是多晶矽或其他材料形成之虛設閘極電極28。在一些實施例中，虛設閘極結構26更包括虛設間隔物30及/或虛設閘極介電質32。在其他實施例中，並未形成虛設間隔物30及/或虛設閘極介電質32。虛設閘極結構26之頂表面與ILD0 24之頂表面齊平。
請參照第2圖，透過蝕刻將虛設閘極結構26移除，進而在ILD0 24之中形成開口34。因此，在一些實施例中，基板20之頂表面透過開口34而露出。請參照第3圖，接著進行閘極介電層36(為一介電層)之沉積。閘極電極層44為一導電層，進一步沉積在閘極介電層36之上。每一層閘極介電層36及閘極電極層44包括一部分覆蓋ILD0 24及一部分位於開口34中(第2圖)。在一些實施例中，閘極介電層36及閘極 電極層44為順應層(conformal layers)，其個別的水平部分與垂直部分大致上具有相同的厚度。
閘極介電層36可為一單層或一包括多層結構的組合層。例如，閘極介電層36可包括一氧化層及位於氧化層上之一高介電常數(high-k)介電層。氧化層可為一經沉積而形成之氧化矽層。高介電常數(high-k)介電層可包括氧化鉿、氧化鋯、或其他類似的材料。在一些實施例中，由氮化鈦形成之阻障層(未顯示)可例如形成於高介電常數(high-k)介電層上方。
在一些實施例中，閘極電極層44包括導電層38、位於導電層38上方的潤濕層40、及位於潤濕層40上方的含鋁層42。導電層38可包括多晶矽、TaSiN、WN、TiAlN、TaC、或其他類似的材料。在其他實施例中，閘極電極層44包括位於導電層38上方的潤濕層40及位於潤濕層40上方的含鋁層42。然而，在這些實施例中並未形成導電層38。導電層38的厚度可介於約1奈米到10奈米，此厚度也可更大或更小。含鋁層42、潤濕層40、及導電層38可包括物理氣相沉積(Physical Vapor Deposition；PVD)、金屬有機化學氣相沉積(Metal-Organic Chemical Vapor Deposition；MOCVD)、及/或其他可使用的方法，取決於導電層38、潤濕層40、及含鋁層42所使用的材料。
在一些實施例中，含鋁層42具有一大於約90%或大於約95%的鋁原子比例。應了解的是，說明書中所提及的數值僅為舉例，可更改成不同的數值。在開口34(第2圖)中的含鋁層42部分可具有一側向尺寸W1，其介於例如約25 奈米到1微米。潤濕層40為用以提高含鋁層42及導電層38之間的附著性，其厚度可介於例如約1奈米到10奈米。潤濕層40可具有一大於約60%的鈦原子比例。潤濕層40也可包括一實質上的(substantially)純鈦層，其具有例如一大於約95%的鈦原子比例。實質上的純鈦層(如有的話)，可與上方的含鋁層42物理性接觸。純鈦層有助於避免含鋁層42及上方的含銅區域56B(第7A圖)中的鋁原子及銅原子之間的交互擴散(inter-diffusion)。其原因在於鈦原子與上方的含鋁層42之間形成良好的鍵結，使得含鋁層42中已鍵結的鋁原子更難以向上遷移到含銅區域56B中。在其他實施例中，潤濕層40為一單層或一複合層，此複合層包括鈦(Ti)、氮化鈦(TiN)、鉭(Ta)、氮化鉭(TaN)、及/或其他類似的材料。
請參照第4圖，利用一平坦化像是化學機械平坦化(Chemical Mechanical Polish；CMP)來移除閘極介電層36及閘極電極層44位於ILD0 24上的多餘部分。所形成的結構包括置換閘極堆疊(replacement gate stack)45。閘極介電層36及閘極電極層44之剩餘部分此後稱為閘極介電質36及閘極電極44。在所示的實施例中，每一個閘極介電質36、導電層38、及潤濕層40包括一底部及一側壁部分，此側壁部分位於底部的另一端上方並與其連接。進行化學機械平坦化(CMP)之後，氧化鋁層46可形成於含鋁層42的頂表面上，並與其接觸。
第5圖顯示下(lower)源/汲極接觸插塞48(此後也稱為M0_OD1 48)的形成，其中“OD”表示接觸插塞48與一主動區域連接。以下簡易的討論一形成製程之實施例。形成製程 可包括蝕刻ILD0 24以形成開口(被接觸插塞48佔據)，以露出源極及汲極區域22。透過此開口執行一自對準矽化(self-aligned silicidation)以形成矽化區域50於開口底部。將導電材料填入開口，並接著進行一化學機械平坦化(CMP)步驟以移除多餘的導電材料。導電材料的剩餘部份形成接觸插塞48。在一些實施例中，M0_OD1s 48包括附著/阻障層48A及位於附著/阻障層48A上的鎢插塞48B。附著/阻障層48A可包括鈦、氮化鈦、鉭、氮化鉭、前述之組合、或前述材料之多層結構。鎢插塞48B可例如由鎢或鎢合金形成。
請參照第6圖，蝕刻停止層52形成於閘極結構45及ILD0 24之頂表面上，並可與其物理性接觸。在一些實施例中，蝕刻停止層52由氮化矽形成，或可由其他介電材料例如碳化矽、氮氧化矽、或其他類似的材料形成。在蝕刻停止層52形成後，另一層間介電層(ILD)稱為ILD1 54便形成於蝕刻停止層52上方。ILD1 54可由磷矽酸鹽玻璃(PSG)、硼矽酸鹽玻璃(BSG)、硼磷矽玻璃(BPSG)、四乙氧化矽烷(TEOS oxide)、或其他類似的材料形成。
第7圖顯示閘極接觸插塞56與源/汲極接觸插塞58的形成，這兩者可同步形成或是於不同的製程階段中形成。源/汲極接觸插塞58此後也稱為M0_OD2或上(upper)源/汲極接觸插塞。源/汲極接觸插塞58與各自底下的下(lower)源/汲極接觸插塞M0_OD1s 48對準並接觸。閘極接觸插塞56與閘極電極44電耦合。每一個閘極接觸插塞56及M0_OD2s 58包括一阻障層，也稱為56A或58A；以及一含銅區域，其可稱為 56B或58B。形成製程可包括對ILD1 54及蝕刻停止層52進行蝕刻以形成開口，以及利用阻障層與含銅層填充開口。接著，進行化學機械平坦化(CMP)以移除阻障層及含銅層的多餘部分。阻障層的剩餘部分形成阻障層56A及58A，而含銅層的剩餘部分則形成含銅區域56B及58B。
在一些實施例中，阻障層56A包括一層，其包括一鈦(Ti)層、一氮化鈦(TiN)層、一鉭(Ta)層、一氮化鉭(TaN)層、或前述材料之多層結構。當阻障層56A(或58A)包括一實質上的純鈦層，此實質上的純鈦層可與含銅區域56B(或58B)的底表面及其側壁物理性接觸，或是不與其接觸。實質上的純鈦層位於含銅區域56B與含鋁層42之間，並因此形成一良好的屏障，可用以避免含銅區域56B中的銅及含鋁層42中的鋁擴散至對方的區域中。阻障層56A之厚度可介於例如約2奈米到20奈米之間。含銅區域56B及58B之銅原子比例可大於約80%，或約100%。
閘極接觸插塞56(及其各自之阻障層56A)包括與導電層38或潤濕層40的頂邊緣接觸之一部分。在一些實施例中，當開口(閘極接觸插塞56填入的地方)露出後，氧化鋁層46露出的部分不會被蝕刻。從而，閘極接觸插塞56(及其各自阻障層56A)可更包括一部分位於不導電的氧化鋁層46的頂表面上方，並與其接觸。因此，閘極電極44與閘極接觸插塞56之間的電耦合穿過導電層38及/或潤濕層40的頂邊緣，但不穿過含鋁層42的頂表面。
第7B圖及第7C圖顯示第7A圖一些實施例中之結 構俯式圖。請參照第7B圖，閘極接觸插塞56可與氧化鋁層46的中央錯位(misaligned)。取而代之的是，閘極接觸插塞56與閘極電極44的一邊對齊以與導電層38及/或潤濕層40的頂邊緣接觸。第7C圖顯示兩個閘極接觸插塞56與同一個閘極電極44電耦合，其中一個閘極接觸插塞56比閘極電極44寬，因此，此閘極接觸插塞56可與位於氧化鋁層46相反邊的導電層38/潤濕層40的一部分接觸。另一個閘極接觸插塞56也可與氧化鋁層46錯位以接觸導電層38/潤濕層40。
請參照第8圖，在後續的製程中，蝕刻停止層59、M0導孔62、及導線64皆形成於金屬層M1的底部之中。M0導孔62及導線64形成於介電層60之中，其中介電層60可由一低介電常數(low-k)介電材料形成，其具有一小於例如約3.0或小於例如約2.5的介電常數(k)數值。在一些實施例中，可利用一雙鑲嵌(dual-damascene)製程形成M0導孔62及導線64，因此在M0導孔62及其各自其上的導線64之間沒有明顯的界面存在。在另一些實施例中，可利用一單鑲嵌(single-damascene)製程形成M0導孔62及導線。又在另一些實施例中，M0導孔62未被形成而導線64與接觸插塞56及58接觸。M0導孔62及導線64可包括一擴散阻障層及一位於擴散阻障層上之含銅材料。在後續的製程中，更多金屬層(未顯示)可形成於金屬層M1上方。
第9圖到第11圖為根據其他實施例顯示金氧半(MOS)裝置及其底下的結構於中間製程之剖面圖。除非特別提及，在這些實施例中，類似的元件所使用的材料及其形成方法 相同，並以如第1圖到第8圖實施例中類似的參考數字表示。因此，在第9圖到第11圖中元件之形成製程及材料相關的細節，可在第1圖到第8圖實施例之討論中找到。
在這些實施例中，其起始步驟與第1圖到第6圖中所示相同。接下來，如第9圖所示，進行ILD1 54及其底下的蝕刻停止層52的蝕刻以形成開口70及72。當氧化鋁層46形成後，進行透過開口70而露出的部分氧化鋁層46的蝕刻，並於開口70露出其底下的含鋁層42。接著，如第10A圖所示，閘極接觸插塞56及M0_OD2s 58各自於開口70及72中形成。閘極接觸插塞56(及阻障層56A)與含鋁層42接觸並穿過氧化鋁層46。第10B圖及第10C圖顯示第10A圖中所顯示結構之各自的俯視圖。如第10B圖所示，閘極接觸插塞56可與氧化鋁層46對準或錯位(misaligned)。當閘極接觸插塞56與氧化鋁層46錯位時，阻障層56A的底表面可與導電層38及潤濕層40的頂邊緣接觸。如第10C圖所示，閘極接觸插塞56也可比含鋁層42更寬，而因此可與含鋁層42的頂表面及導電層38與潤濕層40的頂邊緣接觸。第11圖顯示金屬層M1形成後之結構。
於第8圖及第11圖之實施例中，阻障層56A與潤濕層40兩者之一包括一鈦層(根據一些實施例，此鈦層實質上純)。當潤濕層40包括鈦層，此鈦層可與含鋁層42之底表面及其側壁接觸。在其他實施例中，鈦層形成於阻障層56A及潤濕層40之中。鈦層有助於減少含銅區域56B中的銅及含鋁層42中的鋁之間的相互擴散(inter-diffusion)。此外，在第8圖所 示之實施例中，氧化鋁層46也有助於減少交互擴散(inter-diffusion)。
儘管在一些實施例中，含鋁閘極電極與含銅接觸插塞被用來當做範例以解釋實施例的概念，實施例的概念可應用於減少其他含鋁區域與含銅區域之間的相互擴散(inter-diffusion)，包括但不限於例如含鋁金屬墊及其上的含銅後鈍化內連接(Post-Passivation Interconnect；PPI)結構。在這些實施例中，含鋁金屬墊及含銅後鈍化內連接(PPI)結構形成於所有的低介電常數(low-k)層上方，且其中含銅後鈍化內連線(PPI)結構更形成於鈍化層(passivation layer)上方。
雖然本發明已以數個較佳實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作任意之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
10‧‧‧晶圓
20‧‧‧基板
22‧‧‧源極及汲極區域
24‧‧‧層間介電層(ILD0)
36‧‧‧閘極介電層
38‧‧‧導電層
40‧‧‧潤濕層
42‧‧‧含鋁層
46‧‧‧氧化鋁層
48‧‧‧接觸插塞(M0_OD1s)
50‧‧‧矽化區域
52、59‧‧‧蝕刻停止層
54‧‧‧層間介電層(ILD1)
56‧‧‧閘極接觸插塞
56A、58A‧‧‧阻障層
56B、58B‧‧‧含銅區域
58‧‧‧源/汲極接觸插塞(M0_OD2)
60‧‧‧介電層
62‧‧‧M0導孔
64‧‧‧金屬線路
M1‧‧‧金屬層

Claims (10)

  1. 一種銅接觸插塞裝置，包括：一導電層，包括一底部，及位於該底部上方之一側壁部分，其中該側壁部分與該底部之一端連接；一含鋁層，與該導電層之該底部重疊；一氧化鋁層，位於該含鋁層之上，其中該氧化鋁層之一頂表面大致上與該導電層之該側壁部分之一頂邊緣齊平；以及一含銅區域，位於該氧化鋁層上方，並藉由該氧化鋁層與該含鋁層隔離，其中該含銅區域透過該導電層之該側壁部分之該頂邊緣與該含鋁層電耦合。
  2. 如申請專利範圍第1項所述之銅接觸插塞裝置，尚包括一潤濕層，該潤濕層包括：一底部，位於該含鋁層之該底部之下並與其接觸；以及一側壁部分，位於該含鋁層之一側壁部分與該導電層之該側壁部分之間，並與其接觸。
  3. 如申請專利範圍第2項所述之銅接觸插塞裝置，其中該潤濕層包括一實質上的純鈦層，與該含鋁層接觸。
  4. 如申請專利範圍第1項所述之銅接觸插塞裝置，尚包括一阻障層，該阻障層包括：一底部，位於該含銅區域之該底部之下，其中該底部包括一第一底表面，與該導電層之該側壁部分之該頂邊緣接觸；以及一側壁部分，與該含銅區域之一側壁接觸。
  5. 如申請專利範圍第4項所述之銅接觸插塞裝置，其中該阻障層之該底部尚包括一第二底表面，與該氧化鋁層之一頂表面接觸。
  6. 如申請專利範圍第4項所述之銅接觸插塞裝置，其中該阻障層包括一實質上的純鈦層。
  7. 一種銅接觸插塞裝置，包括：一潤濕層，包括：一第一底部；一第一側壁部分，位於該第一底部上方，並與該第一底部之一端連接；一含鋁層，與該第一底部重疊，其中該含鋁層之一側壁與該潤濕層之該第一側壁部分接觸，其中該潤濕層的該第一側壁部分之一頂邊緣高於該含鋁層之一頂表面；一氧化鋁層，位於該含鋁層之上；以及一阻障層，包括：一第二底部，位於該含鋁層上方，並與其接觸；一第二側壁部分，位於該第二底部上方，並與該第二底部之一端連接；以及一含銅區域，與該潤濕層之該第二底部重疊，並與該阻障層之該第二側壁部分齊平，其中該潤濕層與該阻障層中至少一層包括一實質上的純鈦層，其中該含銅區域位於該氧化鋁層上方，並藉由該氧化鋁層與該含鋁層隔離。
  8. 一種銅接觸插塞裝置的形成方法，包括：形成一導電層，包括一底部，及位於該底部上方之一側壁 部分，其中該側壁部分與該底部之一端連接；形成一含鋁層，位於該導電層之該底部上方，其中一氧化鋁層形成於該含鋁層之一頂表面上，且該氧化鋁層之一頂表面大致上與該導電層之該側壁部分之一頂邊緣齊平；形成一介電層，位於該含鋁層上方；形成一開口，位於該介電層中以露出該導電層之一側壁部分之一頂邊緣及該氧化鋁層之一部分；以一阻障層及位於該阻障層上方之一含銅材料填充該開口；以及移除該阻障層及該含銅材料之多餘部份，其中該阻障層之一部分及該含銅材料之一部分留在該開口中以形成一接觸插塞，且其中該阻障層包括一第一底表面，與該氧化鋁層之一頂表面接觸，及一第二底表面，與該導電層之一頂邊緣接觸。
  9. 如申請專利範圍第8項所述之銅接觸插塞裝置的形成方法，其中形成該阻障層之步驟包括沉積一實質上的純鈦層。
  10. 如申請專利範圍第8項所述之銅接觸插塞裝置的形成方法，尚包括：在形成該導電層之步驟後及形成該含鋁層之步驟前，沉積一實質上的純鈦層，其中該含鋁層與該實質上的純鈦層接觸。
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