CN109427775A - 集成电路及其形成方法 - Google Patents

集成电路及其形成方法 Download PDF

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Publication number
CN109427775A
CN109427775A CN201711276307.4A CN201711276307A CN109427775A CN 109427775 A CN109427775 A CN 109427775A CN 201711276307 A CN201711276307 A CN 201711276307A CN 109427775 A CN109427775 A CN 109427775A
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integrated circuit
source
gate electrode
track
buried
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CN109427775B (zh
Inventor
王柏钧
江庭玮
赖志明
庄惠中
杨荣展
刘如淦
张世明
周雅琪
林义雄
黄禹轩
张玉容
吴国晖
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本申请的实施例提供了一种集成电路，包括半导体衬底、延伸到半导体衬底中的并且在半导体衬底的块状部分上面的隔离区、包括在隔离区中的部分的掩埋导电轨道、以及具有源极/漏极区和栅电极的晶体管。源极/漏极区或栅电极连接到掩埋导电轨道。本申请的实施例还提供了另一种集成电路以及形成集成电路的方法。

Description

集成电路及其形成方法
技术领域
本申请涉及半导体领域，并且更具体地，涉及集成电路及其形成方法。
背景技术
现代集成电路由在半导体衬底上形成的晶体管、电容器、和其它器件 组成。在衬底上，这些器件彼此最初隔离，但是后来互连在一起以形成功 能电路。典型的互连结构包括诸如金属线(引线)的横向互连件以及诸如 通孔和接触件的竖直互连件。互连结构的质量影响制造的电路的性能和可 靠性。互连件越来越多地确定了现代集成电路的性能和密度的极限。
互连结构可以包括钨插塞和铝线。在新一代集成电路中，还使用了双 镶嵌结构以形成互连结构，其中该双镶嵌结构包括使用双镶嵌工艺形成的 铜线和通孔。
发明内容
根据本申请的实施例，提供了一种集成电路，包括：半导体衬底；隔 离区，延伸到半导体衬底中并且在半导体衬底的块状部分上面；掩埋导电 轨道，包括在隔离区中的一部分；以及晶体管，包括源极/漏极区和栅电极， 其中，源极/漏极区或栅电极连接到掩埋导电轨道。
根据本申请的实施例，提供了一种集成电路，包括：半导体衬底，半 导体衬底包括块状部分；介电层，介电层包括：底部部分，底部部分具有 接触半导体衬底的块状部分的顶面的底面；以及在底部部分上方的侧壁部 分，其中，侧壁部分连接到底部部分的相对端；掩埋金属轨道，位于介电 层的底部部分上方并且在介电层的侧壁部分之间；以及介电帽，位于掩埋 金属轨道的顶面上面并且接触掩埋金属轨道的顶面。
根据本申请的实施例，提供了一种形成集成电路的方法，包括：蚀刻 半导体衬底以形成第一沟槽；将金属轨道填充到第一沟槽中；形成覆盖金 属轨道的介电帽；以及形成与金属轨道邻近的晶体管，其中，晶体管包括： 源极/漏极区；源极/漏极接触插塞；以及栅电极，其中，金属轨道包括被源 极/漏极接触插塞和栅电极中的一个重叠的部分。
附图说明
当结合附图进行阅读时，根据下面详细的描述可以最佳地理解本发明 的方面。应该强调的是，根据工业中的标准实践，各个部件未按比例绘制。 实际上，为了清楚的讨论，各种部件的尺寸可以被任意增加或减少。
图1示出了根据一些实施例的包括掩埋金属轨道的集成电路的一部分 的顶视图。
图2A至图23C示出了根据一些实施例的形成管芯堆叠件的中间阶段 的横截面图。
图24示出了根据一些实施例的用于形成包括掩埋金属轨道的集成电 路的工艺流程。
具体实施方式
以下公开内容提供了许多不同实施例或实例，用于实现本发明的不同 特征。以下描述组件和布置的具体实例以简化本发明。当然，这些仅仅是 实例而不旨在限制。例如，在以下描述中，在第二部件上方或上形成第一 部件可以包括第一部件和第二部件直接接触的实施例，也可以包括形成在 第一部件和第二部件之间的附加部件使得第一部件和第二部件不直接接触 的实施例。而且，本发明在各个实例中可以重复参考数字和/或字母。这种重复仅是为了简明和清楚，其自身并不表示所论述的各个实施例和/或配置 之间的关系。
而且，为了便于描述，在此可以使用诸如“在...下面”、“在...下方”、“下 部”、“在...上面”、“上部”等空间相对术语以描述如图所示的一个元件或部 件与另一个(或另一些)元件或部件的关系。除了图中所示的方位外，空 间相对位置术语旨在包括器件在使用或操作中的不同方位。装置可以以其 他方式定位(旋转90度或在其他方位)，并且在本文中使用的空间关系描 述符可以同样地作相应地解释。
根据各种示例性实施例提供一种掩埋导电轨道(track)(其可以是金 属轨道)及其形成方法。根据一些实施例，示出了形成掩埋金属轨道的中 间阶段。讨论了一些实施例的一些变化。贯穿各个视图和说明性实施例， 相同的参考标号用于指定相同的元件。
图1示出了集成电路100的一部分的顶视图。根据本公开的一些实施 例，集成电路100的所示部分是标准单元的一部分，其被预先设计并保存 在数据库中。在设计电路时，预先设计的标准单元被复制以形成更大电路 的一部分。然后在制造更大的电路时，在物理晶圆上制造作为更大设计的 一部分的标准单元。虚线示意性地示出标准单元的边界。根据本公开的可 选实施例，在设计时，布局集成电路100而不是标准单元并且被复制。
根据本公开的一些实施例，集成电路100包括一个或多个有源区102A 和有源区102B，它们被共同且单独地称为有源区102。有源区102可以是 半导体鳍，或者可以是平坦的有源区。在半导体鳍102上方形成多个栅极 结构108以形成多个晶体管115。当有源区102是半导体鳍时，基于半导 体鳍形成的所得到的晶体管是鳍式场效应晶体管(FinFET)。当有源区是 平坦的有源区时，晶体管也可以是平坦的晶体管。贯穿说明书，以FinFET 为例进行了讨论。应当理解，本公开的概念，诸如金属轨道及其用途，也 可以与平坦的晶体管一起使用。导电轨道112可以形成在半导体鳍102之 间，并且可以具有平行于半导体鳍102的长度方向的长度方向。导电轨道 112可以是金属轨道，并且因此在整个描述中可选地被称为金属轨道112， 而其也可以由诸如掺杂的多晶硅的其它导电材料形成。
栅极结构108包括栅极堆叠件104和在相应的栅极堆叠件104的相对 两侧上的栅极间隔件106。栅极堆叠件104还包括栅极电介质和栅电极(未 单独地示出)，这将在后续段落中讨论。
根据本公开的一些实施例，半导体鳍102是较长的鳍，多个栅极结构 108跨越半导体鳍以形成多个晶体管。一些晶体管可以共享共同的源极区 和/或共同的漏极区，并且将晶体管组合用作单个晶体管。例如，在所示的 示例性电路中，四个栅极结构108可以跨越半导体鳍102A以形成四个晶体 管，其可并联连接(共享共用的源极/漏极区)以形成一个晶体管。根据可 选实施例，较长的鳍可以被切割成较短的鳍，并且基于较短的鳍形成的所 示出的晶体管中的一些或全部是分立的晶体管。例如，当鳍102(诸如102A 和/或102B)在区110处被切开时，将存在两个半导体鳍102A和两个半导 体鳍102B，每个半导体鳍用于形成晶体管或多个晶体管。
在半导体鳍102之间可以形成金属轨道112。集成电路100还可以包 括在晶体管上方的金属层中形成的金属线114(包括114A和114B)。金 属轨道112和金属线组合地执行用于互连集成电路的功能。虽然未示出， 可以在与金属线114A和114B相同的层上存在附加的金属线，并且根据一 些实施例，附加的金属线可以与金属轨道112重叠。根据一些实施例，金 属轨道112具有平行于金属线114A和金属线114B的长度方向的长度方向。
根据本公开的一些实施例，集成电路100包括基于半导体鳍102外延 生长的外延半导体区116，和用于连接至源极/漏极接触插塞的源极/漏极接 触插塞71。导电通孔120用于连接源极/漏极接触插塞71中的一个至掩埋 金属轨道112。导电通孔122用于连接栅极堆叠件104中的一个的栅电极 至掩埋金属轨道112。根据其中鳍102A在区110中被分开的一些实施例， 在区110左侧上的鳍102A的部分将用于形成第一晶体管，并且在区110 右侧上的鳍102A的部分将用于形成与第一晶体管分立的第二晶体管。因 此，所示的金属轨道112用于连接第一晶体管的源极/漏极区至第二晶体管 的栅极。根据其中鳍102A(和/或102B)是较长的鳍而不被切开的其他实 施例，基于多个栅极结构108形成的多个晶体管连接作为单个晶体管，并 且金属轨道112执行与用于互连晶体管的栅极和源极/漏极的对接接触件相同的功能。
图2A至图23C示出了根据本公开的一些实施例的形成包括掩埋导电 (金属轨道)的集成电路的一部分的中间阶段的横截面图。图2A至图23C 中示出的步骤也在图24中示出的工艺流程中示意性地反映。图2A至图23C 中的附图标号中的每个可以包括字母“A”、“B”、或“C”。字母“A”表示从与 图1中的包含线A-A的竖直平面相同的平面获得相应的附图。字母“B”表 示从与图1中的包含线B-B的竖直平面相同的平面获得相应的附图。字母 “C”表示从与图1中的包含线C-C的竖直平面相同的平面获得相应的附图。 因此，标号包括字母“A”的附图示出了从晶体管的源极/漏极区获得的横截 面图，并且标号包括字母“B”的附图示出了从栅极堆叠件104中的一个获得 的横截面图，这些将在后面的段落中详细讨论。
图2A和2B示出了作为晶圆的一部分的衬底20的横截面图。衬底20 可以是诸如硅衬底、硅碳衬底、硅锗衬底、绝缘体上硅衬底、或由其它半 导体材料形成的衬底的半导体衬底。衬底20也可以是由诸如III-V族化合 物半导体材料的其它半导体材料形成的。衬底20可轻掺杂有p型或n型杂 质。
通过蚀刻在半导体衬底20中形成沟槽21。相应的步骤被示出为图24 所示的工艺流程中的步骤202。应当理解，如图2A所示的沟槽21和图2B 所示的沟槽21是相同沟槽的不同部分，其可以是宽度大致均匀的纵长沟 槽。例如，如图1所示，沟槽21的顶视图形状与金属轨道112和电介质 22占据的区域的顶视图形状相同。
返回参考图2A和图2B，根据一些实施例，沟槽21的深度D1可以在 约60nm和约80nm之间的范围内。沟槽21的宽度W1可以在约20nm至约 50nm的范围内。应当理解，整个说明书中记载的值是实例，并且可以使用 不同的值。接近图1所示的掩埋金属轨道112的长度L1的沟槽21的长度 可以大于约10μm，并且可以在约500nm和约10μm之间的范围内。
接下来，如图3A和图3B所示，形成延伸至沟槽21中的介电层22。 相应的步骤被示出为图24所示的工艺流程中的步骤204。介电层22可以 由氮化硅、氧化硅、氮氧化硅、碳化硅、碳氮化硅等形成。根据一些实施 例，通过沉积形成介电层22，并且形成方法可以包括原子层沉积(ALD)、 化学汽相沉积(CVD)、低压化学汽相沉积(LPCVD)等。根据可选实施 例，通过使衬底20的表面层反应以产生介电层22来形成介电层22。当通 过反应形成时，衬底20的表面层可以被氧化和/或氮化以形成氧化硅、氮 化硅、或氮氧化硅。介电层22可以是共形层，其水平部分和垂直部分具有 彼此接近的厚度。例如，水平部分的厚度T1(图3A)和竖直部分的厚度T2可以具有小于厚度T1和厚度T2的约20％的差。厚度T1和厚度T2可 以在约3nm和约10nm之间的范围内。
然后，沟槽21用可以是含金属的材料的导电材料填充以形成导电轨道 112，如图4A和图4B所示。相应的步骤被示出为图24所示的工艺流程中 的步骤206。贯穿说明书，导电轨道112可选地被称为金属轨道112。根据 一些实施例，导电材料的填充通过以下方式实现：通过物理汽相沉积(PVD) 沉积晶种层，并且然后执行电镀工艺以在晶种层上沉积金属材料。也可以 通过CVD填充导电材料。根据本公开的一些实施例，导电材料由选自Cu、 Co、W、Ru、Al、Ni、或其合金的金属形成。根据本公开的其它实施例， 导电材料由诸如AlCu、W-TiN、TiSi、NiSi、TiN、TaN等的金属化合物形 成。根据本公开的其它实施例，导电材料包括多晶硅，其可以掺杂有诸如 硼的p型掺杂剂或诸如磷或砷的n型掺杂剂。在填充导电材料之后，执行 诸如化学机械抛光(CMP)或机械研磨的平坦化步骤以去除衬底20的顶面 上方的介电层22和导电材料的部分。
图5A和图5B示出了介电层22和金属轨道112的凹进以形成凹槽26。 相应的步骤被示出为图24所示的工艺流程中的步骤208。可以通过湿蚀刻 或干蚀刻进行凹进。凹进深度D2可以在约30nm和约50nm之间的范围内。 剩余的金属轨道可以具有在约20nm和约40nm之间的高度H1。根据一些 实施例，介电层22的顶面是倾斜的，顶面的更靠近衬底20的外部部分越 来越高于顶面的靠近金属轨道112的相应的内部部分。这可以通过控制诸 如工艺气体流量比、分压、温度等的蚀刻工艺条件类实现。
图6A和图6B以及图7A和图7B示出了用于覆盖金属轨道112的介 电帽28的形成。相应的步骤被示出为图24所示的工艺流程中的步骤210。 参考图6A和图6B，沉积介电材料27。介电材料27可以由选自用于形成 介电层22的相同组的候选材料的介电材料形成。此外，介电材料27和介 电层22可以由相同的介电材料或不同的介电材料形成。介电层27可以完 全填充凹槽26(图5A和图5B)或部分地填充凹槽26。介电层可以被平坦 化。
然后，介电材料27被回蚀刻，并且介电材料27的剩余部分被称为介 电帽28，如图7A和图7B所示。介电帽28和介电层22之间可以具有或不 具有可区分的界面。因此，使用虚线示出介电帽28和介电层22之间的界 面，以指示其可能存在或不存在。根据一些实施例，回蚀刻包括两个倾斜 的干蚀刻工艺以帮助形成倾斜的顶面。倾斜蚀刻由箭头29示出。在每个倾 斜的蚀刻中，施加偏置电压以使从蚀刻气体形成离子以在相对于相应晶圆 的主顶面倾斜的方向上移动。
在图7A和图7B所示的横截面图中，金属轨道112由包括介电层22 和介电帽28的介电材料包围并被掩模在介电材料中。因此，贯穿说明书， 金属轨道112被称为掩埋金属轨道112。
图8A、图8B、图9A、和图9B示出了隔离区和半导体鳍的形成。相 应的步骤被示出为图24所示的工艺流程中的步骤212。参考图8A和图8B， 蚀刻衬底20以形成沟槽30。剩余结构包括半导体带32，其为剩余衬底20 的带状部分。半导体带32在衬底20的块状部分上方。在蚀刻中，介电帽 28和介电层22未被蚀刻，并且因此介电层22的一些部分高于衬底20的 块状部分的顶面。介电层22的底部可以延伸至衬底20中。掩埋金属轨道 112的底表面可以高于、齐平于、或低于衬底20的块状部分的顶面。
在随后的步骤中，如图9A和图9B所示，形成介电区/材料36以填充 如图8A和图8B所示的沟槽30。所示的介电区也被称为隔离区36或浅沟 槽隔离(STI)区36。根据本公开的一些实施例，STI区36包括衬垫氧化 物(未单独地示出)和在衬垫氧化物上方的填充介电材料(未单独地示出)。 衬垫氧化物可以形成为共形层，其水平部分和竖直部分具有彼此接近的厚 度。根据本公开的一些实施例，衬垫氧化物通过在含氧环境中，例如，通 过局部硅氧化(LOCOS)氧化衬底20的暴露的表面层和半导体带32而形 成，其中氧气(O2)可以被包括在相应的工艺气体中。形成填充介电材料 以填充沟槽30的剩余部分。填充介电材料可以由氧化硅、碳化硅、氮化硅、 或其多层形成。填充介电材料的形成方法可以选自可流动化学汽相沉积 (FCVD)、旋涂、CVD、ALD、高密度等离子体化学汽相沉积(HDPCVD)、 和LPCVD。在填充介电材料的沉积之后，执行平坦化步骤以去除衬垫氧化 物和填充介电材料的多余部分。结果，STI区36可以具有略高于半导体带32的顶面的顶面。然后，执行凹进步骤以去除STI区的覆盖介电帽28的 部分，并且所得结构示出在图9A和图9B中。
在所得到的结构中，如图9A和图9B所示，半导体带32的顶部高于 STI区36的顶面，并且被称为半导体鳍102(也在图1中示出)。介电帽 28可以具有在倾斜的顶面的顶端处的尖端，并且顶部尖端也可以突出高于 STI区36的顶面。
接下来，形成伪栅极堆叠件，其中，图10B示出了伪栅极堆叠件44 中的一个。相应的步骤被示出为图24所示的工艺流程中的步骤214。根据 本公开的一些实施例，每个伪栅极堆叠件44包括伪栅极电介质38、伪栅 电极40、和硬掩模42。根据本公开的一些实施例，伪栅极电介质38可以 由氧化硅形成，伪栅电极40可以由多晶硅形成，以及硬掩模42可以由氮化硅形成。伪栅极电介质38、伪栅电极40、和硬掩模42的形成可以包括 将这些层沉积为毯式层，并且在蚀刻步骤中图案化毯式层。如图1所示， 所得到的伪栅极堆叠件44处于与栅极堆叠件104相同的位置，并且具有与 栅极堆叠件104相同的形状和尺寸。如图10B所示，伪栅极堆叠件44跨越 半导体鳍102(也参见图1)。在形成伪栅极堆叠件44之后，在伪栅极堆 叠件44的侧壁上形成栅极间隔件106(在图1中示出)。由于图10A和图 10B所示的横截面图是从图1中的分别包含线A-A和线B-B的竖直平面获 得的，因此伪栅极堆叠件44在图10B中示出，并且不存在于图10A所示 的横截面图中。
图11A示出了根据一些实施例的在半导体鳍102上选择性地生长的外 延半导体区116(也参考图1)的形成。相应的步骤被示出为图24所示的 工艺流程中的步骤216。由于生长是选择性的，所以如图11B所示，半导 体区116不会在伪栅极堆叠件44上生长。在一些示例性实施例中，半导体 区116包括硅锗或硅。取决于产生的FinFET是p型FinFET还是n型FinFET， 随着外延的进行可以原位掺杂p型或n型杂质。例如，当所得到的FinFET 是p型FinFET时，可以生长硅锗硼(SiGeB)。相反地，当所得到的FinFET 是n型FinFET时，可以生长硅磷(SiP)或硅碳磷(SiCP)。根据本公开 的可选实施例，半导体区116由诸如GaAs、InP、GaN、InGaAs、InAlAs、GaSb、AlSb、AlAs、AlP、GaP、其组合、或其多层的III-V族化合物形成。
在外延步骤之后，半导体区116和鳍102可以进一步注入有p型或n 型杂质以增加它们的杂质浓度。根据本公开的可选实施例，当在外延期间 半导体区116原位掺杂有p型或n型杂质时，跳过注入步骤。因此，形成 包括外延半导体区116和鳍102的源极/漏极区46。
根据可选实施例，代替直接从鳍102生长半导体区116，执行蚀刻步 骤(以下称为源极/漏极凹进)以蚀刻鳍102。半导体区116从凹槽生长。
如图11A所示，半导体区116横向和竖直地生长。如图23A所示，如 果过度生长发生，介电帽28的尖端可能抑制相邻半导体区116的过度生长， 并且可能有助于留下足够的空间用于形成通孔120。
参考图12A，形成接触蚀刻停止层(CESL)50和层间电介质(ILD) 52。对应的步骤还示出为图24中所示的工艺流程中的步骤216。根据本公 开的一些实施例，在形成CESL 50之前，在源极和漏极区46上也可以形成 缓冲氧化物层(未示出)。缓冲氧化物层可以由氧化硅形成，并且CESL 50 可以由氮化硅、碳氮化硅等形成。例如，可以使用诸如ALD的共形沉积法形成缓冲氧化物层和CESL 50。ILD 52可以包括使用，例如，FCVD、旋 涂、CVD或另一适用的沉积方法形成的介电材料。ILD 52可以由正硅酸乙 酯(TEOS)氧化物、PECVD氧化物(SiO2)、磷酸硅酸盐玻璃(PSG)、 硼硅酸盐玻璃(BSG)、硼掺杂的磷酸硅酸盐玻璃(BPSG)等形成。可以 执行诸如CMP或机械研磨的平坦化步骤，以使ILD 52(图12A)、伪栅极 堆叠件44(图12B)、以及栅极间隔件106(图1)的顶面彼此齐平。
然后，去除如图12B所示的伪栅极堆叠件44。由此，形成凹槽54(图 13B)。相应的步骤被示出为图24所示的工艺流程中的步骤218。参考图1， 凹槽54(未示出)将位于示出栅极堆叠件104的相同位置处。同时，ILD 52 (图13A)和栅极间隔件106(图1)将保持并且将环绕凹槽54。如图13B 所示，半导体鳍102的部分被露出并暴露于凹槽54中。介电帽28也可能 被露出。
接下来，如图14A和图14B所示，形成(替代)栅极介电层56，其延 伸到凹槽54(图14B)中，并且可以具有在如图14A所示的在ILD 52上 方延伸的部分。相应的步骤被示出为图24所示的工艺流程中的步骤220。 根据本公开的一些实施例，栅极介电层56包括作为其下部的界面层(未单 独示出的IL)。IL形成在半导体鳍102的暴露表面上，并且可以或可以不 在STI区36和介电帽28上延伸。IL可以包括通过半导体鳍102的热氧化、 化学氧化工艺或沉积工艺形成的诸如氧化硅层的氧化物层。栅极介质层56 还可以包括在IL上方形成的高k介电层。高k介电层形成为共形层，并且 包括诸如氧化铪、氧化镧、氧化铝、氧化锆等的高k介电材料。高k介电 材料的介电常数(k值)高于3.9，并且可以高于约7.0。根据本公开的一 些实施例，栅极介电层56中的高k介电层使用ALD或CVD形成。
图15A、图15B、图16A、和图16B示出掩埋金属轨道112的暴露。 对应的步骤还示出为图24中所示的工艺流程中的步骤220。图15B示出可 以是光刻胶的蚀刻掩模58的形成。蚀刻掩模58被图案化以露出掩埋金属 轨道112正上方的栅极介电层56的部分，同时覆盖图15B中的鳍102上面 的栅极介电层56的部分。也暴露如图15A所示的栅极介电层56的部分。
接下来，蚀刻栅极介电层56的暴露部分。此外，还蚀刻介电帽28， 并且暴露出掩埋金属轨道112。在蚀刻栅极介电层56之后，去除蚀刻掩模 58，并且在图16A和图16B中示出了得到的结构。
在随后的步骤中，如图17B所示，栅电极60在栅极介电层56上方形 成并填充如图16B所示的沟槽54。相应的步骤被示出为图24所示的工艺 流程中的步骤222。栅电极60的形成可以包括多个沉积工艺以沉积多个导 电层，并且执行平坦化步骤以除去ILD 52上方的导电层的暴露部分(图 17A)。因此，所得到的栅电极60将具有在用虚线61所示的水平上的顶面。 可以使用诸如ALD或CVD的共形沉积方法来执行导电层的沉积。
栅电极60可以包括扩散阻挡层60A和扩散阻挡层上方的一个(或多个) 功函数层。扩散阻挡层60A可以由氮化钛(TiN)形成，其可以(或可以 不)掺杂硅以形成TiSiN。功函数层确定栅极的功函数，并且包括至少一层 或由不同材料形成的多层。根据各自的FinFET是n型FinFET还是p型 FinFET来选择功函数层的具体材料。例如，当FinFET是n型FinFET时，功函数层可以包括TaN层和在TaN层上方的钛铝(TiAl)层。当FinFET 是p型FinFET时，功函数层可以包括TaN层、TaN层上方的TiN层、和 TiN层上方的TiAl层。在沉积功函数层之后，形成可以是另一TiN层的另 一阻挡层。例如，栅电极60还可以包括由钨或钴形成的填充金属。填充金 属完全填充剩余的凹槽54(图16B)。
如图17B所示，导电材料的一部分形成通孔122，其位于栅电极60下 面，并且将栅电极60连接到掩埋金属轨道112。还在图1中示出通孔122。 掩埋金属轨道112和通孔122具有与在晶体管上方形成的互连结构中的金 属线和通孔相似的功能。接下来，蚀刻栅电极60以形成凹槽62，如图17B 所示。
参考图18B，在栅电极104上方形成硬掩模64。如图17B所示，硬掩 模64填充凹槽62。硬掩模64由介电材料形成，其可以是氧化硅、氮化硅、 氧化铝、碳化硅等。栅极介电层56、栅电极60、和硬掩模64组合被称为 栅极堆叠件104，其也在图1中所示。也如图1所示，栅极堆叠件104形 成彼此平行的多个带，并且栅极堆叠件104的长度方向可以垂直于掩埋金属轨道112的长度方向。
图19A至图22示出了源极/漏极接触插塞的形成。参考图19A，形成 并图案化光刻胶66。如图19B所示，光刻胶66覆盖栅极堆叠件104。然后， 将图案化的光刻胶66用作蚀刻掩模以蚀刻ILD 52，使得开口68形成为延 伸到ILD 52中。相应的步骤被示出为图24所示的工艺流程中的步骤224。 选择蚀刻剂，使得半导体区116不被蚀刻，并且可以在一些区域中用作蚀 刻停止层。在ILD 52的蚀刻之后，去除光刻胶66。
接下来，参考图20A和图20B，光刻胶70被形成和图案化，因此覆盖 栅极堆叠件104，并且使ILD 52的一部分露出。进一步蚀刻ILD 52，使得 开口68进一步向下延伸到ILD52中，直到暴露出介电帽28(图19A)。 然后，蚀刻暴露的介电帽28，并且暴露出掩埋金属轨道112。在蚀刻之后， 去除光刻胶70。
图21A示出了导电部件118的形成。相应的步骤被示出为图24所示的 工艺流程中的步骤226。此外，在半导体区116的表面上形成源极/漏极硅 化物区76。根据一些实施例，导电部件118的形成包括形成延伸到开口68 (图20A)中的金属层和金属氮化物层(未单独地示出)。金属层可以由 钛形成，并且金属氮化物层可以由氮化钛形成。金属层和金属氮化物层可 以是延伸到源极/漏极区46的侧壁以及面向上和面向下的刻面上的共形层。 接下来，执行退火，并且在源极/漏极区46的表面上形成源极/漏极硅化物 区76。然后，沉积金属材料以填充剩余的开口68，随后进行平坦化步骤。 因此，在ILD 52中形成导电部件118。导电部件118包括同时形成的源极/ 漏极接触插塞71和通孔120。因此，形成FinFET 80，每个FinFET 80包 括源极/漏极区46(图21A)，和鳍102以及在鳍102上方的栅极堆叠件 104(图21B，也参考图1)。
如图1和图21A所示，源极/漏极接触插塞71通过通孔120电连接到 掩埋金属轨道。因此，如图21A和图21B所示，掩埋金属轨道112能够同 时连接到栅电极和源极/漏极接触插塞(并且因此源极/漏极区)，并且可以 用作互连结构的一部分。
图22示出了根据一些实施例形成的源极/漏极接触插塞71的横截面 图。所示的源极/漏极接触插塞71不连接到掩埋金属轨道112。图22所示 的横截面图也可以从如图1所示的包含线D-D的竖直平面获得。
图23A和图23B示出了介电层84的形成，其也可以称为ILD，以及 ILD 84中的接触插塞82A和接触插塞82B。接触插塞82A和接触插塞82B 分别地连接至源极/漏极接触插塞71和栅电极60。然后，形成金属间电介 质(IMD)88和金属线86，金属线86连接到接触插塞82A和接触插塞82B。 例如，IMD 88可以由低k介电层形成。
图23C示出了从图1中的包含线C-C的竖直线获得的横截面图。根据 一些实施例，如图23C所示，相应的栅电极60未连接到掩埋金属轨道112。 相对地，栅极电介质56和介电帽28用于将相应的栅电极60与掩埋金属轨 道112电绝缘。
本公开的实施例具有一些有利的特征。在诸如标准单元的集成电路的 布局中，所需数量的金属线路成为用于减小集成电路的尺寸(特别是宽度 (诸如图1中的宽度Wcell))的瓶颈。通过掩埋一些金属线至STI区中而 不是在金属层中形成所有金属线，可以形成更多的金属线，并且可以减少 标准单元的宽度Wcell，其可能受限于分配所需数量的金属线的所需的宽度。 例如，标准单元的宽度Wcell可以减少约10％至约50％之间。晶体管的栅 极密度也可以被增加，因为晶体管可以更紧凑地布置，而不受金属线的布 线能力的限制。
根据本公开的一些实施例，一种集成电路包括半导体衬底、延伸到半 导体衬底的并且在半导体衬底的块状部分上面的隔离区、包括在隔离区中 的部分的掩埋导电轨道、以及具有源极/漏极区和栅电极的晶体管。源极/ 漏极区或栅电极连接到掩埋导电轨道。在一个实施例中，掩埋导电轨道包 括低于晶体管延伸的部分。在一个实施例中，掩埋导电轨道连接到栅电极， 并且集成电路还包括位于栅电极下面并连接到栅电极的通孔。在一个实施例中，栅电极连续地连接到通孔，在栅电极和通孔之间没有形成界面。在 一个实施例中，集成电路还包括连接到掩埋导电轨道的源极/漏极接触插 塞。在一个实施例中，集成电路还包括在源极/漏极接触插塞和掩埋导电轨 道之间的并且连接到源极/漏极接触插塞和掩埋导电轨道的附加通孔。在一 个实施例中，集成电路还包括介电层，该介电层包括位于掩埋导电轨道的 相对两侧上的侧壁部分，并且侧壁部分具有倾斜的顶面；以及被掩埋导电 轨道重叠的底部部分。
根据本公开的一些实施例，一种集成电路包括具有块状部分的半导体 衬底和介电层。介电层具有底部部分，底部部分具有与半导体衬底的块状 部分的顶面接触的底面；以及在底部上方的侧壁部分，并且侧壁部分连接 到底部部分的相对端。集成电路还包括位于介电层的底部部分上方并且在 介电层的侧壁部分之间的掩埋金属轨道；以及在掩埋金属轨道的顶面上面 并且接触掩埋金属轨道的顶面的介电帽。在一个实施例中，介电层的底部 部分延伸到半导体衬底的块状部分中。在一个实施例中，权利要求的集成 电路还包括浅沟槽隔离区，其具有在包括掩埋金属轨道和介电层的组合区 的相对侧上的部分。在一个实施例中，集成电路还包括在半导体衬底的块 状部分上面的半导体带；以及与半导体带重叠的半导体鳍，并且半导体鳍 高于浅沟槽隔离区，并且掩埋金属轨道的长度方向平行于半导体鳍的长度 方向。在一个实施例中，集成电路还包括包含源极/漏极区的晶体管；以及具有与源极/漏极区重叠的第一部分和与源极/漏极区处于相同水平的第二 部分的源极/漏极接触插塞，并且掩埋金属轨道的一部分被源极/漏极接触插 塞的第二部分重叠并且电连接到源极/漏极接触插塞的第二部分。在一个实 施例中，集成电路还包括具有栅电极的晶体管，并且掩埋金属轨道被栅电 极重叠并且电连接至栅电极。在一个实施例中，晶体管还包括栅极电介质， 并且掩埋金属轨道通过栅极电介质中的开口连接到栅电极。
根据本公开的一些实施例，一种方法包括蚀刻半导体衬底以形成第一 沟槽，将金属轨道填充到第一沟槽中，形成覆盖金属轨道的介电帽，以及 形成与金属轨道邻近的晶体管。晶体管包括源极/漏极区；源极/漏极接触插 塞；和栅电极，并且金属轨道具有被源极/漏极接触插塞和栅电极中的一个 重叠的部分。在一个实施例中，金属轨道的一部分在源极/漏极接触插塞的 下面，并且通过通孔连接到源极/漏极接触插塞。在一个实施例中，在共同 的工艺中形成通孔和源极/漏极接触插塞。在一个实施例中，金属轨道的部 分位于栅电极的下面并且通过通孔连接到栅电极。在一个实施例中，在共 同的工艺中形成通孔和栅电极。在一个实施例中，该方法还包括形成浅沟 槽隔离区，其包括在金属轨道的相对侧上的部分。
根据本公开的一些实施例，一种集成电路包括隔离区、彼此平行的第 一半导体带和第二半导体带，并且第一半导体带和第二半导体带位于隔离 区中，掩埋金属轨道在第一半导体带和第二半导体带之间；以及分别与第 一半导体带和第二半导体带重叠的第一半导体鳍和第二半导体鳍。在一个 实施例中，集成电路还包括跨越掩埋金属轨道、第一半导体鳍和第二半导 体鳍的栅电极。在一个实施例中，掩埋金属轨道电连接到栅电极。
根据本公开的一些实施例，一种方法包括形成延伸到半导体衬底中的 金属轨道，并且金属轨道由包括介电层和介电帽的介电部件包围；蚀刻半 导体衬底以形成半导体带；沉积介电材料以将金属轨道和半导体带嵌入其 中；使介电材料凹进以形成浅沟槽隔离区，并且介电帽被暴露出，并且半 导体带的顶部突出高于浅沟槽隔离区的顶面以形成半导体鳍；在半导体鳍 的第一部分上方形成金属栅极；在半导体鳍的第二部分上生长外延半导体区；以及将金属轨道电耦合到金属栅极和外延半导体区中的一个。在一个 实施例中，金属栅极与金属轨道的一部分重叠，并且金属轨道通过金属栅 极下面的通孔连接到金属栅极。在一个实施例中，在共同的工艺中形成通 孔和金属栅极。在一个实施例中，该方法还包括形成与外延半导体区的一 部分和金属轨道的一部分重叠的源极/漏极接触插塞，并且金属轨道通过源 极/漏极接触插塞下面的通孔连接到源极/漏极接触插塞。在一个实施例中，在共同的工艺中形成通孔和源极/漏极接触插塞。
根据本公开的一些实施例，一种方法包括形成晶体管，其包括具有高 于隔离区的顶面的部分的源极/漏极区；形成掩埋金属轨道，其具有比隔离 区的顶面低的部分；以及将晶体管连接到掩埋金属轨道。在一个实施例中， 该方法还包括形成在掩埋金属轨道的横截面图中围绕掩埋金属轨道的介电 层。
根据本申请的实施例，提供了一种集成电路，包括：半导体衬底；隔 离区，延伸到半导体衬底中并且在半导体衬底的块状部分上面；掩埋导电 轨道，包括在隔离区中的一部分；以及晶体管，包括源极/漏极区和栅电极， 其中，源极/漏极区或栅电极连接到掩埋导电轨道。
根据本申请的实施例，掩埋导电轨道包括低于晶体管延伸的部分。
根据本申请的实施例，掩埋导电轨道连接到栅电极，并且集成电路还 包括位于栅电极下面的并连接到栅电极的通孔。
根据本申请的实施例，栅电极连续地连接到通孔，在栅电极和通孔之 间没有形成界面。
根据本申请的实施例，还包括连接到掩埋导电轨道的源极/漏极接触插 塞。
根据本申请的实施例，还包括在源极/漏极接触插塞和掩埋导电轨道之 间并连接到源极/漏极接触插塞和掩埋导电轨道的附加通孔。
根据本申请的实施例，还包括介电层，介电层包括：在掩埋导电轨道 的相对侧上的侧壁部分，其中，侧壁部分具有倾斜的顶面；以及被掩埋导 电轨道重叠的底部部分。
根据本申请的实施例，提供了一种集成电路，包括：半导体衬底，半 导体衬底包括块状部分；介电层，介电层包括：底部部分，底部部分具有 接触半导体衬底的块状部分的顶面的底面；以及在底部部分上方的侧壁部 分，其中，侧壁部分连接到底部部分的相对端；掩埋金属轨道，位于介电 层的底部部分上方并且在介电层的侧壁部分之间；以及介电帽，位于掩埋 金属轨道的顶面上面并且接触掩埋金属轨道的顶面。
根据本申请的实施例，介电层的底部部分延伸到半导体衬底的块状部 分中。
根据本申请的实施例，还包括：浅沟槽隔离区，包括在包含掩埋金属 轨道和介电层的组合区的相对侧上的部分。
根据本申请的实施例，还包括：在半导体衬底的块状部分上面的半导 体带；以及与半导体带重叠的半导体鳍，其中，半导体鳍高于浅沟槽隔离 区，并且其中，掩埋金属轨道的长度方向平行于半导体鳍的长度方向。
根据本申请的实施例，还包括晶体管，晶体管包括：源极/漏极区；以 及源极/漏极接触插塞，源极/漏极接触插塞具有与源极/漏极区重叠的第一 部分和与源极/漏极区处于相同水平的第二部分，其中，掩埋金属轨道的一 部分被源极/漏极接触插塞的第二部分重叠并且电连接至源极/漏极接触插 塞的第二部分。
根据本申请的实施例，还包括晶体管，晶体管包括：栅电极，其中， 掩埋金属轨道被栅电极重叠并且电连接至栅电极。
根据本申请的实施例，晶体管还包括栅极电介质，其中，掩埋金属轨 道通过栅极电介质中的开口连接到栅电极。
根据本申请的实施例，提供了一种形成集成电路的方法，包括：蚀刻 半导体衬底以形成第一沟槽；将金属轨道填充到第一沟槽中；形成覆盖金 属轨道的介电帽；以及形成与金属轨道邻近的晶体管，其中，晶体管包括： 源极/漏极区；源极/漏极接触插塞；以及栅电极，其中，金属轨道包括被源 极/漏极接触插塞和栅电极中的一个重叠的部分。
根据本申请的实施例，金属轨道的部分在源极/漏极接触插塞的下面并 且通过通孔连接到源极/漏极接触插塞。
根据本申请的实施例，在共同的工艺中形成通孔和源极/漏极接触插 塞。
根据本申请的实施例，金属轨道的部分在栅电极的下面并且通过通孔 连接到栅电极。
根据本申请的实施例，在共同的工艺中形成通孔和栅电极。
根据本申请的实施例，还包括形成浅沟槽隔离区，浅沟槽隔离区包括 在金属轨道的相对侧上的部分。
以上论述了若干实施例的特征，使得本领域技术人员可以更好地理解 本发明的各方面。本领域技术人员应该理解，他们可以容易地使用本发明 作为基础来设计或修改用于实施与本文所介绍的实施例相同的目的和/或 实现相同优点的其他工艺和结构。本领域技术人员也应该意识到，这种等 同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围 的情况下，本文中他们可以做出多种变化、替换以及改变。

Claims (10)

1.一种集成电路，包括：
半导体衬底；
隔离区，延伸到所述半导体衬底中并且在所述半导体衬底的块状部分上面；
掩埋导电轨道，包括在所述隔离区中的一部分；以及
晶体管，包括源极/漏极区和栅电极，其中，所述源极/漏极区或所述栅电极连接到所述掩埋导电轨道。
2.根据权利要求1所述的集成电路，其中，所述掩埋导电轨道包括低于所述晶体管延伸的部分。
3.根据权利要求1所述的集成电路，其中，所述掩埋导电轨道连接到所述栅电极，并且所述集成电路还包括位于所述栅电极下面的并连接到所述栅电极的通孔。
4.根据权利要求3所述的集成电路，其中，所述栅电极连续地连接到所述通孔，在所述栅电极和所述通孔之间没有形成界面。
5.根据权利要求1所述的集成电路，还包括连接到所述掩埋导电轨道的源极/漏极接触插塞。
6.根据权利要求5所述的集成电路，还包括在所述源极/漏极接触插塞和所述掩埋导电轨道之间并连接到所述源极/漏极接触插塞和所述掩埋导电轨道的附加通孔。
7.根据权利要求1所述的集成电路，还包括介电层，所述介电层包括：
在所述掩埋导电轨道的相对侧上的侧壁部分，其中，所述侧壁部分具有倾斜的顶面；以及
被所述掩埋导电轨道重叠的底部部分。
8.一种集成电路，包括：
半导体衬底，所述半导体衬底包括块状部分；
介电层，所述介电层包括：
底部部分，所述底部部分具有接触所述半导体衬底的所述块状部分的顶面的底面；以及
在所述底部部分上方的侧壁部分，其中，所述侧壁部分连接到所述底部部分的相对端；
掩埋金属轨道，位于所述介电层的所述底部部分上方并且在所述介电层的所述侧壁部分之间；以及
介电帽，位于所述掩埋金属轨道的顶面上面并且接触所述掩埋金属轨道的顶面。
9.根据权利要求8所述的集成电路，其中，所述介电层的所述底部部分延伸到所述半导体衬底的所述块状部分中。
10.一种形成集成电路的方法，包括：
蚀刻半导体衬底以形成第一沟槽；
将金属轨道填充到所述第一沟槽中；
形成覆盖所述金属轨道的介电帽；以及
形成与所述金属轨道邻近的晶体管，其中，所述晶体管包括：
源极/漏极区；
源极/漏极接触插塞；以及
栅电极，其中，所述金属轨道包括被所述源极/漏极接触插塞和所述栅电极中的一个重叠的部分。
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