CN109841619A - 半导体结构切割工艺和由此形成的结构 - Google Patents

半导体结构切割工艺和由此形成的结构 Download PDF

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CN109841619A
CN109841619A CN201810920097.6A CN201810920097A CN109841619A CN 109841619 A CN109841619 A CN 109841619A CN 201810920097 A CN201810920097 A CN 201810920097A CN 109841619 A CN109841619 A CN 109841619A
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fin
cutting
interstitital texture
grid
semiconductor structure
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CN109841619B (zh
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黄士文
林嘉慧
张智铭
陈哲明
郑凯鸿
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
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    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
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    • H01L29/7855—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with at least two independent gates
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Abstract

描述了切割鳍的方法和由此形成的结构。在实施例中，结构包括位于衬底上的第一鳍、位于衬底上的第二鳍以及设置在第一鳍和第二鳍之间的鳍切割填充结构。第一鳍和第二鳍纵向对准。鳍切割填充结构包括绝缘衬垫和位于绝缘衬垫上的填充材料。绝缘衬垫邻接第一鳍的第一侧壁和第二鳍的第二侧壁。绝缘衬垫包括带隙大于5eV的材料。本发明实施例涉及半导体结构切割工艺和由此形成的结构。

Description

半导体结构切割工艺和由此形成的结构
技术领域
本发明实施例涉及半导体结构切割工艺和由此形成的结构。
背景技术
随着半导体工业在追求更高的器件密度、更高的性能和更低的成本的过程中进入纳米技术工艺节点，来自制造和设计问题的挑战已经引起了诸如鳍式场效应晶体管(FinFET)的三维设计的发展。FinFET器件通常包括具有高高宽比的半导体鳍，并且在该半导体鳍中形成沟道和源极/漏极区域。利用沟道的增大的表面积的优势，在鳍结构上方以及沿着鳍结构的侧面(例如，包裹)形成栅极，以产生更快、更可靠和更易控制的半导体晶体管器件。然而，随着按比例缩小，出现了新的挑战。
发明内容
根据本发明的一些实施例，提供了一种半导体结构，包括：第一鳍，位于衬底上；第二鳍，位于所述衬底上，所述第一鳍和所述第二鳍纵向对准；以及鳍切割填充结构，设置在所述第一鳍和所述第二鳍之间，所述鳍切割填充结构包括：绝缘衬垫，邻接所述第一鳍的第一侧壁和所述第二鳍的第二侧壁，所述绝缘衬垫包括带隙大于5eV的材料；和填充材料，位于所述绝缘衬垫上。
根据本发明的另一些实施例，还提供了一种半导体结构，包括：绝缘结构，横向设置在所述第一鳍和所述第二鳍之间，所述第一鳍和所述第二鳍在衬底上纵向对准，所述绝缘结构包括：高带隙衬垫，沿着所述第一鳍和所述第二鳍的相应端部侧壁设置，所述高带隙衬垫具有大于5eV的带隙；以及填充材料，位于所述高带隙衬垫上。
根据本发明的又一些实施例，还提供了一种形成半导体结构的方法，包括：在衬底上形成鳍；通过在所述鳍的第一段和所述鳍的第二段之间形成切割开口，将所述鳍切割成所述鳍的第一段和所述鳍的第二段；在所述切割开口中形成共形衬垫层，所述共形衬垫层包括带隙大于5eV的材料；以及在所述切割开口中的所述共形衬垫层上形成填充材料。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳理解本发明的各个方面。应该指出，根据工业中的标准实践，各个部件未按比例绘制。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1、图2、图3A至图3B、图4A至图4D、图5A至图5C、图6A至图6C、图7A至图7C、图8A至图8C、图9A至图9C、图10A至图10C、图11A至图11C、图12A至图12C、图13A至图13C是根据一些实施例的处于形成包括一个或多个FinFET的半导体器件的示例性工艺的中间阶段的相应的中间结构的各个视图。
图14是根据一些实施例的示例性鳍切割填充结构的截面图。
具体实施方式
以下公开内容提供了许多用于实现所提供主题的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。此外，本发明可在各个实施例中重复参考标号和/或字符。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且，为便于描述，在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等空间相对术语，以描述如图所示的一个元件或部件与另一个(或另一些)原件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上)，而本文使用的空间相对描述符可以同样地作出相应的解释。
本文描述了切割半导体器件(诸如包括鳍式场效应晶体管(FinFET))中的有源区(诸如鳍)的方法以及由这些方法形成的结构。通常，在形成多个(例如，双层)绝缘结构的位置处(在该位置处切割鳍)实施鳍切割工艺。多个绝缘结构包括绝缘衬垫，该绝缘衬垫包括或是高带隙材料，其可以减小切割的鳍的段之间的泄漏电流。
在FinFET的上下文中描述本文描述的示例性实施例。可以在其他工艺中和/或其他器件中使用本发明实现的一些方面。描述了示例性方法和结构的一些变型。本领域普通技术人员将容易理解，可以作出的其他修改预期在其他实施例的范围内。虽然以特定顺序讨论了方法实施例，但是各个其他方法实施例可以以任何逻辑顺序实施并且可以包括本文中描述的更少或更多的步骤。
图1、图2、图3A至图3B、图4A至图4D以及图5A至图5C至图13A至图13C是根据一些实施例的形成包括一个或多个FinFET的半导体器件的示例性工艺中的中间阶段期间相应的中间结构的各个视图。图1以截面图示出了半导体衬底20。半导体衬底20可以是或可以包括块状半导体衬底、绝缘体上半导体(SOI)衬底等，其可以是掺杂(例如，用p型或n型掺杂剂)或未掺杂的。通常，SOI衬底包括形成在绝缘层上的半导体材料层。绝缘层可以是例如埋氧(BOX)层、氧化硅层等。通常在硅或玻璃衬底的衬底上提供绝缘层。也可以使用诸如多层衬底或梯度衬底的其他衬底。在一些实施例中，半导体衬底的半导体材料可以包括硅(Si)；锗(Ge)；包括碳化硅、砷化镓、磷化镓、磷化铟、砷化铟或锑化铟的化合物半导体；包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP或GaInAsP的合金半导体；或它们的组合。
图2以截面图示出了半导体衬底20中的鳍24的形成。在一些实例中，在形成鳍24中，使用掩模(例如，硬掩模)。例如，在半导体衬底20上方沉积一个或多个掩模层，并且之后将一个或多个掩模层图案化成掩模。在一些实例中，一个或多个掩模层可以包括或可以是氮化硅、氮氧化硅、碳化硅、碳氮化硅等或它们的组合，并且可以通过化学汽相沉积(CVD)、物理汽相沉积(PVD)、原子层沉积(ALD)或其他沉积技术来沉积。可以使用光刻图案化一个或多个掩模层。例如，可以诸如通过使用旋涂在一个或多个掩模层上形成光刻胶，并且通过使用适当的光掩模将光刻胶暴露于光来图案化光刻胶。之后，取决于使用的是正性光刻胶还是负性光刻胶来去除光刻胶的曝光或未曝光部分。之后，可以诸如通过使用合适的蚀刻工艺将光刻胶的图案转印至一个或多个掩模层，从而形成掩模。蚀刻工艺可以包括反应离子蚀刻(RIE)、中性束蚀刻(NBE)、电感耦合等离子体(ICP)蚀刻等或它们的组合。蚀刻工艺可以是各向异性的。随后，例如，在灰化或湿剥离工艺中去除光刻胶。
使用掩模，可以蚀刻半导体衬底20，从而在相邻的一对鳍24之间形成沟槽并且使得鳍24从半导体衬底20突出。蚀刻工艺可以包括RIE、NBE、ICP蚀刻等或它们的组合。蚀刻工艺可以是各向异性的。
图3A和图3B分别以截面图和俯视图示出了隔离区域26各自在相应的沟槽中的形成。隔离区域26可以包括或可以是诸如氧化物(诸如氧化硅)、氮化物等或它们的组合的绝缘材料，并且可以通过高密度等离子体CVD(HDP-CVD)、可流动CVD(FCVD)(例如，远程等离子体系统中的CVD基材料沉积以及后固化以使其转化成诸如氧化物的另一材料)等或它们的组合形成绝缘材料。可以使用由任何可接受的工艺形成的其他绝缘材料。在示出的实施例中，隔离区域26包括由FCVD工艺形成的氧化硅。诸如化学机械抛光(CMP)的平坦化工艺可以去除任何过量的绝缘材料和任何剩余的掩模(例如，用于蚀刻沟槽并且形成鳍24)以使绝缘材料的顶面和鳍24的顶面形成为共面。之后，可以使绝缘材料凹进以形成隔离区域26。使绝缘材料凹进，从而使得鳍24从相邻的隔离区域26之间突出，这可以至少部分地将鳍24划定为半导体衬底20上的有源区。可以使用可接受的蚀刻工艺(诸如对绝缘材料的材料有选择性的工艺)使绝缘材料凹进。例如，可以采用使用蚀刻、应用材料SICONI工具或稀氢氟(dHF)酸的化学氧化物去除。此外，隔离区域26的顶面可以具有如图所示的平坦表面、可以由蚀刻工艺产生的凸表面、凹表面(诸如凹陷)或它们的组合。如图3B的俯视图示出的，鳍24横跨半导体衬底20纵向延伸。
本领域普通技术人员将容易理解，参照图1至图3A至图3B描述的工艺仅仅是如何可以形成鳍24的实例。在其他实施例中，可以在半导体衬底20的顶面上方形成介电层；可以穿过介电层蚀刻沟槽；可以在沟槽中外延生长同质外延结构；并且可以使介电层凹进，从而使得同质外延结构从介电层突出以形成鳍。仍在其他实施例中，异质外延结构可以用于鳍。例如，可以使鳍24凹进(例如，在平坦化隔离区域26的绝缘材料之后并且在使绝缘材料凹进之前)，并且可以在它们的位置外延生长与鳍不同的材料。在更进一步的实施例中，可以在半导体衬底20的顶面上方形成介电层；可以穿过介电层蚀刻沟槽；可以使用与半导体衬底20不同的材料在沟槽中外延生长异质外延结构；并且可以使介电层凹进，从而使得异质外延结构从介电层突出以形成鳍。在外延生长同质外延或异质外延结构的一些实施例中，生长材料可以在生长期间原位掺杂，这可以避免鳍的之前的注入，但是原位掺杂和注入掺杂可以一起使用。更进一步地，对n型器件外延生长的材料与对p型器件外延生长的材料不同可能是有利的。
图4A、图4B、图4C和图4D示出了鳍24上的伪栅极堆叠件的形成。图4A和图4B示出了截面图；图4C示出了俯视图；以及图4D示出了三维视图。图4C和图4D示出了截面A-A和B-B。图1、图2、图3A、图4A和以下以“A”字符结尾的附图示出了对应于截面A-A的处于各个工艺阶段的截面图，并且图4B和以下以“B”字符结尾的附图示出了对应于截面B-B的处于各个工艺阶段的截面图。在一些附图中，可以省略其中示出的组件或部件的一些参考标号以避免模糊其他组件或部件；这是为了便于描述附图。
伪栅极堆叠件位于鳍24上方并且垂直于鳍24横向延伸。每个伪栅极堆叠件均包括一个或多个界面电介质28、伪栅极30和掩模32。可以通过依次形成相应的层，并且之后将这些层图案化成伪栅极堆叠件来形成用于伪栅极堆叠件的一个或多个界面电介质28、伪栅极30和掩模32。例如，用于一个或多个界面电介质28的层可以包括或可以是氧化硅、氮化硅等或它们的多层，并且可以如图所示热生长和/或化学生长在鳍24上，或诸如通过等离子体增强CVD(PECVD)、ALD或其他沉积技术共形沉积。用于伪栅极30的层可以包括或可以是由CVD、PVD或其他沉积技术沉积的硅(例如，多晶硅)或另一材料。用于掩模32的层可以包括或可以是由CVD、PVD、ALD或其他沉积技术沉积的氮化硅、氮氧化硅、碳氮化硅等或它们的组合。之后，可以例如使用如上所述的光刻和一个或多个蚀刻工艺来图案化用于掩模32、伪栅极30和一个或多个界面电介质28的层以形成用于每个伪栅极堆叠件的掩模32、伪栅极30和一个或多个界面电介质28。
在示出的实例中，伪栅极堆叠件实施为用于替换栅极工艺。在其他实例中，可以使用栅极堆叠件来实施先栅极工艺，栅极堆叠件包括例如代替一个或多个界面电介质28的栅极电介质以及代替伪栅极30的栅电极。在一些先栅极工艺中，可以使用与参照伪栅极堆叠件描述的类似的工艺和材料形成栅极堆叠件；但是在其他实例中，可以实施其他工艺或材料。例如，栅极电介质可以包括或可以是高k介电材料，诸如具有大于约7.0的k值，高k介电材料可以包括Hf、Al、Zr、La、Mg、Ba、Ti、Pb的金属氧化物或硅酸盐、它们的多层或它们的组合。也可以通过分子束沉积(MBD)、ALD、PECVD或其他沉积技术来沉积栅极电介质。栅电极也可以包括或可以是诸如TiN、TaN、TaC、Co、Ru、Al、它们的多层或它们的组合的含金属材料，并且也可以通过CVD、PVD或其他沉积技术来沉积。
截面A-A沿着伪栅极堆叠件，在随后的附图和描述中将通过该截面A-A进行栅极切割和鳍切割。截面B-B沿着鳍24(例如，沿着鳍24中的沟道方向)，在随后的附图和描述中将通过该截面B-B进行鳍切割。截面A-A和B-B彼此垂直。
图5A、图5B和图5C示出了栅极间隔件34的形成。沿着伪栅极堆叠件的侧壁(例如，一个或多个界面电介质28、伪栅极30和掩模32的侧壁)并且在鳍24上方形成栅极间隔件34。也可以沿着鳍24的侧壁形成残留栅极间隔件34。例如，可以通过共形沉积用于栅极间隔件34的一个或多个层并且各向异性蚀刻一个或多个层来形成栅极间隔件34。用于栅极间隔件34的一个或多个层可以包括或可以是碳氮化硅、氮化硅、氮氧化硅、碳氮化硅等、它们的多层或它们的组合，并且可以通过CVD、ALD或其他沉积技术来沉积。蚀刻工艺可以包括RIE、NBE或其他蚀刻工艺。
在鳍24中形成源极/漏极区域35。在一些实例中，通过使用伪栅极堆叠件和栅极间隔件34作为掩模将掺杂剂注入至鳍24来形成源极/漏极区域35。因此，可以通过在每个伪栅极堆叠件的相对侧上注入来形成源极/漏极区域35。在其他实例中，可以使用伪栅极堆叠件和栅极间隔件34作为掩模使鳍24凹进，并且可以在凹槽中外延生长外延源极/漏极区域35。外延源极/漏极区域35可以相对于鳍24凸起，如图5B中的虚线示出的。外延源极/漏极区域35可以在外延生长期间通过原位掺杂而掺杂和/或在外延生长之后通过注入来掺杂。因此，源极/漏极区域35可以通过外延生长并且可能利用在每个伪栅极堆叠件的相对侧上的注入形成。用于源极/漏极区域35的示例性掺杂剂可以包括或可以是例如用于p型器件的硼和用于n型器件的磷或砷，但是可以使用其他掺杂剂。源极/漏极区域35可以具有在从约1019cm-3至约1021cm-3的范围内的掺杂剂浓度。源极/漏极区域35未在随后的附图中明确示出以避免模糊那些图中示出的其他部件和组件；然而，本领域普通技术人员将容易理解，源极/漏极区域35存在于那些图示出的结构中。
图6A、图6B和图6C示出了一个或多个介电层36的形成。例如，一个或多个介电层36可以包括蚀刻停止层(ESL)和层间电介质(ILD)。通常，蚀刻停止层可以提供当形成例如接触件或通孔时的蚀刻工艺的停止机制。蚀刻停止层可以由与邻近的层(例如，层间电介质)具有不同蚀刻选择性的介电材料形成。蚀刻停止层可以共形地沉积在鳍24、伪栅堆叠件、栅极间隔件34和隔离区域26上方。蚀刻停止层可以包括或可以是氮化硅、碳氮化硅、碳氧化硅、碳氮化物等或它们的组合，并且可以通过CVD、PECVD、ALD或其他沉积技术来沉积。层间电介质可以包括或可以是二氧化硅、诸如氮氧化硅、磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BSG)、硼磷硅酸盐玻璃(BPSG)、未掺杂硅酸盐玻璃(USG)、氟硅酸盐玻璃(FSG)、有机硅酸盐玻璃(OSG)、SiOxCy、旋涂玻璃、旋涂聚合物、硅碳材料、它们的化合物、它们的复合物等的低k介电材料(例如，具有小于二氧化硅的介电常数的材料)或它们的组合。可以通过旋涂、CVD、FCVD、PECVD、PVD或其他沉积技术来沉积层间电介质。
一个或多个介电层36形成为具有与伪栅极30的顶面共面的顶面。可以实施诸如CMP的平坦化工艺，以使一个或多个介电层36的顶面与伪栅极30的顶面齐平。CMP也可以去除伪栅极30上的掩模32(以及在一些情况下，栅极间隔件34的上部)。因此，通过一个或多个介电层36暴露伪栅极30的顶面。
图7A、图7B和图7C示出了形成切割开口42以切割伪栅极堆叠件。在示出的实例中，使用掩模40(例如，硬掩模)来形成切割开口42。例如，在伪栅极堆叠件、栅极间隔件34和一个或多个介电层36上方沉积一个或多个掩模层，并且之后图案化一个或多个掩模层以形成具有对应于切割开口42的掩模开口的掩模40。在一些实例中，一个或多个掩模层可以包括或可以是氮化硅、氮氧化硅、碳化硅、碳氮化硅等或它们的组合，并且可以通过CVD、PVD、ALD或其他沉积技术来沉积。如前所述，可以使用光刻和蚀刻工艺图案化一个或多个掩模层。掩模40可以具有在与将要切割的伪栅极堆叠件横向垂直并且相交的方向上延伸的掩模开口(每个均对应于切割开口42)。
使用掩模40，可以蚀刻伪栅极堆叠件、栅极间隔件34和一个或多个介电层36，从而形成切割伪栅极堆叠件的切割开口42。切割开口42可以例如穿过伪栅极30以及取决于实施方式穿过一个或多个界面电介质28延伸至对应的隔离区域26中和/或内一定深度。蚀刻工艺可以包括RIE、NBE、ICP蚀刻等或它们的组合。蚀刻可以是各向异性的。
图8A、图8B和图8C示出了在切割开口42中形成栅极切割填充结构44。在切割伪栅极堆叠件的切割开口42中沉积用于栅极切割填充结构44的绝缘材料。例如，如上所述，在切割开口42延伸至对应的隔离区域26中和/或内一定深度的情况下，栅极切割填充结构44可以延伸至对应的隔离区域26中和/或内(例如，栅极切割填充结构44的底面可以位于对应的隔离区域26的顶面之下一定深度处)。在一些实例中，栅极切割填充结构44的每个均可以是单一绝缘材料，并且在其他实例中，栅极切割填充结构44可以包括诸如以多层配置的多种不同的绝缘材料。在一些实例中，绝缘材料可以包括或可以是氧化硅、氮化硅、氮氧化硅、碳化硅、碳氮化硅等或它们的组合，并且可以通过CVD、PVD、ALD或其他沉积技术来沉积。去除一个或多个介电层36的顶面之上的用于栅极切割填充结构44的绝缘材料的部分以及掩模40。例如，如CMP的平坦化工艺可以去除一个或多个介电层36的顶面之上的用于栅极切割填充结构44的绝缘材料的部分以及掩模40，并且栅极切割填充结构44的顶面可以形成为与一个或多个介电层36的顶面共面。因此，栅极切割填充结构44电隔离伪栅极堆叠件的彼此被切割的段。
图9A、图9B和图9C示出了切割开口52的形成以切割鳍24。在示出的实例中，使用掩模50(例如，硬掩模)来形成切割开口52。例如，在伪栅极堆叠件、栅极间隔件34、一个或多个介电层36和栅极切割填充结构44上方沉积一个或多个掩模层，之后图案化一个或多个掩模层以形成具有对应于切割开口52的掩模开口的掩模50。在一些实例中，一个或多个掩模层可以包括或可以是氮化硅、氮氧化硅、碳化硅、碳氮化硅等或它们的组合，并且可以通过CVD、PVD、ALD或其他沉积技术来沉积。如前所述，可以使用光刻和蚀刻工艺图案化一个或多个掩模层。掩模50可以具有在与将要切割的鳍24横向垂直并且相交的方向上延伸的掩模开口(每个均对应于切割开口52)。
使用掩模50，蚀刻由掩模50中的切割开口52暴露的伪栅极堆叠件、栅极切割填充结构44和鳍24，从而形成切割暴露的鳍24的切割开口52。切割开口52可以延伸至隔离区域26的上表面之下一定深度。例如，蚀刻可以形成延伸至隔离区域26内(此处鳍24被切割)的切割开口52。切割鳍24的鳍切割区域54保留在半导体衬底20上。鳍切割区域54位于相邻隔离区域26之间并且具有位于相邻隔离区域26的顶面之下的顶面。蚀刻工艺可以包括RIE、NBE、ICP蚀刻等或它们的组合。蚀刻可以是各向异性的。在已经形成切割鳍24的切割开口52之后，可以去除掩模50。
图10A、图10B和图10C示出了在切割鳍24的切割开口52中共形地形成绝缘衬垫56和位于绝缘衬垫56上的填充材料58。绝缘衬垫56可以包括或可以是高带隙材料，诸如具有等于或大于约5eV的带隙的材料，高带隙材料也可以等于或大于约氮化硅的带隙的两倍。示例性高带隙材料包括氧化硅(SiOx)、氧化铝(Al2O3)、氧化钛(TiOx)、氧化钽(TaOx)、氟化铝(AlF)、氟氧化铝(AlOFx)、硅酸锆(ZrSiOx)、硅酸铪(HfSiOx)、氧化铪(HfO2)、氧化锆(ZrO2)或它们的组合。
一些实例使用ALD工艺来形成绝缘衬垫56。这种ALD工艺可以使用诸如SiH2[N(C2H5)2]2、硅烷(SiH4)、氧(O2)、三甲基铝(Al2(CH3)6)、蒸汽(H2O)、臭氧(O3)、氟(F2)和三氟化氮(NF3)的一种或多种前体来沉积以上列出的高带隙材料或其他材料，并且可以使用范围在从约100W至约1000W的范围内的射频(RF)功率、范围在从约2torr至约9torr的压力以及范围在从约45℃至约700℃的温度。ALD技术可以提供具有良好阶梯覆盖的均匀绝缘衬垫56。
填充材料58可以是绝缘材料。在一些实例中，填充材料58可以是单一绝缘材料，并且在其他实例中，填充材料58可以包括诸如以多层配置的多种不同的绝缘材料。填充材料58可以包括或可以是氮化硅、氮氧化硅、碳化硅、碳氮化硅等或它们的组合，并且可以通过ALD、热沉积、CVD或其他沉积技术来沉积。在实例中，填充材料58是由ALD或CVD沉积的氮化硅。
图11A、图11B和图11C示出了去除位于一个或多个介电层36、栅极间隔件34、栅极切割填充结构44和伪栅极堆叠件的顶面之上的填充材料58和绝缘衬垫56的过量部分以形成鳍切割填充结构。例如，如CMP的平坦化工艺可以去除位于一个或多个介电层36等的顶面之上的填充材料58和绝缘衬垫56的部分，并且鳍切割填充结构的顶面可以形成为与一个或多个介电层36等的顶面共面。平坦化工艺可以进一步暴露伪栅极30，以用于随后伪栅极堆叠件的替换。每个鳍切割填充结构均包括填充材料58和绝缘衬垫56。鳍24的切割形成鳍切割填充结构，鳍切割填充结构垂直于鳍24横向延伸并且切开被切割的鳍24。由于鳍切割填充结构，在鳍24的切割之前的鳍24的整个段可以制成彼此电隔离的段。
图12A、图12B和图12C示出了用替换栅极结构替换伪栅极堆叠件。在实施先栅极工艺的其他实施例中，可以省略图12A、图12B和图12C的工艺。诸如通过一个或多个蚀刻工艺去除伪栅极30和一个或多个界面电介质28。可以通过对伪栅极30有选择性的蚀刻工艺去除伪栅极30，其中，一个或多个界面电介质28用作蚀刻停止层，并且随后，可以通过对一个或多个界面电介质28有选择性的不同的蚀刻工艺去除一个或多个界面电介质28。蚀刻工艺可以是例如RIE、NBE、湿蚀刻工艺或其他蚀刻工艺。在栅极间隔件34之间(从该处去除了伪栅极堆叠件)形成凹槽，并且通过凹槽暴露鳍24的沟道区域。
在通过去除伪栅极堆叠件而形成的凹槽中形成替换栅极结构。每个替换栅极结构均包括一个或多个共形层60和栅电极62。一个或多个共形层60包括栅极介电层并且可以包括一个或多个功函调整层。栅极介电层可以共形地沉积在去除了伪栅极堆叠件的凹槽中(例如，隔离区域26的顶面上、鳍24的沿着沟道区域的侧壁和顶面上以及栅极间隔件34和栅极切割填充结构44的侧壁上)以及一个或多个介电层36、栅极间隔件34和栅极切割填充结构44的顶面上。栅极介电层可以是或包括氧化硅、氮化硅、高k介电材料、它们的多层或其他介电材料。高k介电材料可以具有大于约7.0的k值，并且可以包括HF、Al、Zr、La、Mg、Ba、Ti、Pb的金属氧化物或金属硅酸盐或它们的组合。可以通过ALD、PECVD、MBD或其他沉积技术来沉积栅极介电层。
之后，如果实施，则可以在栅极介电层上共形地沉积功函调整层。功函调整层可以包括或者可以是钽、氮化钽、钛、氮化钛等或它们的组合，并且可以通过ALD、PECVD、MBD或其他沉积技术来沉积。与该功函调整层类似，可以依次沉积任何额外的功函调整层。
在一个或多个共形层60上方形成用于栅电极62的层。用于栅电极62的层可以填充去除伪栅极堆叠件的剩余的凹槽。用于栅电极62的层可以是或包括含金属材料，诸如Co、Ru、Al、W、Cu、它们的多层或它们的组合。可以通过ALD、PECVD、MBD、PVD或其他沉积技术来沉积用于栅电极62的层。
去除一个或多个介电层36、栅极间隔件34和栅极切割填充结构44的顶面之上的用于栅电极62的层和一个或多个共形层60的部分。例如，如CMP的平坦化工艺可以去除一个或多个介电层36、栅极间隔件34和栅极切割填充结构44的顶面之上的用于栅电极62的层和一个或多个共形层60的部分。因此，如图12A至图12C示出的，可以形成包括栅电极62和一个或多个共形层60的替换栅极结构。
图13A、图13B和图13C示出了形成一个或多个介电层70和在一个或多个介电层36和/或70中形成至鳍24的源极/漏极区域35和至栅电极62的导电部件72。例如，一个或多个介电层70可以包括蚀刻停止层(ESL)和层间电介质(ILD)或金属间电介质(IMD)。可以在一个或多个介电层36、栅极切割填充结构44、鳍切割填充结构、栅极间隔件34、栅电极62和一个或多个共形层60上方沉积蚀刻停止层。蚀刻停止层可以包括或可以是氮化硅、碳氮化硅、碳氧化硅、碳氮化物等或它们的组合，并且可以通过CVD、PECVD、ALD或其他沉积技术来沉积。层间电介质或金属间电介质可以包括或可以是二氧化硅、诸如氧氮化硅、PSG、BSG、BPSG、USG、FSG、OSG、SiOxCy、旋涂玻璃、旋涂聚合物、硅碳材料的低k介电材料、它们的化合物、它们的复合物等或它们的组合。可以通过旋涂、CVD、FCVD、PECVD、PVD或其他沉积技术来沉积层间电介质或金属间电介质。
可以在介电层70和36中和/或穿过介电层70和36形成至源极/漏极区域35和栅电极62的凹槽和/或开口，以分别暴露源极/漏极区域35和栅电极62的至少部分。例如，可以使用光刻和一个或多个蚀刻工艺将介电层70和36图案化为具有凹槽和/或开口。之后，可以在凹槽和/或开口中形成导电部件72。例如，导电部件72可以包括粘合层和/或阻挡层以及位于粘合层和/或阻挡层上的导电材料。在一些实例中，导电部件72可以包括硅化物区域。
粘合层和/或阻挡层可以共形地沉积在凹槽和/或开口中以及一个或多个介电层70上方。粘合层和/或阻挡层可以是或包括钛、氮化钛、氧化钛、钽、氮化钽、氧化钽等或它们的组合，并且可以通过ALD、CVD或其他沉积技术来沉积。通过使源极/漏极区域35的上部与粘合层和/或阻挡层反应，可以在源极/漏极区域35的上部上形成硅化物区域。可以实施退火以促进源极/漏极区域35与粘合层和/或阻挡层的反应。
导电材料可以沉积在粘合层和/或阻挡层上并且填充凹槽和/或开口。导电材料可以是或包括钨、铜、铝、金、银、它们的合金等或它们的组合，并且可以通过CVD、ALD、PVD或其他沉积技术来沉积。在沉积导电部件72的材料之后，可以例如通过使用诸如CMP的平坦化工艺去除过量的材料。平坦化工艺可以从一个或多个介电层70的顶面之上去除导电部件72的过量材料。因此，导电部件72和一个或多个介电层70的顶面可以是共面的。导电部件72可以是或可以称为接触件、插塞等。
如图所示，导电部件72形成至鳍24的源极/漏极区域35或至替换栅极结构以分别电连接源极/漏极区域35或替换栅极结构。附图中的导电部件72的布局仅仅是实例。本领域普通技术人员将容易理解，导电部件的布局可以在不同的实施方式之间不同。
图14示出了根据一些实施例的示例性鳍切割填充结构的截面图。鳍切割填充结构包括如参照先前的附图描述的和先前的附图中示出的绝缘衬垫56和填充材料58。截面中示出的鳍切割填充结构横向地设置在栅极间隔件34之间并且垂直地延伸至相邻的隔离区域26(以虚线示出)的上表面的水平面之下一定深度。横向地，绝缘衬垫56设置在相应的栅极间隔件34和填充材料58之间以及切割鳍24的相应的段和填充材料58之间。垂直地，在示出的截面中，绝缘衬垫56设置在(i)半导体衬底20和/或鳍24的切割区域的剩余部分之间和(ii)填充材料58之间。垂直地，在另一截面(例如，穿过隔离区域26)中，绝缘衬垫56设置在隔离区域26(如虚线所示)和填充材料58之间。绝缘衬垫56共形地设置在填充材料58和形成在半导体衬底20上和/或从半导体衬底20形成的其他结构之间。
如图所示，鳍切割填充结构具有垂直尺寸D1，其从鳍切割填充结构的顶面延伸至相邻的隔离区域26(以虚线示出)的上表面的水平面之下一定深度。鳍切割填充结构在鳍切割填充结构的顶面处具有横向尺寸D2。在一些实例中，垂直尺寸D1在从约200nm至约320nm的范围内，并且横向尺寸D2在从约20nm至约25nm的范围内。在一些实例中，垂直尺寸D1与横向尺寸D2的高宽比大于或等于约10，诸如约13。
在一些实例中，鳍24的被切割的深度D3在从约130nm至约190nm的范围内。在一些实例中，鳍24的高度D4在从约40nm至约70nm的范围内。在一些实例中，一个或多个介电层36距鳍24的顶面的高度D5在从约70nm至约130nm的范围内。在一些实例中，鳍切割填充结构的上部处的绝缘衬垫56的厚度D6在从约2nm至约6nm的范围内，并且鳍切割填充结构的下部处的绝缘衬垫56的厚度D7在从约1.6nm至约6nm的范围内。在一些实例中，下部处的厚度D7与上部处的厚度D6的比率在从约1.0至约0.8的范围内。
一些实施例可以实现许多优势。通过使用高带隙材料作为鳍切割填充结构中的绝缘衬垫，可以减少切割的鳍的相邻段(例如，鳍的之间有鳍切割填充结构和邻接鳍切割填充结构的段)之间的泄漏。这可以使得晶圆允收测试(WAT)结果更好，并且由切割的鳍形成的器件的可靠性更高。可以实现其他优势。
实施例是一种结构。该结构包括位于衬底上的第一鳍、位于衬底上的第二鳍以及设置在第一鳍和第二鳍之间的鳍切割填充结构。第一鳍和第二鳍纵向对准。鳍切割填充结构包括绝缘衬垫和位于绝缘衬垫上的填充材料。绝缘衬垫邻接第一鳍的第一侧壁和第二鳍的第二侧壁。绝缘衬垫包括带隙大于5eV的材料。
另一实施例是一种结构。该结构包括横向设置在第一鳍和第二鳍之间的绝缘结构。第一鳍和第二鳍在衬底上纵向对准。绝缘结构包括沿着第一鳍和第二鳍的相应端部侧壁设置的高带隙衬垫，并且包括位于高带隙衬垫上的填充材料。高带隙衬垫具有大于5eV的带隙。
另一实施例是一种方法。在衬底上形成鳍。通过在鳍的第一段和鳍的第二段之间形成切割开口，将鳍切割成鳍的第一段和鳍的第二段。在切割开口中形成共形衬垫层。共形衬垫层包括带隙大于5eV的材料。在切割开口中的共形衬垫层上形成填充材料。
根据本发明的一些实施例，提供了一种半导体结构，包括：第一鳍，位于衬底上；第二鳍，位于所述衬底上，所述第一鳍和所述第二鳍纵向对准；以及鳍切割填充结构，设置在所述第一鳍和所述第二鳍之间，所述鳍切割填充结构包括：绝缘衬垫，邻接所述第一鳍的第一侧壁和所述第二鳍的第二侧壁，所述绝缘衬垫包括带隙大于5eV的材料；和填充材料，位于所述绝缘衬垫上。
在上述半导体结构中，所述绝缘衬垫的材料选自由氧化硅(SiOx)、氧化铝(Al2O3)、氧化钛(TiOx)、氧化钽(TaOx)、氟化铝(AlF)、氟氧化铝(AlOFx)、硅酸锆(ZrSiOx)、硅酸铪(HfSiOx)、氧化铪(HfO2)、氧化锆(ZrO2)或它们的组合组成的组。
在上述半导体结构中，所述填充材料是绝缘材料。
在上述半导体结构中，所述填充材料是氮化硅。
在上述半导体结构中，还包括：相邻隔离区域，所述第一鳍和所述第二鳍从所述相邻隔离区域之间突出，所述鳍切割填充结构的底面位于所述相邻隔离区域的相应的顶面之下。
在上述半导体结构中，所述鳍切割填充结构在所述鳍切割填充结构的顶面处具有宽度并且沿着所述第一鳍和所述第二鳍的纵向对准的方向，并且具有从所述鳍切割填充结构的顶面延伸至所述鳍切割填充结构的底面的深度，所述深度与所述宽度的比率至少为10。
在上述半导体结构中，还包括：第一栅极间隔件，在所述第一鳍的第一侧壁处在所述第一鳍上方延伸；第二栅极间隔件，在所述第二鳍的第二侧壁处在所述第二鳍上方延伸；以及栅极结构，设置在所述第一栅极间隔件和所述第二栅极间隔件之间，所述鳍切割填充结构横向设置在所述第一栅极间隔件和所述第二栅极间隔件之间，所述鳍切割填充结构邻接所述栅极结构。
在上述半导体结构中，还包括：栅极结构，位于所述栅极上方；栅极切割填充结构，设置在所述鳍切割填充结构和所述栅极结构之间并且邻接所述鳍切割填充结构和所述栅极结构。
根据本发明的另一些实施例，还提供了一种半导体结构，包括：绝缘结构，横向设置在所述第一鳍和所述第二鳍之间，所述第一鳍和所述第二鳍在衬底上纵向对准，所述绝缘结构包括：高带隙衬垫，沿着所述第一鳍和所述第二鳍的相应端部侧壁设置，所述高带隙衬垫具有大于5eV的带隙；以及填充材料，位于所述高带隙衬垫上。
在上述半导体结构中，还包括：第一隔离区域和第二隔离区域，所述第一鳍和所述第二鳍的每个均横向设置在所述第一隔离区域和所述第二隔离区域之间，所述高带隙衬垫在所述第一隔离区域和所述第二隔离区域的相应的顶面之下延伸。
在上述半导体结构中，所述绝缘结构进一步横向设置在第一栅极间隔件和第二栅极间隔件之间，所述第一栅极间隔件位于所述第一鳍的端部侧壁处的所述第一鳍上方，所述第二栅极间隔件位于所述第二鳍的端部侧壁处的所述第二鳍上方，所述高带隙衬垫进一步沿着所述第一栅极间隔件和所述第二栅极间隔件的相应的侧壁设置。
在上述半导体结构中，所述绝缘结构进一步横向设置在第一栅极结构和第二栅极结构之间，所述第一栅极结构和所述第二栅极结构在所述衬底上纵向对准。
在上述半导体结构中，所述高带隙衬垫的材料选自由氧化硅(SiOx)、氧化铝(Al2O3)、氧化钛(TiOx)、氧化钽(TaOx)、氟化铝(AlF)、氟氧化铝(AlOFx)、硅酸锆(ZrSiOx)、硅酸铪(HfSiOx)、氧化铪(HfO2)、氧化锆(ZrO2)或它们的组合组成的组；以及所述填充材料是氮化硅。
根据本发明的又一些实施例，还提供了一种形成半导体结构的方法，包括：在衬底上形成鳍；通过在所述鳍的第一段和所述鳍的第二段之间形成切割开口，将所述鳍切割成所述鳍的第一段和所述鳍的第二段；在所述切割开口中形成共形衬垫层，所述共形衬垫层包括带隙大于5eV的材料；以及在所述切割开口中的所述共形衬垫层上形成填充材料。
在上述方法中，形成所述共形衬垫层包括使用原子层沉积(ALD)工艺。
在上述方法中，所述共形衬垫层的材料选自由氧化硅(SiOx)、氧化铝(Al2O3)、氧化钛(TiOx)、氧化钽(TaOx)、氟化铝(AlF)、氟氧化铝(AlOFx)、硅酸锆(ZrSiOx)、硅酸铪(HfSiOx)、氧化铪(HfO2)、氧化锆(ZrO2)或它们的组合组成的组。
在上述方法中，所述填充材料是绝缘材料。
在上述方法中，还包括：在所述衬底上形成第一隔离区域和第二隔离区域，所述鳍从所述第一隔离区域和所述第二隔离区域之间突出，所述切割开口延伸至所述第一隔离区域和所述第二隔离区域的相应的顶面之下一定深度。
在上述方法中，形成所述切割开口包括去除栅极结构的至少部分，所述栅极结构的所述部分位于所述鳍上面。
在上述方法中，所述切割开口的高宽比至少为10。
上面概述了若干实施例的特征，使得本领域人员可以更好地理解本发明的方面。本领域人员应该理解，它们可以容易地使用本发明作为基础来设计或修改用于实施与本人所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，本文中它们可以做出多种变化、替换以及改变。

Claims (10)

1.一种半导体结构，包括：
第一鳍，位于衬底上；
第二鳍，位于所述衬底上，所述第一鳍和所述第二鳍纵向对准；以及
鳍切割填充结构，设置在所述第一鳍和所述第二鳍之间，所述鳍切割填充结构包括：
绝缘衬垫，邻接所述第一鳍的第一侧壁和所述第二鳍的第二侧壁，所述绝缘衬垫包括带隙大于5eV的材料；和
填充材料，位于所述绝缘衬垫上。
2.根据权利要求1所述的半导体结构，其中，所述绝缘衬垫的材料选自由氧化硅(SiOx)、氧化铝(Al2O3)、氧化钛(TiOx)、氧化钽(TaOx)、氟化铝(AlF)、氟氧化铝(AlOFx)、硅酸锆(ZrSiOx)、硅酸铪(HfSiOx)、氧化铪(HfO2)、氧化锆(ZrO2)或它们的组合组成的组。
3.根据权利要求1所述的半导体结构，其中，所述填充材料是绝缘材料。
4.根据权利要求1所述的半导体结构，其中，所述填充材料是氮化硅。
5.根据权利要求1所述的半导体结构，还包括：相邻隔离区域，所述第一鳍和所述第二鳍从所述相邻隔离区域之间突出，所述鳍切割填充结构的底面位于所述相邻隔离区域的相应的顶面之下。
6.根据权利要求1所述的半导体结构，其中，所述鳍切割填充结构在所述鳍切割填充结构的顶面处具有宽度并且沿着所述第一鳍和所述第二鳍的纵向对准的方向，并且具有从所述鳍切割填充结构的顶面延伸至所述鳍切割填充结构的底面的深度，所述深度与所述宽度的比率至少为10。
7.根据权利要求1所述的半导体结构，还包括：
第一栅极间隔件，在所述第一鳍的第一侧壁处在所述第一鳍上方延伸；
第二栅极间隔件，在所述第二鳍的第二侧壁处在所述第二鳍上方延伸；以及
栅极结构，设置在所述第一栅极间隔件和所述第二栅极间隔件之间，所述鳍切割填充结构横向设置在所述第一栅极间隔件和所述第二栅极间隔件之间，所述鳍切割填充结构邻接所述栅极结构。
8.根据权利要求1所述的半导体结构，还包括：
栅极结构，位于所述栅极上方；以及
栅极切割填充结构，设置在所述鳍切割填充结构和所述栅极结构之间并且邻接所述鳍切割填充结构和所述栅极结构。
9.一种半导体结构，包括：
绝缘结构，横向设置在所述第一鳍和所述第二鳍之间，所述第一鳍和所述第二鳍在衬底上纵向对准，所述绝缘结构包括：
高带隙衬垫，沿着所述第一鳍和所述第二鳍的相应端部侧壁设置，所述高带隙衬垫具有大于5eV的带隙；以及
填充材料，位于所述高带隙衬垫上。
10.一种形成半导体结构的方法，包括：
在衬底上形成鳍；
通过在所述鳍的第一段和所述鳍的第二段之间形成切割开口，将所述鳍切割成所述鳍的第一段和所述鳍的第二段；
在所述切割开口中形成共形衬垫层，所述共形衬垫层包括带隙大于5eV的材料；以及
在所述切割开口中的所述共形衬垫层上形成填充材料。
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