TW201436241A - 具有源極-汲極側壁間隔物並降低高度的鰭式場效電晶體 - Google Patents
具有源極-汲極側壁間隔物並降低高度的鰭式場效電晶體 Download PDFInfo
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- TW201436241A TW201436241A TW103108686A TW103108686A TW201436241A TW 201436241 A TW201436241 A TW 201436241A TW 103108686 A TW103108686 A TW 103108686A TW 103108686 A TW103108686 A TW 103108686A TW 201436241 A TW201436241 A TW 201436241A
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- 125000006850 spacer group Chemical group 0.000 title claims abstract description 127
- 239000004065 semiconductor Substances 0.000 claims abstract description 103
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- 238000002955 isolation Methods 0.000 claims description 36
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- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 claims description 22
- 229910001936 tantalum oxide Inorganic materials 0.000 claims description 22
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- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 claims description 15
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- BIXHRBFZLLFBFL-UHFFFAOYSA-N germanium nitride Chemical compound N#[Ge]N([Ge]#N)[Ge]#N BIXHRBFZLLFBFL-UHFFFAOYSA-N 0.000 claims 1
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- WOCIAKWEIIZHES-UHFFFAOYSA-N ruthenium(iv) oxide Chemical compound O=[Ru]=O WOCIAKWEIIZHES-UHFFFAOYSA-N 0.000 claims 1
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- NFFIWVVINABMKP-UHFFFAOYSA-N methylidynetantalum Chemical compound [Ta]#C NFFIWVVINABMKP-UHFFFAOYSA-N 0.000 description 4
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- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
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- 238000002513 implantation Methods 0.000 description 1
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- 229910052762 osmium Inorganic materials 0.000 description 1
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
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Classifications
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
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- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
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- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
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- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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- H01L29/4975—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 being a silicide layer, e.g. TiSi2
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- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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Abstract
一種積體電路裝置,包含半導體基板、延伸進入半導體基板的隔離區、突出於隔離區之上的半導體鰭片、閘極堆疊、以及鰭片間隔物。隔離區包含第一部分和第二部分,第一部分與第二部分位於半導體鰭片的相對兩側,其中半導體鰭片具有第一高度。閘極堆疊與半導體鰭片的中間部份重疊。鰭片間隔物位於半導體鰭片末端的側壁上。鰭片間隔物具有第二高度,其中第一高度大於第二高度的兩倍。
Description
本發明是關於一種積體電路裝置,特別是關於一種電晶體。
電晶體是現代積體電路的關鍵元件。為了達到愈來愈快的速度的需求,電晶體的驅動電流也隨之增大。由於電晶體的驅動電流與電晶體閘極寬度成正比,因此電晶體偏好擁有較寬的閘極寬度。
然而,電晶體閘極寬度的增加抵觸了縮小半導體元件尺寸的需求。因此鰭式場效電晶體(fin field-effect transistor,finFET)開始發展。藉由形成鰭片作為鰭式場效電晶體的通道區,不需要佔用更多晶片面積,即可以增大電晶體的驅動電流。
然而,鰭式場效電晶體具有某些缺點。隨著鰭式場效電晶體尺寸的縮小,鰭片的縮小造成源極/汲極區電阻的增加,因此降低了積體電路裝置的驅動電流。在接觸插塞和源極/汲極矽化物區之間的接觸電阻,也因為鰭片面積的縮小而增加。此外,接觸插塞和鰭式場效電晶體之源極/汲極矽化物區間的連接並不容易。這是因為鰭式場效電晶體
的鰭片面積很小,接觸插塞對應的著陸區也因此很小。要將接觸插塞精準地著陸於鰭片上的製程窗口也很小,這表示在沒有改變既有鰭式場效電晶體的可靠性前,幾乎不容許製程中有任何的變動。
本發明之一實施方案提出一種積體電路裝置,包含半導體基板、延伸進入半導體基板的隔離區、突出於隔離區之上的半導體鰭片、閘極堆疊、以及鰭片間隔物。其中,隔離區包含第一部分和第二部分,第一部分和第二部分位於半導體鰭片的相對兩側。半導體鰭片具有第一高度。閘極堆疊與半導體鰭片的中間部份重疊。鰭片間隔物位於半導體鰭片末端部分的側壁上。鰭片間隔物具有第二高度,其中第一高度約高於第二高度的兩倍。
本發明之另一實施方案提出一種積體電路裝置,包含半導體基板、延伸進入半導體基板的隔離區、以及鰭式場效電晶體。鰭式場效電晶體包含位於隔離區之上的半導體鰭片。隔離區包含第一部分和第二部分,其中第一部分和第二部分位於半導體鰭片的相對兩側。半導體鰭片具有第一高度。鰭式場效電晶體更包含位於半導體鰭片中間部份的閘極堆疊、位於半導體鰭片末端上的源極/汲極區、以及位於源極/汲極區側壁上的鰭片間隔物。鰭片間隔物具有第二高度,其中第一高度約高於兩倍的第二高度。鰭式場效電晶體更包含源極/汲極矽化物層,源極/汲極矽化物層具
有源極/汲極區側壁上的側壁部分,其中源極/汲極矽化物層的底端接觸第一鰭片間隔物的頂端。
本發明之又一實施方案提出一種積體電路裝置的製作方法,包含形成覆蓋於半導體鰭片中間部分上的閘極堆疊、形成位於閘極堆疊和半導體鰭片之上的閘極間隔物、以及圖案化閘極間隔層,用以形成位於閘極堆疊側壁之上的閘極間隔物,以及半導體鰭片末端部分之側壁部分上的鰭片間隔物。鰭片間隔物經過蝕刻,當完蝕刻後,鰭片間隔物之第一高度小於約半導體鰭片之第二高度之一半。
20‧‧‧半導體基板
21‧‧‧部分
22‧‧‧隔離區
24‧‧‧半導體鰭片
241‧‧‧中間部分
242‧‧‧末端部分
30‧‧‧閘極堆疊
34‧‧‧閘極介電層
36‧‧‧閘極電極層
38‧‧‧遮罩層
40‧‧‧閘極介電層
42‧‧‧閘極電極層
44‧‧‧遮罩層
48‧‧‧間隔層
50‧‧‧矽氧化物層
52‧‧‧矽氮化物層
54‧‧‧閘極間隔物
56‧‧‧鰭片間隔物
60‧‧‧氧化物部分
62‧‧‧氮化物部分
64‧‧‧源極/汲極區
66‧‧‧矽化物層
68‧‧‧層間介電層
70‧‧‧接觸插塞
72‧‧‧鰭式場效電晶體
T1、T2‧‧‧厚度
Hc1、Hc2、Hc3‧‧‧高度
第1圖至第9B圖是本發明一實施例之鰭式場效電晶體製程中多個階段的截面圖和透視圖。
以下將以圖式及詳細說明清楚說明本發明之精神,任何所屬技術領域中具有通常知識者在瞭解本發明之較佳實施例後,當可由本發明所教示之技術,加以改變及修飾,其並不脫離本發明之精神與範圍。
本發明提供了鰭式場效電晶體和鰭式場效電晶體之製作方法,也提供鰭式場效電晶體製程的中間階段,並且討論鰭式場效電晶體的變動和個別製作的方法。下文係
舉實施例配合所附圖式作詳細說明,但所提供之實施例並非用以限制本案所涵蓋的範圍,而結構運作之描述非用以限制其執行之順序,任何由元件重新組合之結構,所產生具有均等功效的裝置,皆為本案所涵蓋的範圍。此外,圖式僅以說明為目的,並未依照原尺寸作圖。為使便於理解,下述說明中相同元件將以相同之符號標示來說明。
參照第1圖,提供半導體基板20。半導體基板20可以是一大塊的矽基板、一大塊的矽鍺基板等等。形成隔離區22以延伸進入半導體基板20。在某些實施方案中,隔離區22的形成包含藉由凹陷半導體基板20於半導體基板20中形成數個溝槽,接著用介電材料注滿溝槽。隔離區22可能包含數個氧化物,其形成來自如高密度電漿(HDP)和可流動化學氣象沉積(FCVD)等等的使用。在某些實施方案的範例中,隔離區22包含矽氧化物(SiO2)、矽氮化物、或矽氧化物和矽氮化物的多層堆疊。以下隔離區22亦可稱作淺溝槽隔離區22。
如第2圖,淺溝槽隔離區22是凹陷的。因此部份的半導體基板20突出淺溝槽隔離區22的頂面之上,形成半導體鰭片24。在某些實施方案的範例中,半導體鰭片24的高度H1在約100Å和約900Å之間。然而,就該領域的專家所知,高度的數值僅是由記載中抄錄下的範例而已,事實上高度的數值會隨著積體電路尺寸縮小的比例而變動。
在某些選擇性的實施方案中,在製作淺溝槽隔離區
22凹陷之前,半導體基板20的一部分21(見第1圖)將由另一種異於半導體基板20的材料所取代。在某些實施方案的範例中,半導體基板20的一部分21將先經由蝕刻移除,如此一來即形成凹陷。其次,利用磊晶技術在既有凹陷中重新生長另一種半導體材料,之後再進行化學機械研磨(chemical mechanical polish,CMP)。重新生長的半導體材料可能包含矽鍺、半導體III-V族化合物材料等等。因此,半導體鰭片24和半導體基板20包含不同的材料。
參照第3圖,形成閘極堆疊30,其中包含閘極介電層34、閘極電極層36、和遮罩層38。在某些實施方案中,閘極介電層34包含矽氧化物,可能是由半導體鰭片24的熱氧化形成。在其餘的實施方案中,閘極介電層34是由沉積法所製成,並且可能包含介電常數(k值)等於或高於3.8的介電材料。可用於形成閘極介電層34的材料包含矽氧化物、矽氮化物、氮氧化物、和金屬氧化物,例如HfO2、HfZrOx、HfSiOx、HfTiOx、HfAlOx、以及以上材料的組合和多層堆疊。
在某些實施方案中,閘極電極層36是由多晶矽所形成。在其餘的實施方案中,閘極電極層36包含材料選自金屬氮化物(例如一氮化鈦(TiN)、一氮化鉭(TaN)、和氮化鉬(MoNx))、金屬碳化物(例如碳化鉭(TaC)和碳化鉿(HfC))、金屬碳氮化物(例如TaCN)、金屬氧化物(例如氧化鉬(MoOx))、金屬氮氧化物(例如氮氧化鉬(MoOxNy))、金屬矽化物(例如矽化鎳)、以及以上材料的組合。閘極電極層
36也可以是一層冠有多晶矽層的金屬層。
依據某些實施方案,遮罩層38可以進一步形成於閘極電極層36之上。遮罩層38可能包含矽氮化物。換句話說,遮罩層38可以使用不同於隨後形成鰭片間隙物的其他材料。
其次,圖案化閘極堆疊30以形成閘極介電層40、閘極電極層42、和遮罩層44。第4圖為說明既有結構的透視圖。為了形成鰭式場效電晶體裝置,閘極介電層40、閘極電極層42和遮罩層44覆蓋於半導體鰭片24中間部分241上,其中鰭片24的末端部分242並未受到覆蓋。末端部分242位於中間部分241的相對兩側。
接著,參照第5圖,間隔層48用以作為一毯覆層。第5圖沿著第4圖線段A-A的截面圖。據此,閘極電極層42(第4圖)將不會展現在此說明圖中。在某些實施方案中,間隔層48包含矽氧化物層50和矽氧化物層50之上的矽氮化物層52。在另一些實施方案中,間隔層48可能由其他介電材料形成,並且/或具有其他結構。例如,間隔層48可能是單層的矽氧化物層或矽氮化物層等等。間隔層48基本上是保形層,因此半導體鰭片24和閘極堆疊30側壁上的間隔層48垂直部分的厚度T1,接近於間隔層48水平部分的厚度T2。例如,厚度T1和T2的差值可能小於厚度T2的20%。
接著,參照第6A圖和第6B圖,圖案化間隔層48,形成閘極間隔物54和鰭片間隔物56。第6A圖和第6B圖
分別為示意圖和截面圖,其中第6B圖為第6A圖線段6B-6B的剖面圖。在某些實施範例中,間隔層48(第5圖)包含矽氧化物層50和矽氮化物層52,其中矽氮化物層52(如第6圖)的圖案化包含使用CH2F2作為侵蝕劑的乾式蝕刻,而矽氧化物層50的圖案化則包含使用CF4作為侵蝕劑的乾式蝕刻,不排除仍有其他可使用的侵蝕劑。圖案化包含各向異性(anisotropic)的效果,因此一方面移除間隔層48的水平部分,一方面保留閘極堆疊30側壁上的垂直部分,以形成閘極間隔物54。連帶地,保留之半導體鰭片24側壁上之垂直部分會形成鰭片間隔物56。鰭片間隔物56和閘極間隔物54可以包含氧化物部分60和氮化物部分62,分別是矽氧化物層50(第5圖)和矽氮化物層52的保留部份。
在某些程序中,移除間隔層48的水平部分後,更包含完成間隔層48的圖案化,因此半導體鰭片24的上邊緣會水平齊於既有鰭片間隔物56的上邊緣。換句話說,在個別的鰭式場效電晶體中,半導體鰭片24的高度Hc1與鰭片間隔物56的高度Hc2一樣。在本發明的某些實施範例中,在第6A圖和第6B圖中的結構形成後,間隔層48繼續圖案化,如此一來鰭片間隔物56變得更薄,且其高度變低。同時,閘極間隔物54的高度也降低。然而,因為閘極間隔物54遠高於鰭片間隔物56,因此,按百分比而言,降低閘極間隔物54之高度的重要性並不如降低鰭片間隔物56之高度重要。在某些實施範例中,鰭片間隔物56的細薄化包含蝕刻步驟。如第6A圖和第6B圖中的蝕刻步驟,蝕刻步
驟可能透過相同或相似的程序條件和侵蝕劑氣體而實行,但不排除可以使用不同的程序條件。例如,連續的蝕刻可以是各向異性的蝕刻。為了防止閘極間隔物54過度蝕刻,可以在鰭片間隔物56仍有某些部分殘留時,即停止連續的圖案化。
第7A圖為鰭片間隔物56細薄化完成後的示意圖。第7B圖為沿著第7A圖之線段7B-7B的截面圖。作為細薄化後的結果,鰭片間隔物56的高度降低至Hc3。在某些實施範例中,半導體鰭片24之高度Hc1為鰭片間隔物56之高度Hc3的約2倍至約10倍間。更進一步的說,在某些實施範例中,兩高度的差(Hc1-Hc3)可能大於約10nm。
在某些實施範例中,其中間隔層48(第5圖)包含矽氧化物層50和矽氮化物層52,如第5圖、第6A圖、第6B圖所示,根據採用蝕刻矽氧化物層50和矽氮化物層52的程序條件不同,保留的鰭片間隔物56可能具有不同的結構。在某些實施範例中,鰭片間隔物56包含矽氧化物層50的保留部分,但並不包含矽氮化物層52的保留部分。在另某些實施範例中,鰭片間隔物56包含矽氧化物層50的保留部分和矽氮化物層52保留的部分。另一方面,閘極間隔物54則皆包含矽氧化物層50的保留部分和矽氮化物層52的保留部分。
因為閘極間隔層48(第5圖)和淺溝槽隔離區22是使用不同的程序步驟、不同的方法、和/或包含不同的材料所形成,鰭片間隔物56和淺溝槽隔離區22可能具有可分
辨的多個明顯介面,例如用電子顯微鏡可以辨別。舉例而言,儘管淺溝槽隔離區22和矽氧化物層50皆由矽氧化物所形成,但矽氧化物層50的密度可能會高於淺溝槽隔離區22的密度,因此可以分辨鰭片間隔物56和淺溝槽隔離區22間的介面。
閘極間隔物54和鰭片間隔物56是透過圖案化同樣的閘極間隔層48(第5圖)所形成。因此,閘極間隔物54和鰭片間隔物56連續地連接彼此,閘極間隔物54和鰭片間隔物56之間沒有明顯介面分隔兩者。更確切地說,鰭片間隔物56具有外側壁,外側壁之高度逐漸降低,並且鰭片間隔物56之外側部分的高度分別小於內側部分的高度。
在形成閘極間隔物54之後,接著進行植入步驟,將半導體鰭片24的暴露末端部分242植入,用以形成源極/汲極區64。依據理想的既有鰭式場效電晶體型態,將p型雜質進行植入以形成p型鰭式場效電晶體,或者將n型雜質進行植入以形成n型鰭式場效電晶體。
第8圖說明矽化程序,矽化半導體鰭片24的表面並且形成矽化物層66。第8圖的剖面位置同第7A圖中線段7B-7B的平面。在某些矽化程序的範例中,首先沉積一層薄金屬(圖中未繪示),例如鎳、鉑、鈀、釩、鈦、鈷、鉭、鐿、鋯、或是以上材料之組合。接著,加熱該基板,使矽和鍺在接觸金屬的地方與金屬反應。經過反應後,在源極/汲極區64的頂面和側壁上形成金屬矽化物層66,這也屬於半導體鰭片24的一部分。透過侵蝕劑的使用,選擇性地移
除未反應的金屬,侵蝕劑僅侵蝕金屬並不侵蝕矽化物。其後的矽化物層66包含位於半導體鰭片24頂面上的頂面部分和位於半導體鰭片24側壁上之側壁部分。矽化物層66的側壁部分具有底端,底端會自動對準鰭片間隔物56之頂端。因此,個別的矽化程序是自動對準矽化(Salicide)。
第9A圖說明了層間介電層(inter-layer dielectric,ILD)68和層間介電層68中的接觸插塞70的形成。在某些實施方案中,層間介電層68首先形成用以覆蓋第8圖中之結構。層間介電層68可能包含矽氧化物、矽碳化物、一低K介電材料、磷矽酸鹽玻璃(PSG)、硼矽酸鹽玻璃(BSG)、硼磷矽玻璃(BPSG)、四乙基氧矽烷(TEOS)氧化物等等。接著,層間介電層68中形成一接觸開口(由接觸插塞70佔用),用以露出矽化物層66的頂面部分和側壁部分。再者,將金屬灌入接觸開口,再進行化學機械研磨(CMP),用以移除多餘的金屬並水平對齊接觸插塞70的頂面。第9B圖是鰭式場效電晶體的俯視圖,說明閘極介電層40、閘極電極層42、閘極間隔物54、鰭片間隔物56和接觸插塞70的位置。第9A圖是來自第9B圖中包含線9A-9A的平面。倘若移除遮罩層44(第5圖),會形成閘極接觸插塞(圖中未展示),用以電性連接閘極電極層42。因而,形成鰭式場效電晶體72。
如第9A圖所述,接觸插塞70電性連接矽化物層66的側壁部分和頂面部分。因此,在操作既有的鰭式場效電晶體72時,電流可能會流經矽化物層66和半導體鰭片
24的側壁部分和頂面部分。因而降低電流擁擠程度。相較之下,若鰭片間隔物56具有如第6B圖中一樣的高度,則源極/汲極矽化物將會在半導體鰭片24的頂面上形成,而非在半導體鰭片24的側壁上,因此可能會產生電流擁擠效應。模擬結果顯示,藉由使用本發明的實施方案,流經鰭式場效電晶體的每個鰭片的It2電流(一鰭片在靜電放電應力下可以承受的最大電流),可以增加約25%。
綜上所述,本發明之一實施方案提出一種積體電路裝置,包含半導體基板、延伸進入半導體基板的隔離區、突出於隔離區之上的半導體鰭片、閘極堆疊、以及鰭片間隔物。其中,隔離區包含第一部分和第二部分,第一部分和第二部分位於半導體鰭片的相對兩側。半導體鰭片具有第一高度。閘極堆疊與半導體鰭片的中間部份重疊。鰭片間隔物位於半導體鰭片末端部分的側壁上。鰭片間隔物具有第二高度,其中第一高度約高於第二高度的兩倍。
本發明之另一實施方案提出一種積體電路裝置,包含半導體基板、延伸進入半導體基板的隔離區、以及鰭式場效電晶體。鰭式場效電晶體包含位於隔離區之上的半導體鰭片。隔離區包含第一部分和第二部分,其中第一部分和第二部分位於半導體鰭片的相對兩側。半導體鰭片具有第一高度。鰭式場效電晶體更包含位於半導體鰭片中間部份的閘極堆疊、位於半導體鰭片末端上的源極/汲極區、以及位於源極/汲極區側壁上的鰭片間隔物。鰭片間隔物具有第二高度,其中第一高度約高於兩倍的第二高度。鰭式場
效電晶體更包含源極/汲極矽化物層,源極/汲極矽化物層具有源極/汲極區側壁上的側壁部分,其中源極/汲極矽化物層的底端接觸第一鰭片間隔物的頂端。
本發明之又一實施方案提出一種積體電路裝置的製作方法,包含形成覆蓋於半導體鰭片中間部分上的閘極堆疊、形成位於閘極堆疊和半導體鰭片之上的閘極間隔物、以及圖案化閘極間隔層,用以形成位於閘極堆疊側壁之上的閘極間隔物,以及半導體鰭片末端部分之側壁部分上的鰭片間隔物。鰭片間隔物經過蝕刻,當完蝕刻後,鰭片間隔物之第一高度小於約半導體鰭片之第二高度之一半。
雖已詳細陳述實施方案和其優點,但在沒有遠離申請專利範圍所定義的實施方案的精神和範圍下,有各種的變化、成分和轉化可以進行。再者,本發明的應用範圍並沒有限制在上述提到的規格中,如程序、機器、製造方法、以及物質、手段、方法和步驟的編制之特定的實施方案。在該領域的普通技術人員可以預期,藉由本發明之相關實施方案,使目前存在或往後將被發展的發明、程序、機器、製造方法、以及物質、手段、方法或步驟的編制,可以達到如敘述中對應的實施方案基本的功能和效果。據此,追加的申請專利範圍中擬包含範圍例如程序、機器、製造方法、以及物質、手段、方法或步驟的編制。此外,每項申請專利範圍構成一獨立的實施方案,並且各項申請專利範圍和實施方案的組合皆屬於本次發明的範圍。
20‧‧‧半導體基板
22‧‧‧隔離區
24‧‧‧半導體鰭片
242‧‧‧末端部分
30‧‧‧閘極堆疊
40‧‧‧閘極介電層
42‧‧‧閘極電極層
44‧‧‧遮罩層
54‧‧‧閘極間隔物
56‧‧‧鰭片間隔物
60‧‧‧氧化物部分
62‧‧‧氮化物部分
Hc1、Hc2‧‧‧高度
Claims (10)
- 一種積體電路裝置(integrated circuit device),包含:一半導體基板;複數個隔離區,延伸進入該半導體基板;一半導體鰭片,突出於該些隔離區,其中該些隔離區包含一第一部分和一第二部分,該第一部分與該第二部分位於該半導體鰭片之相對兩側,其中該半導體鰭片具有一第一高度;一閘極堆疊,位於該半導體鰭片之一中間部分;以及一第一鰭片間隔物,位於該半導體鰭片之一末端之側壁上,其中該第一鰭片間隔物具有一第二高度,其中該第一高度高於約兩倍之該第二高度。
- 如申請專利範圍第1項所述之積體電路裝置,更包含一閘極間隔物,位於該閘極堆疊之側壁上,其中該閘極間隔物連接該第一鰭片間隔物,其中該閘極間隔物是連續地連接該第一鰭片間隔物,該閘極間隔物與該第一鰭片間隔物之間沒有介面,而其中該第一高度與該第二高度的比例在大約2與大約10之間,該第一鰭片間隔物與該隔離區的該第一部分交疊。
- 如申請專利範圍第1項所述之積體電路裝置,更包含:一金屬矽化物層,包含: 一頂面部分,位於該半導體鰭片之該末端的頂面;以及一側壁部分,位於該半導體鰭片之該末端的側壁上,其中該金屬矽化物層的底端接觸該第一鰭片間隔物的頂端;以及一第二鰭片間隔物,其中該半導體鰭片之該末端構成鰭式場效電晶體的源極區/汲極區,並且該第一鰭片間隔物與第二鰭片間隔物接觸該源極區/汲極區的相對側壁。
- 一種積體電路裝置,包含:一半導體基板;複數個隔離區,延伸進入該半導體基板;以及一鰭式場效電晶體,包含:一半導體鰭片,該半導體鰭片位於該些隔離區之上,其中該些隔離區包含一第一部分與一第二部分,該第一部分與該第二部分位於半導體鰭片之相對兩側,且該半導體鰭片具有第一高度;一閘極堆疊,位於該半導體鰭片之一中間部分;一源極區/汲極區,位於該半導體鰭片之一末端;一第一鰭片間隔物,位於該源極區/汲極區的側壁上,其中該第一鰭片間隔物具有一第二高度,其中該第一高度高於約兩倍之該第二高度;以及一源極/汲極矽化物層,包含位於該源極區/汲極區的側壁上的一側壁部分,其中該源極/汲極矽化物層的 底端接觸該第一鰭片間隔物的頂端。
- 如申請專利範圍第4項所述之積體電路裝置,更包含:一接觸插塞,該接觸插塞包含:一第一部分,與該源極區/汲極區重疊;以及一第二部分,位於該源極區/汲極區之一側,其中該接觸插塞的該第二部分接觸該源極/汲極矽化物層的該側壁部分其中該接觸插塞接觸該第一鰭片間隔物的一側壁;以及一第二鰭片間隔物,其中該第一鰭片間隔物與該第二鰭片間隔物接觸該源極區/汲極區之相對側壁。
- 如申請專利範圍第4項所述之積體電路裝置,其中該第一鰭片間隔物與該些隔離區的該第一部分重疊,並且該第一鰭片間隔物的底面和該些隔離區的該第一部分的頂面間具有一明顯的介面,其中該第一鰭片間隔物包含一矽氧化物層,並且該矽氧化物層接觸部份的該些隔離區,其中該第一鰭片間隔物更包含一矽氮化物層,並且該矽氮化物層位於該矽氧化物層的一水平接腳與一垂直接腳之間。
- 一種積體電路裝置的製作方法,包含:形成一閘極堆疊,覆蓋一半導體鰭片的一中間部分;形成一閘極間隔層,位於該閘極堆疊與該半導體鰭片之間,其中形成該閘極間隔層的步驟,包含沉積一矽氧化 物層和沉積一矽氮化物層於該矽氧化物層上;圖案化該閘極間隔層,用以形成:一閘極間隔物,位於該閘極堆疊的一側壁上;以及一鰭片間隔物,位於該半導體鰭片的一末端的一側壁上;以及蝕刻該鰭片間隔物,其中當蝕刻該鰭片間隔物的步驟完成後,該鰭片間隔物的一第一高度小於該半導體鰭片的一第二高度的一半。
- 如申請專利範圍第7項所述之方法,當蝕刻該鰭片間隔物的步驟完成後,該第二高度與該第一高度的比例在約2至約10之間,其中當蝕刻該鰭片間隔物的步驟完成後,該閘極堆疊具有該矽氧化物層的一第一殘留部分和該矽氮化物層的一第一殘留部分,其中該鰭片間隔物具有該矽氧化物層的一第二殘留部分和該矽氮化物層的一第二殘留部分。
- 如申請專利範圍第7項所述之方法,而當蝕刻該鰭片間隔物的步驟完成後,該閘極堆疊具有該矽氧化物層的一第一殘留部分和該矽氮化物層的一第一殘留部分,其中該鰭片間隔物則具有該矽氧化物層的一第二殘留部分,並且該鰭片間隔物無任何該矽氮化物層的殘留部分。
- 如申請專利範圍第7項所述之方法,更包含:將該半導體鰭片之一末端進行植入,用以形成一源極區/汲極區,其中該鰭片間隔物接觸該源極區/汲極區的一側壁;該鰭片間隔物蝕刻完成後,實行一矽化步驟,用以矽化該半導體鰭片之該末端的頂面和側壁表面,其中經過該矽化步驟後,形成一矽化物層,該矽化物層包含一頂面部分和一側壁部分;以及形成一接觸插塞,用以連接該矽化物層的該頂面部分和該側壁部分。
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US20070102756A1 (en) | 2005-11-10 | 2007-05-10 | Bohumil Lojek | FinFET transistor fabricated in bulk semiconducting material |
US8716797B2 (en) * | 2009-11-03 | 2014-05-06 | International Business Machines Corporation | FinFET spacer formation by oriented implantation |
US8557692B2 (en) | 2010-01-12 | 2013-10-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET LDD and source drain implant technique |
US8169025B2 (en) | 2010-01-19 | 2012-05-01 | International Business Machines Corporation | Strained CMOS device, circuit and method of fabrication |
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2013
- 2013-11-26 US US14/090,763 patent/US9209302B2/en active Active
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2014
- 2014-03-12 TW TW103108686A patent/TWI523237B/zh active
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2015
- 2015-12-07 US US14/961,048 patent/US9548367B2/en active Active
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2017
- 2017-01-04 US US15/398,576 patent/US9887275B2/en active Active
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
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TWI575742B (zh) * | 2015-02-26 | 2017-03-21 | 台灣積體電路製造股份有限公司 | 鰭式場效電晶體元件結構與其形成方法 |
TWI681563B (zh) * | 2015-04-14 | 2020-01-01 | 南韓商三星電子股份有限公司 | 半導體裝置 |
US10622444B2 (en) | 2015-04-14 | 2020-04-14 | Samsung Electronics Co., Ltd. | FinFET semiconductor device with a dummy gate, first gate spacer and second gate spacer |
US11515390B2 (en) | 2015-04-14 | 2022-11-29 | Samsung Electronics Co., Ltd. | Semiconductor devices |
US11610966B2 (en) | 2015-04-14 | 2023-03-21 | Samsung Electronics Co., Ltd. | Semiconductor devices |
Also Published As
Publication number | Publication date |
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US9887275B2 (en) | 2018-02-06 |
TWI523237B (zh) | 2016-02-21 |
US20170117390A1 (en) | 2017-04-27 |
US9209302B2 (en) | 2015-12-08 |
US20160093705A1 (en) | 2016-03-31 |
US20140264604A1 (en) | 2014-09-18 |
US9548367B2 (en) | 2017-01-17 |
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