CN106449762A - 用于finfet间隔物成型的集成工艺 - Google Patents

用于finfet间隔物成型的集成工艺 Download PDF

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CN106449762A
CN106449762A CN201611167849.3A CN201611167849A CN106449762A CN 106449762 A CN106449762 A CN 106449762A CN 201611167849 A CN201611167849 A CN 201611167849A CN 106449762 A CN106449762 A CN 106449762A
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fin
oxide layer
oxide
sin
low energy
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易海兰
雷通
陈勇跃
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Shanghai Huali Microelectronics Corp
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Abstract

介绍了一种新型等离子工艺作为在FinFET器件的间隔物成型期间常规等离子体工艺的改进。在此新型等离子体工艺下，在侧壁材料上生长氧化层并使用低能量等离子体气体对侧壁的拐角区域进行过度蚀刻。该氧化层可在通过低能量等离子体气体过度蚀刻的过程中有效保护侧壁材料，由此降低低能量等离子体气体引起的上述CD损耗。此改进的低能量等离子体蚀刻技术相比于传统低能量等离子体工艺可保护鳍结构不受CD损耗，并且相比于传统高能量等离子体工艺也以降低的Si损耗避免了损害鳍硅结构。

Description

用于FINFET间隔物成型的集成工艺
技术领域
本发明涉及半导体工艺与器件。
背景技术
自从早年德州仪器的Jack Kilby博士发明了集成电路之时起，科学家们和工程师们已经在半导体器件和工艺方面作出了众多发明和改进。近50年来，半导体尺寸已经有了明显的降低，这转化成不断增长的处理速度和不断降低的功耗。迄今为止，半导体的发展大致遵循着摩尔定律，摩尔定律大致是说密集集成电路中晶体管的数量约每两年翻倍。现在，半导体工艺正在朝着20nm以下发展，其中一些公司正在着手14nm工艺。这里仅提供一个参考，一个硅原子约为0.2nm，这意味着通过20nm工艺制造出的两个独立组件之间的距离仅仅约为一百个硅原子。
半导体器件制造因此变得越来越具有挑战性，并且朝着物理上可能的极限推进。华力微电子有限公司TM是致力于半导体器件和工艺研发的领先的半导体制造公司之一。
鳍式场效应晶体管(FinFET)器件包括使用凸起的源-漏沟道区域(被称为鳍)的晶体管架构。FinFET器件可构建于绝缘体上硅(SOI)衬底上，其中诸如硅之类的半导体材料被图案化为鳍形形状并起到晶体管沟道的作用。栅极可包覆在鳍周围和上方。双栅极结构或双重栅极结构包括形成在沟道两侧上的栅极氧化物和栅极触点。3D的三栅极FinFET包括包覆在鳍的三个侧面上的栅极结构。不同于2D平面FET，在3D FinFET器件中，沟道垂直于半导体衬底的上表面形成，由此降低了FinFET器件的物理尺寸。因此，3D三栅极FinFET结构有效地克服了FinFET器件的晶体管尺寸问题并改善了器件性能。然而相比于2D平面FinFET，3D三栅极FinFET器件的三栅极和垂直鳍结构会增加集成3D三栅极FinFET器件的难度。
例如，蚀刻毗邻栅极的氮化物间隔物是FinFET器件集成工艺中的关键挑战之一。常用的蚀刻氮化物间隔物的方法是等离子体蚀刻。可用在等离子体工艺中移除多晶硅的蚀刻剂包括单独的HCl、HBr、HI和Cl2、或者与彼此和/或He,Ar,Xe,N2和O2中的一个或多个的组合。可用于移除氧化硅的合适蚀刻剂是包括CF4/CHF3或CF4/CH2F2的等离子体。移除氮化硅的合适的蚀刻剂是包括CF4/HBr的等离子体。在等离子体工艺的操作中，等离子体气体可流入到内部腔室中并且通过来自反应线圈的能量输入被转换为等离子体。可在衬底上生成合适的RF偏置以将等离子体组分汲取到衬底的表面以蚀刻此表面上的材料。随着蚀刻的进行，可监视释出的反应产物和/或蚀刻剂气体的浓度。蚀刻剂残骸的监视可通过例如分光镜法实现，例如包括紫外可视光谱分析和质谱分析。
发明内容
以下给出一个或多个方面的简要概述以提供对这些方面的基本理解。此概述不是所有构想到的方面的详尽综览，并且既非旨在指认出所有方面的关键性或决定性要素亦非试图界定任何或所有方面的范围。其唯一的目的是要以简化形式给出一个或多个方面的一些概念以为稍后给出的更加详细的描述之序。
根据本发明的一方面，提供了一种用于制造3D鳍场效应晶体管FinFET器件的方法，该方法包括在衬底之上提供鳍形硅；提供包覆在该鳍形硅的三个侧面周围的栅极结构；在该栅极结构和该鳍形硅的整个表面之上沉积氮化硅SiN层；在该SiN层的整个表面之上沉积氧化层；执行氧化物蚀刻工艺以移除该SiN层的表面上在该鳍形硅上方的氧化层部分；执行SiN蚀刻工艺以移除该鳍形硅上方的SiN层部分；以及执行氧化物移除工艺以移除该SiN层上垂直方向上的氧化物层部分，以使垂直方向上的该SiN层至少形成该栅极结构的侧壁间隔物。
附图说明
图1解说常规3D三栅极FinFET(鳍式场效应晶体管)器件的一部分。
图2解说在一些常规FinFET制造工艺中所含的侧壁蚀刻工艺中可采用低能量等离子体气体以平滑拐角。
图3解说在一些FinFET常规工艺中的侧壁蚀刻工艺中可采用高能量等离子体气体以平滑拐角。
图4A大致解说可在改进的低能量等离子体工艺中在栅极结构之上沉积氮化硅层从而形成该栅极结构的间隔物。
图4B解说可在SiN层的整个表面之上生长氧化层以使其覆盖SiN层。
图4C解说可执行选择性湿法蚀刻工艺以移除氧化层。
图4D解说可释放低能量等离子体气体以蚀刻侧壁上水平方向上的SiN材料。
图4E解说可使用湿法蚀刻工艺或SiCoNi工艺移除侧壁上剩余的氧化层以获得间隔物。
参照以下附图，可实现对各个实施例的本质和优点的进一步理解。在附图中，类似组件或特征可具有相同的附图标记。此外，相同类型的各个组件可通过在附图标记后跟随破折号以及在类似组件间进行区分的副标记来区分。如果在说明书中仅使用第一附图标记，则该描述适用于具有相同第一附图标记的任何一个类似组件而不管副附图标记。
具体实施方式
本公开内容涉及在具有不同栅极节距尺寸的集成电路产品上制造间隔物结构以及结果得到的产品。
给出以下描述以使得本领域技术人员能够实施和使用本发明并将其结合到具体应用背景中。各种变型、以及在不同应用中的各种使用对于本领域技术人员将是容易显见的，并且本文定义的一般性原理可适用于较宽范围的实施例。由此，本发明并不限于本文中给出的实施例，而是应被授予与本文中公开的原理和新颖性特征相一致的最广义的范围。
在以下详细描述中，阐述了许多特定细节以提供对本发明的更透彻理解。然而，对于本领域技术人员显而易见的是，本发明的实践可不必局限于这些具体细节。换言之，公知的结构和器件以框图形式示出而没有详细显示，以避免模糊本发明。
请读者注意与本说明书同时提交的且对公众查阅本说明书开放的所有文件及文献，且所有这样的文件及文献的内容以参考方式并入本文。除非另有直接说明，否则本说明书(包含任何所附权利要求、摘要和附图)中所揭示的所有特征皆可由用于达到相同、等效或类似目的的可替代特征来替换。因此，除非另有明确说明，否则所公开的每一个特征仅是一组等效或类似特征的一个示例。
而且，权利要求中未明确表示用于执行特定功能的装置、或用于执行特定功能的步骤的任意组件皆不应被理解为如35 USC第112章节第6段中所规定的装置或步骤条款。特别地，在此处的权利要求中使用“….的步骤”或“….的动作”并不表示涉及35 USC第112章第6段的规定。
注意，在使用到的情况下，标志左、右、前、后、顶、底、正、反、顺时针和逆时针仅仅是出于方便的目的所使用的，而并不暗示任何具体的固定方向。事实上，它们被用于反映对象的各个部分之间的相对位置和/或方向。
典型地，如上所述，晶体管的栅极结构将包括定位于毗邻该栅极结构的至少一个侧壁间隔物。侧壁间隔物典型地由氮化硅(具有相对较高的例如约7-8的k值)构成，并且对于使用替换栅极技术制造的器件它们通常在形成牺牲栅极结构之后很快就形成。对于替换栅极结构，氮化硅间隔物的两个主要用途是限定替换栅极制造工艺中的栅极腔以及保护最终的替换栅极结构。
图1解说常规3D三栅极FinFET(鳍式场效应晶体管)器件100的一部分。此特定的FinFET器件100包括底层衬底(未示出)上的栅极102和鳍104。如图所示，栅极102被间隔物106围绕且在栅极102之上形成有硬掩模108。如上所述，在传统FinFET器件制造过程中，在制造晶体管栅极时，间隔物材料通常被施加于晶体管栅极102，然后被部分地移除或蚀刻以在晶体管栅极的侧壁上形成侧壁间隔物106。在蚀刻侧壁间隔物106期间，由于FinFET器件100的3D结构，难以移除如图1所示的拐角110a和110b附近的SiN膜。在常规工艺中通常需要过度蚀刻以移除这些拐角附近的SiN膜。相比于蚀刻2D平面器件通常需要的30％蚀刻时间，FinFET器件所需的蚀刻时间会在200％至400％的范围内。当硅鳍104暴露时，过度蚀刻会损伤鳍结构，并由此负面地影响FinFET器件100的性能。
传统上为了3D FinFET器件100在拐角(诸如拐角110a和110b)附近的蚀刻，通常采用等离子体蚀刻。图2解说在一些常规FinFET制造工艺中所含的侧壁蚀刻工艺中可采用低能量等离子体气体以平滑拐角110a和110b。如图所示，可如上所述地将低能量等离子体气体202汲取至硅鳍104以轰击拐角110a和110b。如图所示，在此等离子体蚀刻过程中，由于在朝向硅鳍104表面的方向上也有等离子体气体202的轰击，所以硅鳍104处硅的移除是不可避免的。为了最小化此Si损耗，选择低能量等离子体气体202来进行该过度蚀刻，通常约10至100eV。通过移除拐角110a和110b附近的侧壁材料同时具有几乎无Si损耗的弱水平蚀刻效应，图2中示出的低能量等离子体气体处理具有有效平滑拐角110a和110b的特性。因此，图2中所示的低能量等离子体气体处理可有效地保护鳍结构而不会负面地影响器件性能。然而，图2中所示的低能量等离子体处理会蚀刻间隔物106的垂直方向上的侧壁材料并由此降低间隔物106的厚度。这会导致FinFET器件100的关键尺寸(CD)的损耗。
图3解说在一些FinFET常规工艺中的侧壁蚀刻工艺中可采用高能量等离子体气体302以平滑拐角110a和110b。如图所示，可将高能量等离子体气体302汲取至硅鳍104以轰击拐角110a和110b。相比于图2中所示的低能量等离子体工艺，该高能量等离子体工艺具有弱垂直蚀刻效应，由此可以降低或避免图2中所示的低能量等离子体工艺所引起的CD损耗。然而也是相比于图2中所示的低能量等离子体工艺，图3中所示的高能量等离子体工艺具有强水平蚀刻效应，由此将导致比低能量等离子体工艺更大的Si损耗。如图所示，在该高浓度等离子体工艺中，Si会在拐角区域110a和110b处非期望地被移除。
为了解决低能量和/或高能量等离子体工艺中的上述问题，引入了一种新型的等离子体工艺作为改进。在此新型等离子体工艺下，在侧壁材料上生长氧化层并使用低能量等离子体气体对侧壁的拐角区域进行过度蚀刻。该氧化层可在通过低能量等离子体气体过度蚀刻的过程中有效保护侧壁材料，由此降低低能量等离子体气体引起的上述CD损耗。此改进的低能量等离子体蚀刻技术相比于传统低能量等离子体工艺可保护鳍结构不受CD损耗，并且相比于传统高能量等离子体工艺也以降低的Si损耗避免了损害鳍硅结构。
如本领域技术人员在阅读本申请之后将领会的，本文公开的方法和结构可在形成3D晶体管器件时使用。仅出于解释的目的，将在形成透视图中说明性的3D FET器件的上下文中描述本文所公开的发明。附图中描绘的晶体管器件可以是NMOS或PMOS器件。另外，各种掺杂区域，例如源极/漏极区域、晕环注入(halo implant)区域、阱区域等也未在附图中绘出。附图中所绘的说明性的集成电路产品400形成于衬底(未示出)之上，该衬底可具有各种结构形态，诸如所绘的块状硅结构形态。该衬底可由硅构成，或者可由硅以外的其他材料构成。因此，术语“衬底”或“半导体衬底”应被理解为涵盖所有半导体材料和这类材料的所有形式。
图4A-4D解说根据本公开内容的改进的低能量工艺的实施例。它们将参考图1描述。图4A大致解说可在改进的低能量等离子体工艺中在栅极结构之上沉积氮化硅层从而形成该栅极结构的间隔物。如图所示，器件400可包括硅鳍104，在硅鳍104之上形成有晶体管栅极结构102。如图所示，晶体管栅极结构102可包括硬掩模盖108。还是如图所示，可在栅极102和硅鳍104的表面之上形成氮化硅(SiN)层402，使其覆盖硅鳍104和晶体管栅极结构102两者以形成间隔物106。在一些示例中，SiN层402的厚度可以在50埃至300埃的范围内。
图4B解说可在SiN层402的整个表面之上生长氧化层404以使其覆盖SiN层402。在一些示例中，氧化物层404可包括SiOx并且可使用任何合适的工艺来生长，诸如原子层沉积(ALD)或者化学气相沉积(CVD)工艺。在一些示例中，氧化层404的厚度可以控制在10埃至100埃的范围内。
图4C解说可执行选择性干法蚀刻工艺以移除硅鳍104的表面上的氧化层404以及栅极结构102的尖端上(硬掩模108正上方)的氧化层404。如图所示，在图4C所示的选择性干法蚀刻工艺之后，仅留下侧壁402上垂直方向上的氧化层404。选择性干法蚀刻工艺在本领域中很好理解，因此为了清楚起见将不在本公开内容中详细描述。图4D解说可释放低能量等离子体气体406以蚀刻侧壁402上水平方向上的SiN材料。在一些示例中，可将等离子体气体406的能量水平控制在10～100eV的范围内。可如上所述地执行过度蚀刻以平滑拐角110a和110b。可以看见，在图4C中所示的干法蚀刻步骤之后留在侧壁402上垂直方向上的氧化层404可有效地保护侧壁402不受上述低能量等离子体气体406的水平轰击，由此避免上述与传统低能量等离子体气体工艺相关联的CD损耗。图4E解说可使用湿法蚀刻工艺或SiCoNi工艺移除侧壁402上剩余的氧化层404以获得间隔物106。
如本领域技术人员在完整阅读本申请后容易理解的，本文公开的改进工艺适用于各种器件，包括但不限于逻辑器件、存储器件等，且本文公开的方法可被用于形成N型或P型半导体器件。本文公开的方法和器件可被用来使用各种技术制造产品，例如NMOS、PMOS、CMOS等，且它们可被用来制造各种不同器件，例如存储器件、逻辑器件、ASIC等。附图中所绘的各种材料层可通过各种不同已知技术中的任何技术来形成，例如化学气相沉积(CVD)工艺、原子层沉积(ALD)工艺、热生长工艺、旋涂技术等等。而且，如在这里和所附权利要求中使用的，措词“毗邻”被给予广义解释，应被解释为涵盖一个特征实际接触另一个特征或者与该其他特征相邻近的各种情形。
如贯穿本申请的各个部分所解释的，本发明的实施例相比于现有技术和方法可提供许多优点。应领会，本发明的各实施例与现有系统和工艺相兼容。例如，根据本发明的实施例所描述的成型腔可使用现有装备来制造。根据本发明的实施例的成型腔可易于用来制造诸如CMOS、PMOS、NMOS等各种类型的器件。
尽管上文是对特定实施例的全面描述，但是也可使用各种变型、替换构造和等效方案。除了上述内容之外，还存在其他的实施例。因此，上述描述和说明不应当被解释为限制由所附权利要求限定的本发明的范围。

Claims (10)

1.一种用于制造3D鳍场效应晶体管FinFET器件的方法，所述方法包括：
在衬底之上提供鳍形硅；
提供包覆在所述鳍形硅的三个侧面周围的栅极结构；
在所述栅极结构和所述鳍形硅的整个表面之上沉积氮化硅SiN层；
在所述SiN层的整个表面之上沉积氧化层；
执行氧化物蚀刻工艺以移除所述SiN层的表面上在所述鳍形硅上方的氧化层部分；
执行SiN蚀刻工艺以移除所述鳍形硅上方的SiN层部分；以及
执行氧化物移除工艺以移除所述SiN层上垂直方向上的氧化物层部分，以使垂直方向上的所述SiN层至少形成所述栅极结构的侧壁间隔物。
2.如权利要求1所述的方法，其特征在于，所述氧化层的厚度介于10埃至100埃之间。
3.如权利要求1所述的方法，其特征在于，所述氧化层包括氧化硅。
4.如权利要求1所述的方法，其特征在于，所述氧化层是使用原子层沉积ALD工艺或化学气相沉积CVD工艺来沉积的。
5.如权利要求1所述的方法，其特征在于，所述氧化物蚀刻工艺包括选择性地移除所述SiN层的表面上在所述鳍形硅上方的所述氧化层的选择性干法蚀刻步骤。
6.如权利要求5所述的方法，其特征在于，所述选择性干法蚀刻步骤移除形成在所述栅极结构之上的硬掩模盖的表面上的所述氧化层。
7.如权利要求1所述的方法，其特征在于，所述SiN蚀刻工艺是等离子体工艺。
8.如权利要求7所述的方法，其特征在于，所述等离子体工艺中采用的低能量等离子体气体的能量介于10eV至100eV之间。
9.如权利要求7所述的方法，其特征在于，还包括执行过度蚀刻工艺以至少平滑在所述SiN层和所述鳍形硅周围形成的拐角。
10.如权利要求1所述的方法，其特征在于，所述氧化物移除工艺是湿法蚀刻工艺或采用SiCoNi的工艺。
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Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020063299A1 (en) * 2000-11-28 2002-05-30 Kabushiki Kaisha Toshiba Semiconductor device and manufacturing method
US20040132258A1 (en) * 2003-01-07 2004-07-08 You-Seung Jin MOSFET and method of fabricating the same
US7202187B2 (en) * 2004-06-29 2007-04-10 International Business Machines Corporation Method of forming sidewall spacer using dual-frequency plasma enhanced CVD
CN102487003A (zh) * 2010-12-01 2012-06-06 中芯国际集成电路制造(上海)有限公司 辅助侧墙的形成方法
CN103531473A (zh) * 2012-07-02 2014-01-22 中国科学院微电子研究所 氧化硅及氮化硅双层复合侧墙的刻蚀方法
US20140264604A1 (en) * 2013-03-13 2014-09-18 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET Having Source-Drain Sidewall Spacers with Reduced Heights
US20160079388A1 (en) * 2014-09-17 2016-03-17 Commissariat A L'energie Atomique Et Aux Energies Alternatives Production of spacers at flanks of a transistor gate

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020063299A1 (en) * 2000-11-28 2002-05-30 Kabushiki Kaisha Toshiba Semiconductor device and manufacturing method
US20040132258A1 (en) * 2003-01-07 2004-07-08 You-Seung Jin MOSFET and method of fabricating the same
US7202187B2 (en) * 2004-06-29 2007-04-10 International Business Machines Corporation Method of forming sidewall spacer using dual-frequency plasma enhanced CVD
CN102487003A (zh) * 2010-12-01 2012-06-06 中芯国际集成电路制造(上海)有限公司 辅助侧墙的形成方法
CN103531473A (zh) * 2012-07-02 2014-01-22 中国科学院微电子研究所 氧化硅及氮化硅双层复合侧墙的刻蚀方法
US20140264604A1 (en) * 2013-03-13 2014-09-18 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET Having Source-Drain Sidewall Spacers with Reduced Heights
US20160079388A1 (en) * 2014-09-17 2016-03-17 Commissariat A L'energie Atomique Et Aux Energies Alternatives Production of spacers at flanks of a transistor gate

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