CN109427892A - 用于提高p型和N型FinFET性能的混合方案 - Google Patents

用于提高p型和N型FinFET性能的混合方案 Download PDF

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CN109427892A
CN109427892A CN201711190759.0A CN201711190759A CN109427892A CN 109427892 A CN109427892 A CN 109427892A CN 201711190759 A CN201711190759 A CN 201711190759A CN 109427892 A CN109427892 A CN 109427892A
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semiconductor
band
layer
semiconductor layer
top surface
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CN109427892B (zh
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江国诚
朱熙甯
蔡庆威
程冠伦
王志豪
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

一种方法包括蚀刻混合衬底以形成延伸至混合衬底中的凹槽。混合衬底包括具有第一表面取向的第一半导体层、位于第一半导体层上方的介电层以及具有与第一表面取向不同的第二表面取向的第二半导体层。在蚀刻之后，第一半导体层的顶面暴露于凹槽。间隔件形成在凹槽的侧壁上。间隔件接触介电层的侧壁和第二半导体层的侧壁。进行外延以从第一半导体层生长外延半导体区域。去除间隔件。本发明实施例涉及用于提高p型和N型FinFET性能的混合方案。

Description

用于提高p型和N型FinFET性能的混合方案
技术领域
本发明实施例涉及用于提高p型和N型FinFET性能的混合方案。
背景技术
随着集成电路日渐按比例缩小并对集成电路的速度要求日益增加，需要晶体管在尺寸越来越小的同时具有更高的器件电流。因此开发了鳍式场效应晶体管(FinFET)。在常规的FinFET形成工艺中，可以通过在硅衬底中形成沟槽，利用介电材料填充沟槽以形成浅沟槽隔离(STI)区域，然后凹进STI区域的顶部部分来形成半导体鳍。因此，STI区域的凹进部分之间的硅衬底部分形成半导体鳍，在半导体鳍上形成FinFET。
发明内容
根据本发明的一些实施例，提供了一种形成半导体器件的方法，包括：蚀刻混合衬底以形成延伸至所述混合衬底内的凹槽，其中，所述混合衬底包括：第一半导体层，具有第一表面取向；介电层，位于所述第一半导体层上方；和第二半导体层，具有与所述第一表面取向不同的第二表面取向，其中，在所述蚀刻之后，所述第一半导体层的顶面暴露于所述凹槽；在所述凹槽的侧壁上形成间隔件，其中，所述间隔件接触所述介电层的侧壁和所述第二半导体层的侧壁；实施外延以从所述第一半导体层生长外延半导体区域；以及去除所述间隔件。
根据本发明的另一些实施例，还提供了一种形成半导体器件的方法，包括：蚀刻混合衬底以形成凹槽，其中，所述凹槽穿透上半导体层和介电层，其中，位于所述介电层下面的下半导体层的顶面暴露于所述凹槽；在所述凹槽的侧壁上形成竖直间隔件；实施外延以从所述下半导体层生长外延半导体区域；蚀刻所述竖直间隔件，从而通过间隙将所述外延半导体区域与所述上半导体层和所述介电层间隔开；以及进行图案化步骤以形成第一带和第二带，其中，所述第一带包括所述上半导体层的一部分、所述介电层的一部分以及所述下半导体层的一部分，并且所述第二带包括所述外延半导体区域的一部分。
根据本发明的又一些实施例，还提供了一种半导体器件，包括：块状半导体层，具有第一顶面取向；第一半导体带和第二半导体带，位于所述块状半导体层上方并连接至所述块状半导体层，其中，所述第一半导体带和所述第二半导体带具有不同的顶面取向；隔离区域，介于所述第一半导体带与所述第二半导体带之间，所述隔离区域包括从所述隔离区域的底面向下突出的突出部分，其中，所述底面在所述隔离区域的突出部分的相对两侧上；第一源极/漏极区域，覆盖所述第一半导体带，其中，所述第一源极/漏极区域是n型鳍式场效应晶体管(FinFET)的一部分；以及第二源极/漏极区域，覆盖所述第二半导体带，其中，所述第二源极/漏极区域是p型FinFET的一部分。
附图说明
当结合附图进行阅读时，根据下面详细的描述可以最佳地理解本发明的各个方面。应该注意，根据工业中的标准实践，各种部件没有被按比例绘制。实际上，为了清楚的讨论，各种部件的尺寸可以被任意增加或减少。
图1至图16示出根据一些实施例的形成鳍式场效应晶体管(FinFET)的中间阶段的截面图和透视图。
图17A示出根据一些实施例的作为鳍宽度的函数的电子迁移率。
图17B示出根据一些实施例的作为鳍宽度的函数的空穴迁移率。
图18示出根据一些实施例的形成FinFET的工艺流程。
具体实施方式
以下公开内容提供了多种不同实施例或实例，以实现本发明的不同特征。以下将描述组件和布置的具体实例以简化本发明。当然，这些仅是实例并且不意欲限制本发明。例如，在以下描述中，在第二部件上方或上形成第一部件可以包括第一部件和第二部件直接接触的实施例，也可以包括形成在第一部件和第二部件之间的附加部件使得第一部件和第二部件不直接接触的实施例。而且，本发明在各个示例中可以重复参考数字和/或字母。这种重复仅是为了简明和清楚，其自身并不表示所论述的各个实施例和/或配置之间的关系。
而且，为便于描述，在此可以使用诸如“在...下面”、“在...下方”、“下部”、“在...上面”、“上部”等的空间相对术语，以便于描述如图所示的一个元件或部件与另一个(或另一些)元件或部件的关系。除了图中所示的方位外，空间关系术语旨在包括器件在使用或操作过程中的不同方位。装置可以以其他方式定位(旋转90度或在其他方位)，并且在本文中使用的空间关系描述符可以同样地作相应地解释。
根据各种示例性实施例，提供了一种在混合衬底上形成鳍式场效应晶体管(FinFET)的方法以及得到的结构。根据一些实施例说明了形成混合衬底和FinFET的中间阶段。讨论了一些实施例的一些变化。贯穿各个视图和示例性实施例，相同的参考标号用于指定相同的元件。
图1至图16示出根据本发明的一些实施例的形成混合衬底和FinFET的中间阶段的截面图和透视图。图1至图16中示出的步骤也示意性地反映在图18中示出的工艺流程图300中。
参考图1，提供混合衬底20。混合衬底20包括晶体硅层22、硅层22上方的介电层24和介电层24上方的晶体硅层26。介电层24可以由氧化硅或其他介电材料形成，诸如氮化硅、碳化硅等。介电层24的厚度可以在介于约5nm与约15nm之间的范围内，并且可采用不同的厚度。本领域普通技术人员将认识到，整个说明书中列举的尺寸仅仅是示例，并且可以改变为不同的值。硅层26接合至介电层24。混合衬底20包括n型器件区域100中的第一部分和p型器件区域200中的第二部分。
硅层22是具有(100)表面取向的(100)衬底，其中硅层22的顶面在硅的(100)平面中。根据一些实施例，硅衬底26是具有(110)表面取向的(110)衬底，其中硅层的顶面在硅的(110)平面中。根据本发明的替代实施例，硅衬底26是(100)R45层，其通过在切割和接合至介电层24之前将(100)衬底旋转45°来形成。结果，(100)R45层的顶面具有(100)R45表面取向，并且得到的鳍的侧壁(参考图7B所讨论的)也在硅的(100)平面上。
参考图2，实施外延以在硅层26上生长硅层28。相应的步骤在图18所示的工艺流程中表示为步骤302。取决于硅层26的取向，硅层28可以是顶面在硅的(110)平面上的(110)层，或者可以是(100)R45层。硅层28可以不含锗。此外，硅层28可以是本征的，其中在外延中没有掺杂p型和n型杂质。根据替代实施例，在外延期间，硅层28原位掺杂有p型杂质。硅层28的厚度可以接近得到的FinFET的鳍高度。
图3示出在p型器件区域200中的硅层28和混合衬底20的凹进，并且在n型器件区域100中不进行凹进。相应的步骤在图18所示的工艺流程中表示为步骤304。因此形成凹槽35。根据本发明的一些实施例，为了进行凹进，例如，首先通过热氧化或沉积将盖层30形成为毯式平面层。盖层30可以由氧化硅或其他介电材料(诸如氮化硅、碳化硅或氮氧化硅)形成。然后进行凹进。在凹进期间，蚀刻穿过盖层30、硅层28和硅层26，从而暴露下面的介电层24的顶面，然后蚀刻该顶面。因此暴露具有(100)表面平面的硅层22。
接下来，沉积间隔件层，随后进行各向异性蚀刻以去除间隔件层的水平部分，从而形成间隔件32。相应的步骤在图18所示的工艺流程中表示为步骤306。间隔件层由与盖层30的材料不同的材料形成。根据本发明的一些实施例，间隔件32由介电材料形成，诸如氧化铝(Al2O3)、氮化硅等。由于用于形成盖层30和间隔件32的不同材料，在形成间隔件32之后保留盖层30。因此，硅层26和28的侧壁和顶面都被掩蔽。
图4示出半导体层34的选择性外延。相应的步骤在图18所示的工艺流程中表示为步骤308。根据本发明的一些实施例，半导体层34由高迁移率半导体材料形成，诸如硅锗、锗(不含硅)、III-V族化合物半导体(诸如GaAs、InP、GaN、InGaAs、InAlAs、GaSb、AlSb、AlAs、AlP、GaP)、它们的组合或它们的多层。在选择性外延中，在工艺气体中添加诸如HCl的蚀刻气体，使得半导体层34从硅层22的顶面生长，而不是从诸如盖层30和间隔件32的介电材料生长。间隔件32掩蔽硅层26和28的侧壁，从而从单一表面(硅层22的顶面)实现外延，并且因此避免由从不同表面生长导致的缺陷。由于半导体层34从硅层22外延生长，所以具有与硅层22相同的表面取向，并且具有(100)表面取向。
在半导体层34的选择性外延之后，进行诸如化学机械抛光(CMP)或机械研磨的平坦化步骤以使半导体层34的顶面齐平。根据本发明的一些实施例，使用硅层28作为停止层来进行平坦化。根据本发明的替代实施例，使用盖层30作为停止层来进行平坦化，接着进行蚀刻工艺以去除盖层30。
在平坦化之后，去除如图4所示的间隔件32，并且在图5A和图5B中示出所得到的结构。相应的步骤在图18所示的工艺流程中表示为步骤310。图5A示出该结构的透视图，并且图5B示出该结构的截面图。如图5A和图5B两者所示，由于去除间隔件层32而产生凹槽(间隙)36，并且凹槽36将半导体层26和28与半导体层34分离。根据本发明的一些实施例，通过湿蚀刻工艺去除间隔件32。例如，当间隔件32由氮化硅形成时，可以使用磷酸来进行蚀刻。
参考图6，形成保护层38。根据本发明的一些实施例，保护层38由硅形成，并且沉积在图5A所示的结构的顶面上。保护层38也不含锗。沉积可以通过外延工艺来实现，使得硅层是晶体层。根据本发明的替代实施例，硅层38是多晶硅层。保护层38可以形成横跨在凹槽36上方的桥(bridge)，同时保护层38的一些沉积材料可能落入凹槽36中。
如图6和图7A和图7B所示的以下步骤示出半导体带的形成。可以通过任何合适的方法图案化该带。例如，可以使用一个或多个光刻工艺来图案化该带，包括双重图案化或多重图案化工艺。通常，双重图案化或多重图案化工艺将光刻和自对准工艺组合在一起，从而允许创建图案以具有例如比使用单个直接光刻工艺可获得的图案更小的间距。例如，在一个实施例中，在衬底上方形成牺牲层并且使用光刻工艺进行图案化。使用自对准工艺在图案化的牺牲层旁形成间隔件。然后去除牺牲层，并且然后可以使用剩余的间隔件或芯轴来图案化该带。
根据如图6所示的一些示例性实施例，在保护层38上方沉积掩模层，然后图案化掩模层以形成掩模40，该掩模用作用于形成半导体带的蚀刻掩模。根据本发明的一些实施例，掩模40包括由不同材料形成的多个层。例如，掩模40可以包括由氧化硅形成的层40A以及位于相应层40上方的层40B，其中层40B由氮化硅形成。在掩模40的形成中，例如，保护层38保护下面的半导体层34免于由于在掩模层的沉积中所采用的升高的温度而被氧化。硅锗易于氧化，并且氧化率也显著高于硅的氧化率。因此，通过形成保护层38，保护半导体层34免于不期望的氧化。
参考图7A和图7B，进行蚀刻工艺以蚀刻衬底和半导体层，使得带142和242分别形成在n型器件区域100和p型器件区域200中。相应的步骤在图18所示的工艺流程中表示为步骤312。形成凹槽44以分离带142和242。带142包括部分122、124和127。带部分122是图案化的硅层22的剩余部分。带部分124是介电层24(图6)的剩余部分。带部分127是硅层26和28(图6)的剩余部分。根据本发明的一些实施例，硅层26和28(图6)具有(110)顶面取向。因此，带部分127也具有(110)顶面取向。根据本发明的一些实施例，硅层26和28是(100)R45层。因此，带142的顶面和侧壁两者都具有(100)表面取向。带242包括部分222和234。带部分222是图案化的硅层22的剩余部分。带部分234是半导体层34(图6)的剩余部分。因此，带部分234也具有(100)顶面取向。
图7A示出带形成之后的结构的透视图。图7B示出图7A中所示的结构的截面图。在图7B中，带部分127的所示顶面可以在(100)表面平面或(110)表面平面上，并且带部分127的左侧壁和右侧壁在(100)表面平面上。带部分234的所示顶面可以在(100)表面平面上，并且带部分234的左侧壁表面和右侧壁表面可以在(110)平面上。
还如图7A和图7B所示，在用于形成带142和242的图案化中，也蚀刻硅层22的直接位于凹槽36(图6)下方的部分，因此，切口46形成为延伸至硅层22中。由于通过深且窄的凹槽36蚀刻硅层22较慢，所以切口具有的深度D1小于半导体层34(图6)的厚度。根据一些实施例，深度D1(图7B)在介于约5nm和约40nm之间的范围内。切口46的顶部宽度W1可以在介于约3nm和约10nm之间的范围内。带142和242的宽度W2可以在介于约4nm和约6nm之间的范围内。如果在图7A和图7B的俯视图中观察，则切口46和带142和242全部是细长带，其纵向方向彼此平行。
根据一些实施例，切口46可以具有大于约0.5的纵横比，并且纵横比可以在介于约0.5和约5.0之间的范围内。例如，凹槽36的深度和宽度影响纵横比。应当理解，尽管图7A和图7B示出切口46具有直的侧壁和平面底部，但是切口46的侧壁和底部可以是圆形的。例如，切口46的侧壁可以连续弯曲，并且连接至弯曲的底部。切口46的侧壁也可以基本是直的，并且该侧壁连接至弯曲的底部。切口46也可以是有刻面的，并且可以具有U形截面视图，具有直边缘和平坦底面。切口46也可以是有刻面的，具有V形截面视图。也涉及其他形状。
如图4至图7A和图7B所示，如果在形成保护层和掩模之前未去除间隔件32(图4)，则在图7A和图7B所示的图案化步骤中，间隔件32将被留下，并且还将保护下面的硅层22的部分，使得将形成包括间隔件32和下面的硅层22的部分的窄且高的带。在随后的工艺中，诸如在浅沟槽隔离(STI)区域50(图9)的形成中，该带可能会塌陷，并且因此导致缺陷。根据本发明的一些实施例，间隔件的去除避免缺陷的产生。结果，在n型器件区域100与p型器件区域200之间的界面区域处形成切口46。根据本发明的一些实施例，例如，切口46位于带142和242的中间，其中距离S1和S2具有小于距离S1和S2中的任一个的约20％或约10％的差异。当切口46位于带142和242的中间时，S1和S2两者都可以保持最小，同时在p型和n型FinFET之间留下足够的间隔，并且因此得到的FinFET的密度可以最大化。
图8示出了第一衬垫48的形成，第一衬垫48用于掩蔽带部分234的侧壁以免于氧化。根据本发明的一些实施例，衬垫48由硅形成，并且不含或基本不含锗(例如，如果有的话，锗原子百分比低于约5％)。此外，衬垫48可以不含氧和氮，并且因此不包括氧化硅和氮化硅。可以使用诸如原子层沉积(ALD)或化学气相沉积(CVD)的共形沉积方法来进行衬垫48的形成。因此衬垫48延伸至凹槽44和切口46中。此外，衬垫48部分地填充切口46，并且留下切口46的一部分不被填充。
图9示出包括介电衬垫52和位于介电衬垫52上方的介电区域54的STI区域50的形成。相应的步骤在图18所示的工艺流程中表示为步骤314。根据本发明的一些实施例，使用共形沉积方法在图8所示的结构的暴露表面上沉积共形介电衬垫52。例如，可以使用ALD或CVD来形成介电衬垫52。接下来，利用介电材料54填充凹槽44(图8)的剩余部分。可以使用可流动化学气相沉积(FCVD)、旋涂等形成介电材料54。根据其中使用FCVD的一些实施例，使用含硅和氮的前体(例如，三甲硅烷基胺(TSA)或二甲硅烷基胺(DSA))，并且因此得到的介电材料是可流动的(果冻状)。根据本发明的替代实施例，使用基于烷基氨基硅烷的前体形成可流动介电材料。在沉积期间，开启等离子体以激活用于形成可流动氧化物的气态前体。
在介电衬垫52和介电区域54的形成中，可以升高形成工艺的温度，如果带部分234暴露，则这可能导致带部分234的氧化。因此，衬垫48(图8)保护带部分234不被氧化。结果，在介电衬垫52和介电区域54的形成期间，衬垫48(或至少衬垫48的与带部分124、127和234接触的部分)可能被氧化，并且因此转化为氧化硅层。
接下来，在介电区域54和介电衬垫52上进行诸如CMP或机械研磨的平坦化。可以使用掩模40(图8)作为停止层来进行平坦化。接下来，去除掩模40，之后凹进介电区域54和介电衬垫52。相应的步骤在图18所示的工艺流程图中示出为步骤314。图9中示出得到的结构。介电区域54和介电衬垫52的剩余部分称为STI区域50。根据本发明的一些实施例，进行凹进，直到凹进的STI区域50的顶面低于介电带部分124的顶面，从而暴露介电带部分124的侧壁的至少一些部分。根据本发明的替代实施例，凹进的STI区域50的顶面齐平于、高于或低于介电带部分124的底面。在整个说明书中，带142和242的比STI区域50的顶面高的部分称为鳍(或突出的鳍)156和256。切口46(图8)填充有向下突出的部分50'，其为STI区域50中的一个的一部分。
参考图10，伪栅极堆叠件58形成在(突出的)鳍156和256的顶面和侧壁上。相应的步骤在图18所示的工艺流程中表示为步骤316。尽管为了简洁而示出一个伪栅极堆叠件58，但是可以形成彼此平行的多个伪栅极堆叠件，其中多个伪栅极堆叠件横跨相同的半导体鳍156和256。伪栅极堆叠件58可以包括伪栅极电介质60和位于伪栅极电介质60上方的伪栅电极62。例如，可以使用多晶硅形成伪栅电极62，并且也可以使用其他材料。伪栅极堆叠件58也可以包括位于伪栅电极62上方的一个(或多个)硬掩模层64。硬掩模层64可以由氮化硅、碳氮化硅等形成。伪栅极堆叠件58可以跨在单个或多个突出的鳍156和256和/或STI区域50上方。伪栅极堆叠件58的纵向方向垂直于突出的鳍156和256的纵向方向。
接下来，参考图11，沉积间隔件层66。根据本发明的一些实施例，间隔件层66由诸如氮化硅、碳氮氧化硅(SiCON)等的介电材料形成，并且可以具有单层结构或包括多个介电层的多层结构。可以通过诸如ALD或CVD的共形沉积方法来进行该形成。
图12示出间隔件层66的蚀刻，使得在伪栅极堆叠件58的侧壁上形成栅极间隔件68。相应的步骤在图18所示的工艺流程中表示为步骤318。各向异性地实施蚀刻，从而去除间隔件层的位于突出的鳍156和256上的部分。在用于形成栅极间隔件68的蚀刻之后，暴露介电带部分124(图11)的一些侧壁。根据本发明的一些实施例，进行各向同性蚀刻以蚀刻介电带部分124，而突出的鳍156和256的半导体部分以及间隔件68未被蚀刻。相应的步骤在图18所示的工艺流程中表示为步骤320。根据本发明的一些实施例，通过湿蚀刻来进行介电带部分124的蚀刻。例如，当介电带部分124由氧化硅形成时，可以使用HF溶液作为蚀刻剂。在蚀刻介电带部分124之后，形成间隙70，以将带部分127与下面的带部分122分离。根据本发明的替代实施例，在形成栅极间隔件68之后，留下介电带部分124的至少一些部分以将鳍部分127与带部分122分离。
在蚀刻介电带部分124之后，介电带部分124的一些部分仍然保留在伪栅极堆叠件58的正下方。介电带部分124的这些部分未被去除，并且用于支撑上面的带部分127(在下文中称为半导体鳍127)。因此，鳍部分127中的未位于伪栅极堆叠件58正下方的部分悬置在间隙70上方。带部分122的顶面也暴露于间隙70。
接下来，分别通过在突出的鳍156和256上选择性地生长半导体材料来形成外延区域172和272，从而得到图13A和图13B中的结构。相应的步骤在图18所示的工艺流程中表示为步骤322。在不同的外延工艺中外延生长外延区域172和272，其中每个都包括在外延区域172和272中的一个上形成掩模层(未示出)，使得外延区域可以形成在外延区域172和272中的另一个上。取决于得到的FinFET是p型FinFET还是n型FinFET，随着外延的进行，可以原位掺杂p型或n型杂质。例如，外延区域172可以由硅磷(SiP)或硅碳磷(SiCP)形成，并且外延区域272可以由硅锗硼(SiGeB)形成。
在外延步骤之后，外延区域172和带部分127可以进一步注入有n型杂质，以形成n型FinFET的源极和漏极区域174。外延区域272和带部分234也可以注入有p型杂质，以形成p型FinFET的源极和漏极区域274。根据本发明的替代实施例，当在外延期间，外延区域172和272原位掺杂有p型或n型杂质时，跳过注入步骤。
由于如图12所示的间隙70，所以在外延期间，半导体材料从带部分122的顶面和带部分127的表面两者同时生长。半导体材料的从带部分122的顶面生长的部分标注为外延区域172A。半导体材料的从带部分127生长的部分标注为外延区域172B，其在截面图中围绕对应的带部分127。
外延区域172A和172B具有相同的组成，这意味着它们由相同的半导体材料形成，诸如硅、SiP或SiCP等，并且外延区域172A和172B中的对应元素的原子和重量百分比彼此相同。外延区域172A和172B也可以由晶格常数比带部分127的晶格常数小的其他半导体材料形成，使得可以由外延区域172A和172B施加拉伸应力。例如，可以使用晶格常数比带部分127的晶格常数小的III-V族化合物半导体材料。另一方面，带部分122和127具有不同的表面结构。例如，带部分122可以具有(100)顶面取向，而带部分127可以具有(110)或(100)R45顶面取向。因此，外延区域172A和172B具有不同的表面结构，并且外延区域172A具有与带部分122相同的表面结构，并且外延区域172B具有与带部分127相同的表面结构。外延区域172A最终与对应的上面的外延区域172B合并以形成外延区域172。外延区域172A与对应的外延区域172B之间的界面可能高于STI区域50的顶面。图13B示出图13A所示的外延区域172A和172B的截面图。
在如图13A和图13B所示的示例性实施例中，外延区域172A和172B具有圆形的外部侧壁。应当认识到，外延区域172A和172B的形状受诸如材料、带部分127的形状、带部分122的顶面形状等的各种因素的影响。因此，外延区域172A和172B中的任一个的侧壁可以是圆形的(连续弯曲的)或有刻面的(具有如图13B所示的平面中的笔直部分)。而且，外延区域172A与172B之间的界面可以具有不同的形状，包括但不限于笔直界面、弯曲界面(如图13B所示)，或者包括若干笔直部分。例如，外延区域172B的外周边可以具有细长的六边形形状，其中与相应晶圆的顶面垂直的竖直边缘长于其他侧边。
当外延区域172A和172B的直接位于带部分122的中心上方的部分的生长速率低于其对应的左侧部分和右侧部分的生长速率时，也可以形成空隙(其可以是真空间隙或气隙)173(如图13B所示)。取决于生长速率的差异，空隙173可以具有不同的形状。
外延区域172A与外延区域172B的合并是有利的。由于同一晶圆/管芯上不同类型的器件会尽可能多地共用形成工艺以降低制造成本，所以形成FinFET的工艺也可以用于形成二极管和无源器件，诸如衬底区域的拾取区域。这些器件需要同时形成将被连接至衬底22的作为源极/漏极区域174和274的它们的区域。根据本发明的一些实施例，通过去除带部分124，使得外延区域172A和172B可以合并，二极管和无源器件可以连接至衬底22。因此，共用用于形成所示FinFET与形成其他器件(诸如二极管和无源器件)的工艺步骤是可行的。根据替代实施例，介电带部分124未被蚀刻，根据这些实施例，FinFET将具有减小的源极/漏极泄漏。
尽管图13A和图13B示出源极/漏极区域174彼此分离，并且源极/漏极区域274彼此分离，但是应当认识到，取决于外延工艺持续多长时间，源极/漏极区域174可以彼此合并或保持彼此分离，并且源极/漏极区域274可以彼此合并或保持彼此分离。而且，外延区域172和272的形状可以与所示出的类似，或者具有其他形状，诸如铁锹形/菱形形状。气隙可以直接形成在外延区域172的合并部分下面，和/或直接形成在外延区域272的合并部分下面。
图14示出形成为具有接触蚀刻停止层(CESL)76和层间电介质(ILD)78的结构的透视图。相应的步骤在图18所示的工艺流程中表示为步骤324。CESL 76可以由氮化硅、碳氮化硅等形成。例如，可以使用诸如ALD的共形沉积方法来形成CESL 76。例如，ILD 78可以包括使用FCVD、旋涂、CVD或其他沉积方法形成的介电材料。ILD 78也可以由正硅酸乙酯(TEOS)氧化物、等离子体增强CVD(PECVD)氧化物(SiO2)、磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BSG)、硼掺杂的磷硅酸盐玻璃(BPSG)等形成。可以进行诸如CMP或机械研磨的平坦化步骤以使ILD78、伪栅极堆叠件58和栅极间隔件68的顶面彼此平齐。
接下来，如图15A、图15B、图15C、图15D、图15E和图15F所示，包括硬掩模层64、伪栅电极62和伪栅极电介质60的伪栅极堆叠件58被替换栅极堆叠件84替换，该替换栅极堆叠件84包括金属栅极82和替换栅极电介质80。在伪栅极堆叠件58的去除中，暴露先前掩埋在伪栅极堆叠件下方的介电带部分124(图9)，并且由于其材料与伪栅极电介质的材料的相似性而至少被横向凹进。根据本发明的一些实施例，如果带部分124的材料与STI区域50的材料不同，则在去除伪栅极堆叠件之后，还进行可以为湿刻蚀工艺的附加蚀刻工艺，使得去除带部分124，而不损坏STI区域50。
当替换栅极堆叠件时，首先在一个或多个蚀刻步骤中去除硬掩模层64、伪栅电极62和伪栅极电介质60(图14)，得到形成在栅极间隔件68之间的沟槽(开口)。在替换栅极的形成中，首先形成栅极介电层80(图15A)，其延伸至由去除的伪栅极堆叠件留下的凹槽中，并且可以具有在ILD 78上方延伸的部分。根据本发明的一些实施例，栅极电介质80包括作为其下部的界面层(IL，未单独示出)48。IL可以包括通过化学氧化工艺或沉积工艺形成的诸如氧化硅层的氧化物层。栅极电介质80还可以包括形成在IL上方的高k介电层。高k介电层形成为共形层，并且包括高k介电材料，诸如氧化铪、氧化镧、氧化铝、氧化锆等。高k介电材料的介电常数(k值)高于3.9，并且可以高于约7.0。根据本发明的一些实施例，使用ALD或CVD来形成栅极电介质80中的高k介电层。
栅电极82形成在栅极电介质80上方并且填充凹槽的剩余部分。栅电极82的形成可以包括多个沉积工艺以沉积多个导电层，并且进行平坦化步骤以去除ILD 78上方的导电层的多余部分。可以使用诸如ALD或CVD的共形沉积方法来进行导电层的沉积。
栅电极82可以包括扩散阻挡层和位于扩散阻挡层上方的一个(或多个)功函数层。扩散阻挡层可以由氮化钛(TiN)形成，氮化钛(TiN)可以(或可以不)掺杂有硅以形成TiSiN。功函数层确定栅极的功函数，并且包括至少一个层或由不同材料形成的多个层。根据相应的FinFET是n型FinFET还是p型FinFET来选择功函数层的具体材料。例如，对于器件区域100中的n型FinFET，功函数层可以包括TaN层和位于TaN层上方的钛铝(TiAl)层。对于器件区域200中的p型FinFET，功函数层可以包括TaN层、位于TaN层上方的TiN层以及位于TiN层上方的TiAl层。在功函数层的沉积之后，形成可以为另一TiN层的另一阻挡层。栅电极82还可以包括填充金属，例如可以由钨或钴形成。在形成替换栅极84之后，对替换栅极84进行凹进，并且介电硬掩模86填充至凹槽中。
图15B、图15C、图15D和图15E示出器件区域100中的n型FinFET的替换栅极的多个截面图，其中，从图15A中包含线B-B的竖直平面获得截面图。由于介电带部分124的横向凹进，得到的栅极可以形成Ω栅极或四栅极(quad-gate)。例如，图15B示出Ω栅极，其中，介电带部分124的顶部部分被横向凹进，并且介电带部分124的凹进部分的侧壁基本竖直。图15C示出另一Ω栅极，其中，介电带部分124的顶部部分被横向凹进，并且介电带部分124的凹进部分的侧壁是倾斜的，并且可以基本是直的。图15D示出Ω栅极，其中，介电带部分124整体被横向凹进，并且介电带部分124的侧壁基本竖直。图15E示出四栅极，其中，介电带部分124(参考图15D作为对照)被完全去除。得到的栅极堆叠件84包括接触鳍部分127的顶面、底面、左侧壁和右侧壁的四个部分(因此命名为四栅极)。通过形成Ω栅极或四栅极，FinFET的短沟道控制得到改善。在图15B、图15C、图15D和图15E中，鳍部分127形成FinFET的沟道区域。
根据本发明的一些实施例，介电带部分124的高度在介于约5nm和约15nm之间的范围内。介电带部分124的颈缩部分的高度b(图15B和图15C)在介于约3nm和约15nm之间的范围内。介电带部分124的颈缩部分的横向凹进距离c(图15B、图15C和图15D)在介于约1nm和约3nm之间的范围内。
图15F示出器件区域200中的p型FinFET的替换栅极的截面图。鳍部分234形成FinFET的沟道区域。
在形成图15A所示的结构之后，蚀刻ILD 78和CESL 76以形成接触开口。例如，可以使用反应离子蚀刻(RIE)来进行蚀刻。在随后的步骤中，如图16所示，形成源极/漏极接触塞88。相应的步骤在图18所示的工艺流程图中示出为步骤324。在形成接触塞88之前，首先蚀刻CESL 76的暴露于接触开口的部分，以露出外延区域172和272。然后，硅化物区域90形成在外延区域172和272上。根据本发明的一些实施例，接触塞88包括阻挡层和位于相应阻挡层上方的含金属材料。根据本发明的一些实施例，接触塞88的形成包括形成毯式阻挡层和毯式阻挡层上方的含金属材料以及进行平坦化以去除毯式阻挡层和含金属材料的多余部分。阻挡层可以由诸如氮化钛或氮化钽的金属氮化物形成。含金属材料可以由钨、钴、铜等形成。由此形成n型FinFET和192和p型FinFET 292。
图17A示出作为n型FinFET的半导体鳍的宽度(例如，参考图7B中的宽度W1和W2)的函数的电子迁移率。线90A示出从(110)晶圆(具有鳍的侧壁在(100)平面上)和(100)R45晶圆两者获得的结果。说明当鳍的宽度小于约3nm时，电子迁移率低，并且当宽度高于约3nm时，电子迁移率高。因此，基于大于约3nm的鳍宽度形成的FinFET可以具有良好的性能。作为比较，如线90B线所示，(110)晶圆(鳍的顶面和侧壁两者都在(110)平面上)，电子迁移率远低于线90A，并且电子迁移率直到鳍宽度增加到约6nm时才增加。结果表明在(100)R45和(110)晶圆上形成的n型FinFET具有良好的性能。
图17B示出作为p型FinFET的半导体鳍的宽度(例如，参考图7B中的宽度W1和W2)的函数的空穴迁移率。线92A示出从鳍的顶面在(100)平面上并且鳍的侧壁在(110)平面上的晶圆得到的结果。线92B示出从鳍的顶面和侧壁表面两者都在(110)平面上的晶圆获得的结果。线92C示出从鳍的顶面和侧壁表面两者都在(100)平面上的晶圆获得的结果。结果表明线92A比线92B和线92C具有更好的结果。因此，图17A和图17B所示的结果组合在一起表明：(100)R45或(110)顶面上的n型FinFET具有良好的性能，并且(100)顶面上的p型FinFET具有良好的性能。因此，根据本发明的实施例，当形成于混合衬底上时，n型FinFET和p型FinFET两者的性能得到改善。
本发明的实施例具有一些有利特征。通过从混合衬底形成n型FinFET和p型FinFET，提高了n型FinFET和p型FinFET两者的性能。将n型器件区域与p型器件区域分离的间隔件的去除有利地消除了由间隔件的塌陷而引起的缺陷。
根据本发明的一些实施例，一种方法包括蚀刻混合衬底以形成延伸至混合衬底中的凹槽。混合衬底包括具有第一表面取向的第一半导体层、位于第一半导体层上方的介电层以及具有与第一表面取向不同的第二表面取向的第二半导体层。在蚀刻之后，第一半导体层的顶面暴露于凹槽。间隔件形成在凹槽的侧壁上。间隔件接触介电层的侧壁和第二半导体层的侧壁。进行外延以从第一半导体层生长外延半导体区域。去除间隔件。在实施例中，在去除间隔件之后，进行第一图案化步骤，其中，通过第一图案化步骤图案化第二半导体层、介电层和第一半导体层以形成第一半导体带。在实施例中，当进行第一图案化步骤时，同时进行第二图案化步骤，其中，图案化外延半导体区域和第一半导体层以形成第二半导体带。在实施例中，在第一图案化步骤期间，第一半导体层的直接位于去除的间隔件下方的部分被凹进以形成从第一半导体层的顶面向下延伸的切口，并且第一半导体层的顶面延伸至切口的相对两侧。在实施例中，该方法还包括：在第一半导体带的相对两侧上形成隔离区域；对隔离区域进行凹进，其中，第一半导体带的顶部部分突出为高于隔离区域的其余部分的顶面以形成鳍；以及基于该鳍形成鳍式场效应晶体管(FinFET)。在实施例中，在湿蚀刻步骤中进行间隔件的去除。在实施例中，在去除间隔件之后，形成间隙以将外延半导体区域与介电层和第二半导体层的剩余部分分离。
根据本发明的一些实施例，一种方法包括：蚀刻混合衬底以形成凹槽，其中，凹槽穿透上半导体层和介电层，其中位于介电层下面的下半导体层的顶面暴露于凹槽；在凹槽的侧壁上形成竖直间隔件；进行外延以从下半导体层生长外延半导体区域；蚀刻竖直间隔件，使得外延半导体区域与上半导体层和介电层以间隙间隔开；以及进行图案化步骤以形成第一带和第二带，其中，第一带包括上半导体层的一部分、介电层的一部分以及下半导体层的一部分，并且第二带包括外延半导体区域的一部分。在实施例中，方法还包括：在蚀刻竖直间隔件之后并且在图案化步骤之前，在上半导体层和外延半导体区域上方沉积硅层。在实施例中，该方法还包括：在第一带和第二带中的每一个的相对侧上都形成隔离区域；以及对隔离区域进行凹进，其中第一带和第二带的顶部部分突出为高于隔离区域的其余部分的顶面，以分别形成第一鳍和第二鳍。在实施例中，该方法还包括：蚀刻第一带中的介电层的一部分，以将第一带中的上半导体层的部分与第一带中的下半导体层的部分分离。在实施例中，该方法还包括：进行外延以生长附加的半导体材料，其中，附加的半导体材料包括：从第一带中的上半导体层的部分生长的第一部分；和从第一带中的下半导体层的部分生长的第二部分，其中，附加的半导体材料的第一部分和第二部分具有不同的顶面取向并且彼此合并。在实施例中，图案化步骤使得在第一带与第二带之间形成间隙，其中下半导体层的顶面直接位于凹槽下方并且暴露于凹槽，并且形成切口以从下半导体层的顶面向下延伸至下半导体层中。在实施例中，切口在蚀刻的垂直间隔件正下方的位置处。
根据本发明的一些实施例，一种器件包括：块状半导体层，具有第一顶面取向；第一半导体带和第二半导体带，位于块状半导体层上方并连接至块状半导体层，其中，第一半导体带和第二半导体带具有不同的顶面取向；隔离区域，介于第一半导体带与第二半导体带之间，隔离区域包括从隔离区域的底面向下突出的突出部分，其中该底面在隔离区域的突出部分的相对两侧上；第一源极/漏极区域，覆盖第一半导体带，其中，第一源极/漏极区域是n型FinFET的一部分；以及第二源极/漏极区域，覆盖第二半导体带，其中，第二源极/漏极区域是p型FinFET的一部分。在实施例中，第二源极/漏极区域具有第一顶面取向，并且第一源极/漏极区域具有与第一顶面取向不同的第二顶面取向。在实施例中，第一源极/漏极区域具有(110)顶面取向，并且第二源极/漏极区域具有(100)顶面取向。在实施例中，第一源极/漏极区域具有(100)R45顶面取向，并且第二源极/漏极区域具有(100)顶面取向。在实施例中，第一源极/漏极区域包括：上部部分和下部部分，其中，上部部分和下部部分具有不同的顶面取向，其中，上部部分和下部部分的接合处高于隔离区域的顶面。在实施例中，隔离区域的突出部分位于介于第一半导体带与第二半导体带之间的中间处。
根据本发明的一些实施例，一种方法包括：形成竖直间隔件以分离第一半导体区域与第二半导体区域；蚀刻竖直间隔件以在第一半导体区域与第二半导体区域之间形成间隙；形成分别覆盖第一半导体区域和第二半导体区域的第一掩模和第二掩模；以及使用第一掩模和第二掩模作为蚀刻掩模来蚀刻第一半导体区域和第二半导体区域，其中，第一半导体区域和第二半导体区域的剩余部分分别形成第一带和第二带的部分，其中第一带与第二带通过凹槽间隔开，并且形成从凹槽向下延伸至下面的半导体层中的切口。在实施例中，该方法还包括：形成第一半导体区域，包括：在混合衬底上进行外延，其中，混合衬底包括第一半导体层、位于第一半导体层上方的介电层以及位于介电层上方的第二半导体层，其中，在外延中，从第一半导体层生长附加的半导体层。在实施例中，该方法还包括：形成第二半导体区域，包括：蚀刻半导体层和位于半导体层下面的介电层以形成凹槽；并且从凹槽外延生长第二半导体区域。在实施例中，该方法还包括分别基于第一带和第二带形成n型FinFET和p型FinFET。
根据本发明的一些实施例，一种器件包括：n型FinFET，包括形成n型FinFET的第一沟道的第一半导体材料和被第一半导体材料覆盖的第一半导体带；p型FinFET，包括形成p型FinFET的第二沟道的第二半导体材料和被第二半导体材料覆盖的第二半导体带，其中，第一半导体材料和第二半导体材料具有不同的顶面取向；以及STI区域，介于第一半导体带与第二半导体带之间并且接触第一半导体带和第二半导体带，其中，STI区域包括位于第一半导体带和第二半导体带的中间处的突出部分，并且突出部分延伸至STI区域的相反底面以下。在实施例中，第一半导体带和第二半导体带具有与第二半导体材料相同的顶面取向。在实施例中，第一半导体带和第二半导体带具有与第一半导体材料不同的顶面取向。
根据本发明的一些实施例，一种器件包括：n型FinFET，包括第一半导体带、覆盖第一半导体带的第一半导体鳍以及位于第一半导体鳍的一部分上面的第一栅极堆叠件；p型FinFET，包括第二半导体带、覆盖第二半导体带的第二半导体鳍以及位于第二半导体鳍的一部分上面的第二栅极堆叠件；以及STI区域，介于第一半导体带与第二半导体带之间，其中，STI区域包括从STI区域的块状部分向下突出的突出部分，并且从上往下看器件时，突出部分具有与第一半导体带和第二半导体带的纵向方向平行的纵向方向。在实施例中，第一半导体带和第二半导体带具有与第二半导体鳍相同的顶面取向，并且第一半导体带和第二半导体带具有与第一半导体鳍不同的顶面取向。在实施例中，突出部分具有介于约5nm和约40nm之间的高度。
根据本发明的一些实施例，提供了一种形成半导体器件的方法，包括：蚀刻混合衬底以形成延伸至所述混合衬底内的凹槽，其中，所述混合衬底包括：第一半导体层，具有第一表面取向；介电层，位于所述第一半导体层上方；和第二半导体层，具有与所述第一表面取向不同的第二表面取向，其中，在所述蚀刻之后，所述第一半导体层的顶面暴露于所述凹槽；在所述凹槽的侧壁上形成间隔件，其中，所述间隔件接触所述介电层的侧壁和所述第二半导体层的侧壁；实施外延以从所述第一半导体层生长外延半导体区域；以及去除所述间隔件。
在上述方法中，还包括：在去除所述间隔件之后，实施第一图案化步骤，其中，通过所述第一图案化步骤图案化所述第二半导体层、所述介电层和所述第一半导体层以形成第一半导体带。
在上述方法中，还包括：当实施所述第一图案化步骤时，同时实施第二图案化步骤，其中，图案化所述外延半导体区域和所述第一半导体层以形成第二半导体带。
在上述方法中，在所述第一图案化步骤期间，所述第一半导体层的直接位于去除的间隔件下方的部分被凹进以形成从所述第一半导体层的顶面向下延伸的切口，并且所述第一半导体层的顶面延伸至所述切口的相对两侧。
在上述方法中，还包括：在所述第一半导体带的相对两侧上形成隔离区域；对所述隔离区域进行凹进，其中，所述第一半导体带的顶部突出为高于所述隔离区域的剩余部分的顶面以形成鳍；以及基于所述鳍形成鳍式场效应晶体管(FinFET)。
在上述方法中，通过湿蚀刻步骤实施所述间隔件的去除。
在上述方法中，在去除所述间隔件之后，形成间隙以将所述外延半导体区域与所述介电层和所述第二半导体层的剩余部分分离。
根据本发明的另一些实施例，还提供了一种形成半导体器件的方法，包括：蚀刻混合衬底以形成凹槽，其中，所述凹槽穿透上半导体层和介电层，其中，位于所述介电层下面的下半导体层的顶面暴露于所述凹槽；在所述凹槽的侧壁上形成竖直间隔件；实施外延以从所述下半导体层生长外延半导体区域；蚀刻所述竖直间隔件，从而通过间隙将所述外延半导体区域与所述上半导体层和所述介电层间隔开；以及进行图案化步骤以形成第一带和第二带，其中，所述第一带包括所述上半导体层的一部分、所述介电层的一部分以及所述下半导体层的一部分，并且所述第二带包括所述外延半导体区域的一部分。
在上述方法中，还包括：在蚀刻所述竖直间隔件之后并且在所述图案化步骤之前，在所述上半导体层和所述外延半导体区域上方沉积硅层。
在上述方法中，还包括：在每个所述第一带和所述第二带的相对两侧上都形成隔离区域；以及对所述隔离区域进行凹进，其中，所述第一带和所述第二带的顶部突出为高于所述隔离区域的剩余部分的顶面，以分别形成第一鳍和第二鳍。
在上述方法中，还包括：蚀刻所述第一带中的所述介电层的所述一部分，以将所述第一带中的所述上半导体层的所述一部分与所述第一带中的所述下半导体层的所述一部分分离。
在上述方法中，还包括进行外延以生长附加的半导体材料，其中，所述附加的半导体材料包括：从所述第一带中的所述上半导体层的所述一部分生长的第一部分；以及从所述第一带中的所述下半导体层的所述一部分生长的第二部分，其中，所述附加的半导体材料的第一部分和第二部分具有不同的顶面取向并且彼此合并。
在上述方法中，所述图案化步骤使得在所述第一带与所述第二带之间形成间隙，其中所述下半导体层的顶面直接位于所述凹槽下方并且暴露于所述凹槽，并且形成切口以从所述下半导体层的顶面向下延伸至所述下半导体层内。
在上述方法中，所述切口在被蚀刻的竖直间隔件的正下方的位置处。
根据本发明的又一些实施例，还提供了一种半导体器件，包括：块状半导体层，具有第一顶面取向；第一半导体带和第二半导体带，位于所述块状半导体层上方并连接至所述块状半导体层，其中，所述第一半导体带和所述第二半导体带具有不同的顶面取向；隔离区域，介于所述第一半导体带与所述第二半导体带之间，所述隔离区域包括从所述隔离区域的底面向下突出的突出部分，其中，所述底面在所述隔离区域的突出部分的相对两侧上；第一源极/漏极区域，覆盖所述第一半导体带，其中，所述第一源极/漏极区域是n型鳍式场效应晶体管(FinFET)的一部分；以及第二源极/漏极区域，覆盖所述第二半导体带，其中，所述第二源极/漏极区域是p型FinFET的一部分。
在上述半导体器件中，所述第二源极/漏极区域具有第一顶面取向，并且所述第一源极/漏极区域具有与所述第一顶面取向不同的第二顶面取向。
在上述半导体器件中，所述第一源极/漏极区域具有(110)顶面取向，并且所述第二源极/漏极区域具有(100)顶面取向。
在上述半导体器件中，所述第一源极/漏极区域具有(100)R45顶面取向，并且所述第二源极/漏极区域具有(100)顶面取向。
在上述半导体器件中，所述第一源极/漏极区域包括：上部和下部，其中，所述上部和所述下部具有不同的顶面取向，其中，所述上部和所述下部的接合处高于所述隔离区域的顶面。
在上述半导体器件中，所述隔离区域的突出部分位于所述第一半导体带与所述第二半导体带之间的中间处。
以上论述了若干实施例的部件，使得本领域的技术人员可以更好地理解本发明的各个实施例。本领域技术人员应该理解，可以很容易地使用本发明作为基础来设计或更改其他的处理和结构以用于达到与本发明所介绍实施例相同的目的和/或实现相同优点。本领域技术人员也应该意识到，这些等效结构并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，可以进行多种变化、替换以及改变。

Claims (10)

1.一种形成半导体器件的方法，包括：
蚀刻混合衬底以形成延伸至所述混合衬底内的凹槽，其中，所述混合衬底包括：
第一半导体层，具有第一表面取向；
介电层，位于所述第一半导体层上方；和
第二半导体层，具有与所述第一表面取向不同的第二表面取向，其中，在所述蚀刻之后，所述第一半导体层的顶面暴露于所述凹槽；
在所述凹槽的侧壁上形成间隔件，其中，所述间隔件接触所述介电层的侧壁和所述第二半导体层的侧壁；
实施外延以从所述第一半导体层生长外延半导体区域；以及
去除所述间隔件。
2.根据权利要求1所述的方法，还包括：
在去除所述间隔件之后，实施第一图案化步骤，其中，通过所述第一图案化步骤图案化所述第二半导体层、所述介电层和所述第一半导体层以形成第一半导体带。
3.根据权利要求2所述的方法，还包括：
当实施所述第一图案化步骤时，同时实施第二图案化步骤，其中，图案化所述外延半导体区域和所述第一半导体层以形成第二半导体带。
4.根据权利要求2所述的方法，其中，在所述第一图案化步骤期间，所述第一半导体层的直接位于去除的间隔件下方的部分被凹进以形成从所述第一半导体层的顶面向下延伸的切口，并且所述第一半导体层的顶面延伸至所述切口的相对两侧。
5.根据权利要求2所述的方法，还包括：
在所述第一半导体带的相对两侧上形成隔离区域；
对所述隔离区域进行凹进，其中，所述第一半导体带的顶部突出为高于所述隔离区域的剩余部分的顶面以形成鳍；以及
基于所述鳍形成鳍式场效应晶体管(FinFET)。
6.根据权利要求1所述的方法，其中，通过湿蚀刻步骤实施所述间隔件的去除。
7.根据权利要求1所述的方法，其中，在去除所述间隔件之后，形成间隙以将所述外延半导体区域与所述介电层和所述第二半导体层的剩余部分分离。
8.一种形成半导体器件的方法，包括：
蚀刻混合衬底以形成凹槽，其中，所述凹槽穿透上半导体层和介电层，其中，位于所述介电层下面的下半导体层的顶面暴露于所述凹槽；
在所述凹槽的侧壁上形成竖直间隔件；
实施外延以从所述下半导体层生长外延半导体区域；
蚀刻所述竖直间隔件，从而通过间隙将所述外延半导体区域与所述上半导体层和所述介电层间隔开；以及
进行图案化步骤以形成第一带和第二带，其中，所述第一带包括所述上半导体层的一部分、所述介电层的一部分以及所述下半导体层的一部分，并且所述第二带包括所述外延半导体区域的一部分。
9.根据权利要求8所述的方法，还包括：
在蚀刻所述竖直间隔件之后并且在所述图案化步骤之前，在所述上半导体层和所述外延半导体区域上方沉积硅层。
10.一种半导体器件，包括：
块状半导体层，具有第一顶面取向；
第一半导体带和第二半导体带，位于所述块状半导体层上方并连接至所述块状半导体层，其中，所述第一半导体带和所述第二半导体带具有不同的顶面取向；
隔离区域，介于所述第一半导体带与所述第二半导体带之间，所述隔离区域包括从所述隔离区域的底面向下突出的突出部分，其中，所述底面在所述隔离区域的突出部分的相对两侧上；
第一源极/漏极区域，覆盖所述第一半导体带，其中，所述第一源极/漏极区域是n型鳍式场效应晶体管(FinFET)的一部分；以及
第二源极/漏极区域，覆盖所述第二半导体带，其中，所述第二源极/漏极区域是p型FinFET的一部分。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113793834A (zh) * 2020-08-24 2021-12-14 台湾积体电路制造股份有限公司 半导体器件及其形成方法
CN114284212A (zh) * 2021-06-02 2022-04-05 青岛昇瑞光电科技有限公司 FinFET结构及其制备方法

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10707073B2 (en) * 2017-09-05 2020-07-07 Asm Ip Holding B.V. Film forming method and patterning method
US10930569B2 (en) 2018-07-31 2021-02-23 Taiwan Semiconductor Manufacturing Co., Ltd. Dual crystal orientation for semiconductor devices
US11037783B2 (en) * 2018-09-25 2021-06-15 Taiwan Semiconductor Manufacturing Co., Ltd. Field effect transistor using transition metal dichalcogenide and a method for forming the same
US10797049B2 (en) * 2018-10-25 2020-10-06 Globalfoundries Inc. FinFET structure with dielectric bar containing gate to reduce effective capacitance, and method of forming same
CN117038459A (zh) * 2019-01-21 2023-11-10 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
KR20210022814A (ko) 2019-08-20 2021-03-04 삼성전자주식회사 반도체 소자
US11121132B2 (en) * 2019-11-08 2021-09-14 Qualcomm Incorporated Gate-cut isolation structure and fabrication method
CN111029406A (zh) * 2019-11-14 2020-04-17 中国科学院微电子研究所 一种半导体器件及其制备方法
US11545490B2 (en) * 2019-12-17 2023-01-03 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure and method for forming the same
US20210202472A1 (en) * 2019-12-27 2021-07-01 Intel Corporation Integrated circuit structures including backside vias
US11705372B2 (en) 2020-02-11 2023-07-18 Taiwan Semiconductor Manufacturing Co., Ltd. Fin loss prevention
US11723193B2 (en) * 2020-06-30 2023-08-08 Taiwan Semiconductor Manufacturing Company Limited Memory devices and methods of manufacturing thereof
US11742247B2 (en) 2020-07-17 2023-08-29 Synopsys, Inc. Epitaxial growth of source and drain materials in a complementary field effect transistor (CFET)
US20220020647A1 (en) * 2020-07-17 2022-01-20 Synopsys, Inc. Self-limiting manufacturing techniques to prevent electrical shorts in a complementary field effect transistor (cfet)
US11710634B2 (en) 2020-07-17 2023-07-25 Synopsys, Inc. Fabrication technique for forming ultra-high density integrated circuit components
US11915984B2 (en) 2020-07-17 2024-02-27 Synopsys, Inc. Forming a wrap-around contact to connect a source or drain epitaxial growth of a complimentary field effect transistor (CFET) to a buried power rail (BPR) of the CFET
US20230197812A1 (en) * 2021-12-16 2023-06-22 Intel Corporation Hybrid channel region for gate all around (gaa) transistor structures

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080020521A1 (en) * 2004-06-21 2008-01-24 International Business Machines Corporation Hybrid substrate technology for high-mobility planar and multiple-gate mosfets
CN102099902A (zh) * 2008-07-21 2011-06-15 超威半导体公司 带有沟道分隔的鳍状半导体设备生产方法
US20130175618A1 (en) * 2012-01-05 2013-07-11 International Business Machines Corporation Finfet device
US20150333086A1 (en) * 2014-05-19 2015-11-19 Stmicroelectronics, Inc Method for making semiconductor device with different fin sets

Family Cites Families (41)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070063306A1 (en) * 2005-09-22 2007-03-22 Intel Corporation Multiple crystal orientations on the same substrate
US8319285B2 (en) * 2005-12-22 2012-11-27 Infineon Technologies Ag Silicon-on-insulator chip having multiple crystal orientations
US7595232B2 (en) 2006-09-07 2009-09-29 International Business Machines Corporation CMOS devices incorporating hybrid orientation technology (HOT) with embedded connectors
US7569857B2 (en) * 2006-09-29 2009-08-04 Intel Corporation Dual crystal orientation circuit devices on the same substrate
US7897994B2 (en) 2007-06-18 2011-03-01 Texas Instruments Incorporated Method of making (100) NMOS and (110) PMOS sidewall surface on the same fin orientation for multiple gate MOSFET with DSB substrate
EP2073267A1 (en) * 2007-12-19 2009-06-24 INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM vzw (IMEC) Method of fabricating multi-gate semiconductor devices and devices obtained
JP2014093319A (ja) * 2012-10-31 2014-05-19 Toshiba Corp 半導体装置およびその製造方法
US20140353767A1 (en) * 2013-05-31 2014-12-04 Stmicroelectronics, Inc. Method for the formation of fin structures for finfet devices
CN104218082B (zh) * 2013-06-04 2017-08-25 中芯国际集成电路制造(上海)有限公司 高迁移率鳍型场效应晶体管及其制造方法
KR102155181B1 (ko) * 2014-01-28 2020-09-11 삼성전자주식회사 반도체 장치 및 그 제조 방법
US9443963B2 (en) * 2014-04-07 2016-09-13 International Business Machines Corporation SiGe FinFET with improved junction doping control
US9490161B2 (en) * 2014-04-29 2016-11-08 International Business Machines Corporation Channel SiGe devices with multiple threshold voltages on hybrid oriented substrates, and methods of manufacturing same
US9257505B2 (en) 2014-05-09 2016-02-09 Taiwan Semiconductor Manufacturing Co., Ltd. Structures and formation methods of finFET device
US9536900B2 (en) 2014-05-22 2017-01-03 Globalfoundries Inc. Forming fins of different semiconductor materials on the same substrate
US9299618B1 (en) * 2014-09-24 2016-03-29 International Business Machines Corporation Structure and method for advanced bulk fin isolation
US9484346B2 (en) * 2014-10-15 2016-11-01 Taiwan Semiconductor Manufacturing Company Ltd Semiconductor structure and manufacturing method thereof
US9502243B2 (en) * 2014-12-22 2016-11-22 International Business Machines Corporation Multi-orientation SOI substrates for co-integration of different conductivity type semiconductor devices
US9508741B2 (en) 2015-02-10 2016-11-29 International Business Machines Corporation CMOS structure on SSOI wafer
KR102310076B1 (ko) * 2015-04-23 2021-10-08 삼성전자주식회사 비대칭 소스/드레인 포함하는 반도체 소자
LT3294770T (lt) * 2015-05-12 2020-12-28 F. Hoffmann-La Roche Ag Vėžio gydymo ir diagnostikos būdai
US9741623B2 (en) * 2015-08-18 2017-08-22 Globalfoundries Inc. Dual liner CMOS integration methods for FinFET devices
US9954083B2 (en) * 2015-08-20 2018-04-24 International Business Machines Corporation Semiconductor structures having increased channel strain using fin release in gate regions
DE112015006854T5 (de) * 2015-08-28 2018-05-17 Intel Corporation Verfahren und Vorrichtungen zum Integrieren von III-N-Transistorschaltungen mit SI-Transistorschaltungen
KR102427326B1 (ko) * 2015-10-26 2022-08-01 삼성전자주식회사 반도체 소자 및 이의 제조 방법
US10084090B2 (en) * 2015-11-09 2018-09-25 International Business Machines Corporation Method and structure of stacked FinFET
US9490255B1 (en) * 2015-12-01 2016-11-08 International Business Machines Corporation Complementary metal oxide semiconductor replacement gate high-k metal gate devices with work function adjustments
US9786505B2 (en) * 2015-12-30 2017-10-10 Taiwan Semiconductor Manufacturing Co., Ltd. FinFET device using dummy fins for smooth profiling
US9805982B1 (en) * 2016-05-17 2017-10-31 Globalfoundries Inc. Apparatus and method of adjusting work-function metal thickness to provide variable threshold voltages in finFETs
US10355110B2 (en) * 2016-08-02 2019-07-16 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET and method of forming same
US9711507B1 (en) * 2016-09-30 2017-07-18 International Business Machines Corporation Separate N and P fin etching for reduced CMOS device leakage
US10002868B2 (en) * 2016-09-30 2018-06-19 International Business Machines Corporation Vertical fin resistor devices
US10074567B2 (en) * 2016-10-21 2018-09-11 QROMIS, Inc. Method and system for vertical integration of elemental and compound semiconductors
US10164042B2 (en) * 2016-11-29 2018-12-25 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
US10707328B2 (en) * 2016-11-30 2020-07-07 Taiwan Semiconductor Manufacturing Co., Ltd. Method of forming epitaxial fin structures of finFET
US10804161B2 (en) * 2016-12-15 2020-10-13 Taiwan Semiconductor Manufacturing Company, Ltd. CMOS FinFET structures including work-function materials having different proportions of crystalline orientations and methods of forming the same
US10043888B2 (en) * 2016-12-27 2018-08-07 United Microelectronics Corp. Method for forming a semiconductor structure
US10177046B2 (en) * 2017-02-17 2019-01-08 International Business Machines Corporation Vertical FET with different channel orientations for NFET and PFET
US10163731B2 (en) * 2017-04-12 2018-12-25 Taiwan Semiconductor Manufacturing Co., Ltd. FinFET semiconductor structure having hybrid substrate and method of fabricating the same
US9991262B1 (en) * 2017-06-15 2018-06-05 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device on hybrid substrate and method of manufacturing the same
US10541319B2 (en) * 2017-08-30 2020-01-21 Taiwan Semiconductor Manufacturing Co., Ltd. Fin structures having varied fin heights for semiconductor device
US10475654B2 (en) * 2017-08-31 2019-11-12 Taiwan Semiconductor Manufacturing Company, Ltd. Wrap-around contact plug and method manufacturing same

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080020521A1 (en) * 2004-06-21 2008-01-24 International Business Machines Corporation Hybrid substrate technology for high-mobility planar and multiple-gate mosfets
CN102099902A (zh) * 2008-07-21 2011-06-15 超威半导体公司 带有沟道分隔的鳍状半导体设备生产方法
US20130175618A1 (en) * 2012-01-05 2013-07-11 International Business Machines Corporation Finfet device
US20150333086A1 (en) * 2014-05-19 2015-11-19 Stmicroelectronics, Inc Method for making semiconductor device with different fin sets

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113793834A (zh) * 2020-08-24 2021-12-14 台湾积体电路制造股份有限公司 半导体器件及其形成方法
CN113793834B (zh) * 2020-08-24 2024-05-24 台湾积体电路制造股份有限公司 半导体器件及其形成方法
CN114284212A (zh) * 2021-06-02 2022-04-05 青岛昇瑞光电科技有限公司 FinFET结构及其制备方法
CN114284212B (zh) * 2021-06-02 2023-12-26 青岛昇瑞光电科技有限公司 FinFET结构及其制备方法

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