TW201913750A - 半導體元件及其製造方法 - Google Patents

半導體元件及其製造方法 Download PDF

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TW201913750A
TW201913750A TW106135537A TW106135537A TW201913750A TW 201913750 A TW201913750 A TW 201913750A TW 106135537 A TW106135537 A TW 106135537A TW 106135537 A TW106135537 A TW 106135537A TW 201913750 A TW201913750 A TW 201913750A
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semiconductor
layer
semiconductor layer
region
strip
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TW106135537A
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TWI645461B (zh
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江國誠
朱熙甯
蔡慶威
程冠倫
王志豪
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台灣積體電路製造股份有限公司
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Abstract

本揭露之半導體元件製造方法包括蝕刻混合基板以形成延伸進混合基板之凹陷。混合基板包括具有第一表面取向之第一半導體層、在第一半導體層上方之介電質層，及具有不同於第一表面取向之第二表面取向之第二半導體層。在蝕刻之後，第一半導體層之頂表面暴露於凹陷。間隔物在凹陷側壁上形成。間隔物接觸介電質層之側壁及第二半導體層之側壁。執行磊晶以從第一半導體層生長磊晶半導體區域。去除間隔物。

Description

較佳效能之混合式P型與N型鰭式場效電晶體
本揭露有關於一種半導體元件及其製造方法。
隨著積體電路之日益縮小及對積體電路速度之要求越來越多，電晶體隨著越來越小之尺寸需要具有更高驅動電流。因此發展了鰭式場效電晶體(Fin Field-Effect Transistors；FinFETs)。在常規FinFET形成過程中，半導體鰭片藉由在矽基板中形成溝槽、使用介電質材料填充溝槽以形成淺溝槽隔離(Shallow Trench Isolation；STI)區域、隨後凹下STI區域之頂端部位來形成。STI區域之凹陷部分之間的矽基板部分因此形成半導體鰭片，在其上形成FinFET。
在本揭露的一實施方式中，提出一種半導體元件製造方法，包含以下步驟：蝕刻混合基板以形成延伸進混合基板之凹陷，其中混合基板包含第一半導體層、介電質層以及第二半導體層。混合基板的第一半導體層具有第一表面取向，且 介電質層在第一半導體層上方，且第二半導體層具有不同於第一表面取向之第二表面取向，其中在蝕刻之後，第一半導體層之頂表面暴露於凹陷；在凹陷之側壁上形成間隔物，其中間隔物接觸介電質層之側壁及第二半導體層之側壁；執行磊晶以從第一半導體層生長磊晶半導體區域；以及去除該間隔物。
本揭露之另一面向，提出一種半導體元件製造方法，包含以下步驟：蝕刻混合基板以形成凹陷，其中凹陷穿透上部半導體層及介電質層，其中在介電質層底下之下部半導體層之頂表面暴露於凹陷；在凹陷之側壁上形成垂直間隔物；執行磊晶以從下部半導體層生長磊晶半導體區域；蝕刻垂直間隔物以便磊晶半導體區域與上部半導體層及介電質層分別分隔一縫隙；以及執行圖案化步驟以形成第一條及第二條，其中第一條包含上部半導體層之一部分、介電質層之一部分、及下部半導體層之一部分，以及第二條包含磊晶半導體區域之一部分。
本揭露之又一面向，提出一種半導體元件，包含塊材半導體層、第一半導體條及第二半導體條、隔離區、第一源極/汲極區以及第二源極/汲極區。塊材半導體層具有第一頂表面取向。第一半導體條及一第二半導體條在塊材半導體層上方並連接至塊材半導體層，其中第一半導體條的頂表面取向與第二半導體條的頂表面取向不同。隔離區在第一半導體條與第二半導體條之間，隔離區包含從隔離區之底表面向下突出之突出部分，其中底表面在隔離區之突出部分之相對側上。第一源極/汲極區，與第一半導體條重疊，其中第一源極/汲極區為N 型鰭式場效電晶體之一部分。第二源極/汲極區與第二半導體條重疊，其中第二源極/汲極區為P型鰭式場效電晶體之一部分。
20‧‧‧混合基板
22、26、28‧‧‧矽層
24‧‧‧介電質層
34‧‧‧半導體層
30‧‧‧覆蓋層
32‧‧‧間隔物
35、36、44‧‧‧凹陷
38‧‧‧保護層
40‧‧‧遮罩
40A、40B‧‧‧層
46‧‧‧凹口
48‧‧‧襯墊
50‧‧‧STI區域
50'‧‧‧向下突出部位
52‧‧‧介電質襯墊
54‧‧‧介電質區域
58‧‧‧虛設閘極堆疊
60‧‧‧虛設閘極介電質
62‧‧‧虛設閘電極
64‧‧‧硬遮罩層
66‧‧‧間隔物層
68‧‧‧間隔物
70‧‧‧縫隙
76‧‧‧CESL
78‧‧‧ILD
80‧‧‧替換閘極介電質
82‧‧‧閘電極
84‧‧‧替換閘極
86‧‧‧介電質硬遮罩
88‧‧‧接觸塞
90‧‧‧矽化物區域
90A、90B、92A、92B、92C‧‧‧線
122、124、127、222、234‧‧‧部位
142‧‧‧條
156‧‧‧鰭片
172、172A、172B‧‧‧磊晶區域
173‧‧‧空隙
174‧‧‧源極/汲極區
192‧‧‧N型FinFET
100、200‧‧‧裝置區域
242‧‧‧條
256‧‧‧鰭片
272‧‧‧磊晶區域
274‧‧‧源極及汲極區
292‧‧‧P型FinFET
300‧‧‧流程圖
302、304、306、308、310、312、314、316、318、320、322、324‧‧‧步驟
當結合附圖閱讀時，自以下詳細描述很好地理解本揭示案之態樣。應當注意，根據工業中標準實務，各特徵未按比例繪製。事實上，為論述清楚，各特徵之大小可任意地增加或縮小。
第1圖至第16圖繪示根據一些實施方式之在形成鰭式場效電晶體(FinFET)過程中之中間階段的橫剖面圖及立體圖。
第17A圖繪示根據一些實施方式之作為鰭片寬度之函數的電子遷移率。
第17B圖繪示根據一些實施方式之作為鰭片寬度之函數的電洞遷移率。
第18圖繪示根據一些實施方式之用於形成FinFET的流程圖。
應理解，以下揭示案提供許多不同實施方式或例子，為實現本揭露之不同的特徵。下文描述之組件及排列之特定之實例為了簡化本揭示案。當然，此等僅僅為實例且不意指限制。舉例而言，在隨後描述中在第二特徵上方或在第二特徵上第一特徵之形成可包括第一及第二特徵形成為直接接觸之實施方式，以及亦可包括額外特徵可形成在第一及第二特徵之間，使得第一及第二特徵可不直接接觸之實施方式。另外，本 揭示案在各實例中可重複元件符號及/或字母。重複為出於簡易及清楚之目的，且本身不指示所論述各實施方式及/或結構之間之關係。
另外，空間相對術語，諸如「底層」、「低於」、「下部」、「重疊」、「上部」等，可在本文用以便於描述，以描述如在附圖中繪示之一個元件或特徵相對另一元件或特徵的關係。除圖形中描繪之方向外，空間相對術語意圖是包含裝置在使用或操作中之不同的方向。裝置可為不同之朝向(旋轉90度或在其他的方向)及在此使用之空間相對描述詞可因此同樣地解釋。
根據各示範性實施方式，提供了在混合基板上形成鰭式場效電晶體(FinFET)的方法以及所得結構。根據一些實施方式繪示了形成混合基板及FinFET之中間階段。論述一些實施方式之一些變化。貫穿各視圖及說明性實施方式，相同元件符號用以指示相同元件。
第1圖至第16圖繪示根據本揭示案之一些實施方式之在形成混合基板及FinFET過程中的中間階段的橫剖面圖及立體圖。在第1圖至第16圖中繪示之步驟亦示意地反映在第18圖中繪示之流程圖300。
參看第1圖，提供混合基板20。混合基板20包括晶體矽層22、矽層22上方之介電質層24、及介電質層24上方之晶體矽層26。介電質層24可以由氧化矽或其他介電質材料(諸如氮化矽、碳化矽等等)形成。介電質層24之厚度可以在約5奈米與約15奈米之間的範圍中，並且可以採用不同厚度。本領域中通常技藝者將理解整個描述中敘述之尺寸僅僅為實 例，並且可以轉變為不同數值。矽層26經接合至介電質層24。混合基板20包括N型裝置區域100中之第一部位及P型裝置區域200中之第二部位。
矽層22為具有(100)表面取向之(100)基板，其中矽層22之頂表面在矽之(100)平面中。根據一些實施方式，矽層26為具有(110)表面取向之(110)基板，其中矽層26之頂表面在矽之(110)平面中。根據本揭示案之另一個實施方式，矽層26為(100)R45層，其藉由(100)基板在切斷及接合至介電質層24之前旋轉45度而形成。因此，(100)R45層之頂表面具有(100)R45表面取向，以及所得鰭片之側壁(參看第7B圖論述)亦在矽之(100)平面上。
參看第2圖，執行磊晶以在矽層26上生長矽層28。各別步驟經繪示為在第18圖中繪示之流程圖中的步驟302。根據矽層26之取向，矽層28可以為具有在矽之(110)平面上之頂表面的(110)層，或可以為(100)R45層。矽層28可以不含鍺。此外，矽層28可以為本徵的，其中未有P型及N型雜質摻雜在磊晶中。根據另一個實施方式，矽層28在磊晶期間原位摻雜P型雜質。矽層28之厚度可與所得FinFET的鰭片高度相近。
第3圖繪示在P型裝置區域200中凹陷矽層28及混合基板20，以及此凹陷未在N型裝置區域100中執行。各別步驟經繪示為在第18圖中繪示之流程圖中的步驟304。如此形成凹陷35。根據本揭示案之一些實施方式，為執行凹陷，覆蓋層30首先形成為毯覆平面層，例如經由熱氧化或沉積。覆蓋層30可以由氧化矽或其他介電質材料(諸如氮化矽、碳化矽或氮氧 化矽)形成。隨後執行凹陷。在凹陷期間，覆蓋層30、矽層28及矽層26經蝕穿，從而暴露底下介電質層24之頂表面，隨後蝕刻此頂表面。因此暴露具有(100)表面平面之矽層22。
接下來，沉積間隔物層，之後進行各向異性蝕刻以去除間隔物層之水平部位，以便形成間隔物32。各別步驟經繪示為在第18圖中繪示之流程圖中的步驟306。間隔物層由不同於覆蓋層30之材料的材料形成。根據本揭示案之一些實施方式，間隔物32由介電質材料(諸如氧化鋁(Al2O3)、氮化矽等等)形成。由於形成覆蓋層30及間隔物32之不同材料，覆蓋層30在形成間隔物32之後保留。因此，屏蔽矽層26及矽層28之側壁及頂表面兩者。
第4圖繪示半導體層34之選擇性磊晶。各別步驟經繪示為在第18圖中繪示之流程圖中的步驟308。根據本揭示案之一些實施方式，半導體層34由高遷移率半導體材料所形成，半導體材料諸如矽鍺、鍺(沒有矽)、III-V族化合物半導體諸如GaAs、InP、GaN、InGaAs、InAlAs、GaSb、AlSb、AlAs、AlP、GaP、其組合、或其多層。在選擇性磊晶中，在處理氣體中添加諸如HCl之蝕刻氣體，以便半導體層34從矽層22之頂表面生長，而非從諸如覆蓋層30及間隔物32之介電質材料生長。間隔物32屏蔽矽層26及矽層28之側壁，以便達成單一表面(矽層22之頂表面)磊晶，因此避免由從不同表面生長導致之缺陷。因為半導體層34從矽層22磊晶生長，所以它具有與矽層22相同的表面取向，並且具有(100)表面取向。
在半導體層34之選擇性磊晶之後，執行諸如化學機械拋光(Chemical Mechanical Polish；CMP)或機械研磨之 平坦化步驟以使半導體層34頂表面平整。根據本揭示案之一些實施方式，使用矽層28作為停止層執行平坦化。根據本揭示案之另一個實施方式，使用覆蓋層30作為停止層執行平坦化，之後進行蝕刻製程以去除覆蓋層30。
在平坦化之後，去除如在第4圖中繪示之間隔物32，以及所得結構在第5A圖及第5B圖中繪示。各別步驟經繪示為在第18圖中繪示之流程圖中的步驟310。第5A圖繪示了結構之立體圖，以及第5B圖繪示了結構之剖面圖。如在第5A圖及第5B圖兩者中繪示，由於間隔物32之去除生成凹陷(縫隙)36，以及凹陷36將矽層26及矽層28與半導體層34分隔。根據本揭示案之一些實施方式，透過濕式蝕刻製程去除間隔物32。例如，當間隔物32由氮化矽形成時，可以使用磷酸執行蝕刻。
參看第6圖，形成保護層38。根據本揭示案之一些實施方式，保護層38由矽形成，並且沉積在如在第5A圖中繪示之結構的頂表面上。保護層38亦不含鍺。沉積可以經由磊晶製程達成，使得矽層為晶體層。根據本揭示案之另一個實施方式，保護層38為多晶矽層。保護層38可以形成跨越凹陷36之橋樑，而保護層38之一些沉積材料可以落入凹陷36中。
如在第6圖及第7A圖及第7B圖中繪示之以下步驟說明了半導體條之形成。條可以藉由任何適宜方法圖案化。例如，條可以使用包括雙重圖案化或多重圖案化製程之一或多個光微影製程來圖案化。一般而言，雙重圖案化或多重圖案化製程將光微影及自對準製程組合在一起，從而允許要產生之圖案具有例如小於另外使用單個直接光微影製程可獲得之間距的間距。例如，在一個實施方式中，犧牲層在基板上方形成並 使用光微影製程圖案化。使用自對準製程將間隔物與圖案化之犧牲層並排形成。隨後去除犧牲層，而剩餘間隔物或心軸可以隨後用以圖案化條。
根據如在第6圖中繪示之一些示範性實施方式，遮罩層沉積在保護層38上方，及隨後經圖案化以形成遮罩40，其用作形成半導體條之蝕刻遮罩。根據本揭示案之一些實施方式，遮罩40包括由不同材料形成之複數個層。例如，遮罩40可以包括由氧化矽形成之層40A、及在各別遮罩40上方之層40B，其中層40B由氮化矽形成。在形成遮罩40之過程中，保護層38保護底下半導體層34免於氧化，例如，由於在遮罩40之沉積過程中採用的高溫而導致的氧化。矽鍺易於氧化，及亦具有比矽之氧化速度顯著更高的氧化速度。因此，藉由形成保護層38，避免半導體層34不合需要的氧化。
參看第7A圖及第7B圖，執行蝕刻製程以蝕刻基板及半導體層，使得條142及條242分別形成於N型裝置區域100及P型裝置區域200中。各別步驟經繪示為在第18圖中繪示之流程圖中的步驟312。形成凹陷44以將條142與條242分隔。條142包括部位122、部位124及部位127。條部位122為圖案化矽層22之剩餘部位。條部位124為介電質層24之剩餘部位(第6圖)。條部位127為矽層26及矽層28之剩餘部位(第6圖)。根據本揭示案之一些實施方式，矽層26及矽層28(第6圖)具有(110)頂表面取向。因此，條部位127亦具有(110)頂表面取向。根據本揭示案之一些實施方式，矽層26及矽層28為(100)R45層。因此，條142之頂表面及側壁兩者具有(100)表面取向。條242包括部位222及部位234。條部位222為圖案化矽層22 之剩餘部位。條部位234為半導體層34之剩餘部位(第6圖)。因此，條部位234亦具有(100)頂表面取向。
第7A圖繪示了在條形成之後的結構的立體圖。第7B圖繪示了在第7A圖中繪示之結構的剖面圖。在第7B圖，條部位127之所繪示頂表面可以在(100)表面平面或(110)表面平面上，以及條部位127之左及右側壁在(100)表面平面上。條部位234之繪示頂表面可以在(100)表面平面上，以及條部位234之左及右側壁表面可以在(110)平面上。
如亦在第7A圖及第7B圖中繪示，在用於形成條142及條242之圖案化中，亦蝕刻在凹陷36正下方之矽層22之部位(第6圖)，由此形成凹口46以延伸進矽層22中。因為蝕刻矽層22穿過深且狹窄凹陷36緩慢，所以凹口46具有小於半導體層34之厚度(第6圖)之深度D1。根據一些實施方式，深度D1(第7B圖)在約5奈米與約40奈米之間的範圍中。凹口46之頂部寬度W1可以在約3奈米與約10奈米之間的範圍中。條142及條242之寬度W2可以在約4奈米與約6奈米之間的範圍中。如若在第7A圖及第7B圖之俯視圖中觀察，凹口46及條142及條242為全部具有彼此平行之縱向的細長條。
凹口46可以具有大於約0.5之深寬比，以及深寬比根據一些實施方式可以在約0.5與約5.0之間的範圍中。深寬比例如受凹陷36之深度及寬度影響。應理解，儘管第7A圖及第7B圖繪示了凹口46具有直側壁及平面底部，但凹口46之側壁及底部可以為圓弧。例如，凹口46之側壁可為連續弧形，並連接至弧形的底部。凹口46之側壁亦可為大體上直的，其連接至弧形底部。凹口46亦可經小面化，以及可以具有直邊緣及平 坦的底表面之U形剖面。凹口46亦可為具有V形剖面圖之小面。亦設想其他形狀。
如在第4圖至第7A圖及第7B圖中繪示，如若間隔物32(第4圖)未在形成保護層38及遮罩40之前去除，則在如在第7A圖及第7B圖中繪示之圖案化步驟中，將剩下間隔物32，並且亦將保護矽層22之底下部位，使得將形成包括間隔物32及矽層22之底下部位的狹窄高條。此條可以在諸如形成STI(淺溝槽隔離)區域50(第9圖)之後續製程中破裂，因此導致缺陷。根據本揭示案之一些實施方式，間隔物32之去除避免缺陷之生成。因此，凹口46在N型裝置區域100與P型裝置區域200之間的界面區處形成。根據本揭示案之一些實施方式，凹口46在條142及條242之中間，例如其中距離S1及距離S2的差小於距離S1及距離S2之任一個的約百分之20或小於約百分之10。在凹口46在條142與條242之中間的情況下，S1及S2兩者可以保持最小，同時仍然在P型與N型FinFET之間留下足夠的間距，由此可以最大化所得FinFET的密度。
第8圖繪示第一襯墊48之形成，其用以屏蔽條部位234之側壁氧化。根據本揭示案之一些實施方式，襯墊48由矽形成，並且不含或大體上不含鍺(例如，其中鍺原子百分率(若有)低於約百分之5)。此外，襯墊48可以不含氧及氮，因此不包括氧化矽及氮化矽。襯墊48之形成可以使用諸如原子層沉積(Atomic Layer Deposition；ALD)或化學氣相沉積(Chemical Vapor Deposition；CVD)之共形沉積方法來執行。襯墊48因此延伸進凹陷44及凹口46中。此外，襯墊48部分地填充凹口46，並留下凹口46之部分未填充。
第9圖繪示了STI區域50之形成，其包括介電質襯墊52及在介電質襯墊52上方之介電質區域54。各別步驟經繪示為在第18圖中繪示之流程圖中的步驟314。根據本揭示案之一些實施方式，共形沉積方法用以在第8圖中繪示之結構的暴露表面上沉積共形介電質襯墊52。例如，介電質襯墊52可以使用ALD或CVD形成。接下來，凹陷44之剩餘部位(第8圖)充滿介電質區域54。介電質區域54可以使用可流動的化學氣相沉積(FCVD)、旋塗等等來形成。根據其中使用FCVD之一些實施方式，使用含矽及氮的前驅物(例如，三甲矽烷基(TSA)或二甲矽烷基胺(DSA))，因此所得介電質材料為可流動的(膠狀的)。根據本揭示案之替代實施方式，可流動介電質材料使用烷氨基矽烷基前驅物形成。在沉積期間，打開電漿以啟動氣態前驅物形成流動的氧化物。
在介電質襯墊52及介電質區域54之形成過程中，可以提升形成製程之溫度，若暴露條部位234，其可能導致條部位234之氧化。因此襯墊48(第8圖)保護條部位234免於氧化。因此，襯墊48(或接觸條部位124、條部位127及條部位234之襯墊48的至少部分)可以在介電質襯墊52及介電質區域54之形成過程中被氧化，並且因此轉化為氧化矽層。
接下來，在介電質區域54及介電質襯墊52上執行諸如CMP或機械研磨之平坦化。平坦化可以使用作為停止層之遮罩40(第8圖)執行。接下來，去除遮罩40，之後凹陷介電質區域54及介電質襯墊52。各別步驟亦經繪示為在第18圖中繪示之流程圖中的步驟314。所得結構在第9圖中繪示。介電質區域54及介電質襯墊52之剩餘部位稱作STI區域50。根據本揭示 案之一些實施方式，執行凹陷直到凹陷之STI區域50具有低於介電質條部位124之頂表面的頂表面，使得介電質條部位124之側壁具有暴露之至少一些部位。根據本揭示案之替代實施方式，凹陷之STI區域50具有比介電質條部位124之底表面更高、更低或與之齊平的頂表面。貫穿整個描述，高於STI區域50之頂表面的條142及條242之部分稱作鰭片(或突出鰭片)156及鰭片256。凹口46(第8圖)充滿向下突出部位50'，其為STI區域50之一個的部分。
參看第10圖，虛設閘極堆疊58在(突出)鰭片156及鰭片256之頂表面及側壁上形成。各別步驟經繪示為在第18圖中繪示之流程圖中的步驟316。應理解，儘管為清晰起見繪示了一個虛設閘極堆疊58，但可以形成彼此平行的複數個虛設閘極堆疊，其中複數個虛設閘極堆疊跨相同的半導體鰭片156及半導體鰭片256。虛設閘極堆疊58可以包括虛設閘極介電質60及在虛設閘極介電質60上方之虛設閘電極62。虛設閘電極62可以例如使用多晶矽形成，以及亦可使用其他材料。虛設閘極堆疊58亦可包括在虛設閘電極62上方之一個(或複數個)硬遮罩層64。硬遮罩層64可以由氮化矽、碳氮化矽等等形成。虛設閘極堆疊58可以跨單個或複數個突出鰭片156及突出鰭片256及/或STI區域50。虛設閘極堆疊58亦具有垂直於突出鰭片156及突出鰭片256之長度方向的長度方向。
接下來，參看第11圖，沉積間隔物層66。根據本揭示案之一些實施方式，間隔物層66由諸如氮化矽、氮碳化矽(SiCN)等等之介電質材料形成，以及可以具有包括複數個介電 質層之單層結構或多層結構。可以透過諸如ALD或CVD之共形沉積方法執行形成。
第12圖繪示了間隔物層66之蝕刻，從而導致閘極間隔物68在虛設閘極堆疊58之側壁上的形成。各別步驟經繪示為在第18圖中繪示之流程圖中的步驟318。各向異性地執行蝕刻，使得去除突出鰭片156及突出鰭片256上之間隔物層66的部位。在用於形成閘極間隔物68之蝕刻之後，暴露介電質條部位124之一些側壁(第11圖)。根據本揭示案之一些實施方式，執行各向同性蝕刻以蝕刻介電質條部位124，而突出鰭片156及突出鰭片256及間隔物68之半導體部位未被蝕刻。各別步驟經繪示為在第18圖中繪示之流程圖中的步驟320。根據本揭示案之一些實施方式，經由濕式蝕刻執行介電質條部位124之蝕刻。例如，當介電質條部位124由氧化矽形成時，HF溶液可以用作蝕刻劑。在蝕刻介電質條部位124之後，形成縫隙70以將條部位127與底下條部位122分開。根據本揭示案之替代實施方式，在形成閘極間隔物68之後，留下介電質條部位124之至少一些部位以將鰭片部位127與條部位122分開。
在蝕刻介電質條部位124之後，在虛設閘極堆疊58正下方仍然剩餘介電質條部位124之一些部位。介電質條部位124之這些部位未去除，並且用以支撐上覆的條部位127(以下稱為半導體鰭片127)。因此，不在虛設閘極堆疊58正下方之鰭片部位127的部分懸掛在縫隙70上方。條部位122之頂表面亦暴露於縫隙70。
接下來，磊晶區域172及磊晶區域272藉由在突出鰭片156及突出鰭片256上選擇性生長半導體材料來選擇性地 形成，從而生成在第13A圖及第13B圖中之結構。各別步驟經繪示為在第18圖中繪示之流程圖中的步驟322。磊晶區域172及磊晶區域272在不同磊晶製程中磊晶生長，其中每個包括在磊晶區域172及磊晶區域272之一個上形成遮罩層(未繪示)，使得磊晶區域可以在磊晶區域172及磊晶區域272之另一個上形成。根據所得FinFET為P型FinFET還是N型FinFET，P型或N型雜質可以在磊晶之進行中原位摻雜。例如，磊晶區域172可以由矽磷(SiP)或磷碳矽(SiCP)形成，以及磊晶區域272可以由硼鍺矽(SiGeB)形成。
在磊晶步驟之後，磊晶區域172及條部位127可以進一步植入N型雜質以形成N型FinFET之源極及汲極區174。磊晶區域272及條部位234亦可植入有P型雜質以形成P型FinFET之源極及汲極區274。根據本揭示案之另一個實施方式，當磊晶區域172及磊晶區域272在磊晶期間原位摻雜有P型或N型雜質時，跳過植入步驟。
由於在第12圖中繪示之縫隙70，在磊晶期間，半導體材料從條部位122之頂表面及條部位127之表面兩者同時地生長。從條部位122之頂表面生長的半導體材料之部位表示為磊晶區域172A。從條部位127生長之半導體材料的部位表示為磊晶區域172B，其在剖面圖中環繞對應條部位127。
磊晶區域172A及磊晶區域172B具有相同的組成，其意謂它們由諸如矽、SiP或SiCP等等之相同半導體材料形成，以及磊晶區域172A及磊晶區域172B中之對應元素的原子及重量百分數彼此相同。磊晶區域172A及磊晶區域172B亦可由其他半導體材料形成，此其他半導體材料晶格常數小於條 部位127之晶格常數，使得可以藉由磊晶區域172A及磊晶區域172B施加張應力。例如，可以使用晶格常數小於條部位127之晶格常數的III-V化合物半導體材料。另一方面，條部位122及條部位127具有不同的表面結構。例如，條部位122可以具有(100)頂表面取向，而條部位127可以具有(110)或(100)R45頂表面取向。因此，磊晶區域172A及磊晶區域172B具有不同的表面結構，以及磊晶區域172A具有與條部位122之表面結構相同的的表面結構，以及磊晶區域172B具有與條部位127的表面結構相同的表面結構。磊晶區域172A最後與對應上覆磊晶區域172B合併以形成磊晶區域172。在磊晶區域172A與對應磊晶區域172B之間的界面可能比STI區域50之頂表面更高。第13B圖繪示了如在第13A圖中繪示之磊晶區域172A及磊晶區域172B的剖面圖。
在如在第13A圖及第13B圖中繪示之示範性實施方式中，磊晶區域172A及磊晶區域172B具有圓化之外部側壁。應理解，磊晶區域172A及磊晶區域172B之形狀受各種因素影響，諸如材料、條部位127之形狀、條部位122之頂表面形狀等等。因此，磊晶區域172A及磊晶區域172B之任一個之側壁可以圓化(連續地彎曲)，或小面化(具有在第13B圖中繪示之平面的直部分)。同時，磊晶區域172A與磊晶區域172B之間的界面可以具有不同形狀，其包括但不限於直界面、彎曲界面(如在第13B圖中繪示)，或者包括若干直部分。例如，磊晶區域172B之外部周邊可以具有細長的六邊形形狀，其中垂直邊緣垂直於大於其他側面之相關晶圓之頂表面。
當在條部位122之中心正上方之磊晶區域172A及磊晶區域172B的部位的生長率低於它們對應左邊部位及右邊部位之生長率(如在第13B圖中)時，亦可形成空隙(其可以為真空縫隙或空氣縫隙)173。空隙173可以根據生長率之差異具有不同的形狀。
磊晶區域172A與磊晶區域172B之合併為有利的。因為在相同晶圓/晶粒上之不同類型之裝置將儘可能多地共享形成製程以降低生產成本，所以用於形成FinFET之製程亦可用以形成諸如基板區域之拾取區域的二極體及被動裝置。這些裝置必須具有與源極/汲極區174及源極/汲極區274同時地形成以連接至混合基板22的區域。根據本揭示案之一些實施方式，藉由去除條部位124，使得磊晶區域172A與磊晶區域172B可以合併，二極體及被動裝置可以連接至混合基板22。因此，共享用於形成繪示之FinFET之處理步驟與形成諸如二極體及被動裝置之其他裝置是可行的。根據替代實施方式，介電質條部位124未蝕刻，FinFET根據這些實施方式將具有降低之源極/汲極洩漏。
儘管第13A圖及第13B圖繪示了源極/汲極區174彼此分隔，且源極/汲極區274彼此分隔，應理解，根據磊晶製程持續多長，源極/汲極區174可以彼此合併或彼此保持分隔，以及源極/汲極區274可以彼此合併或彼此保持分隔。同時，磊晶區域172及磊晶區域272之形狀可以類似於繪示之形狀，或具有諸如鏟/菱形形狀之其他形狀。空氣縫隙可以形成於磊晶區域172之合併部位的正下方，及/或磊晶區域272之合併部位的正下方。
第14圖繪示了具有正形成之CESL(Contact Etch Stop Layer，接觸蝕刻停止層)76及ILD(層間介電質)78的結構的立體圖。各別步驟經繪示為在第18圖中繪示之流程圖中的步驟324。CESL 76可以由氮化矽、碳氮化矽等等形成。例如，CESL 76可以使用諸如ALD之共形沉積方法形成。ILD 78可以包括使用例如FCVD、旋塗、CVD或其他沉積方法形成之介電質材料。ILD 78亦可由正矽酸四乙酯(TEOS)氧化物、電漿增強化學氣相沉積(PECVD)氧化物(SiO2)、磷矽玻璃(PSG)、硼矽玻璃(BSG)、硼摻雜磷矽酸鹽玻璃(BPSG)等等形成。可以執行諸如CMP或機械研磨之平坦化步驟以使ILD 78、虛設閘極堆疊58及閘極間隔物68之頂表面彼此齊平。
接下來，包括硬遮罩層64、虛設閘電極62及虛設閘極介電質60之虛設閘極堆疊58替換為替換閘極84，其包括如在第15A圖、第15B圖、第15C圖、第15D圖、第15E圖及第15F圖中繪示之金屬閘極82及替換閘極介電質80。在去除虛設閘極堆疊58之過程中，先前被埋置在虛設閘極堆疊58以下之介電質條部位124(第9圖)被暴露，並且由於其材料與虛設閘極介電質60之材料之類似而至少橫向地凹陷。根據本揭示案之一些實施方式，在去除虛設閘極堆疊58之後，進一步執行額外蝕刻製程(其可以為濕式蝕刻製程)，如若條部位124之材料不同於STI區域50之材料，使得去除條部位124而不損壞STI區域50。
當替換閘極堆疊時，首先在一個或複數個蝕刻步驟中去除硬遮罩層64、虛設閘電極62及虛設閘極介電質60(第14圖)，從而產生在閘極間隔物68之間形成的溝槽(開口)。在形成替換閘極84過程中，首先形成替換閘極介電層80(第 15A圖)，其延伸進藉由去除之虛設閘極堆疊58留下的凹陷中，以及可以具有在ILD 78上方延伸之部位。根據本揭示案之一些實施方式，閘極介電質80包括作為其下部分之界面層(interfacial layer；IL，未單獨繪示)。IL可以包括諸如氧化矽層之氧化層，其透過化學氧化製程或沉積製程而形成。替換閘極介電質80亦可包括在IL上方形成之高k介電質層。高k介電質層形成為共形層，以及包括諸如氧化鉿、氧化鑭、氧化鋁、氧化鋯等等之高k介電質材料。高k值介電質材料之介電常數(k值)高於約3.9，以及可以高於約7.0。根據本揭示案之一些實施方式，替換閘極介電質80中之高k介電質層使用ALD或CVD形成。
閘電極82在替換閘極介電質80上方形成並填充凹陷之剩餘部位。形成閘電極82可以包括用以沉積複數個導電層之複數個沉積製程，以及執行平坦化步驟以去除在ILD 78上方之導電層的多餘部分。可以使用諸如ALD或CVD之共形沉積方法執行導電層之沉積。
閘電極82可以包括擴散阻障層及在擴散阻障層上方之一個(或更多)功函數層。擴散阻障層可以由氮化鈦(TiN)形成，其可以(或可以不)摻雜有矽以形成TiSiN。功函數層決定閘極之功函數，及包括由不同材料形成之至少一個層或複數個層。根據各別FinFET為N型FinFET還是P型FinFET來選擇功函數層之特定材料。例如，對於裝置區域100中之N型FinFET，功函數層可以包括TaN層及在TaN層上方之鋁鈦(TiAl)層。對於裝置區域200中之P型FinFET，功函數層可以包括TaN層、在TaN層上方之TiN層、及在TiN層上方之TiAl 層。在沉積功函數層之後，形成另一阻障層，其可以為另一TiN層。例如，閘電極82亦可包括填充金屬，其可以由鎢或鈷形成。在形成替換閘極84之後，凹陷替換閘極84，以及介電質硬遮罩86充入凹陷。
第15B圖、第15C圖、第15D圖及第15E圖繪示了在裝置區域100中之N型FinFET的替換閘極的複數個橫剖面圖，其中橫剖面圖從含有在第15A圖中之線B-B之垂直面獲得。由於橫向凹陷介電質條部位124，所得閘極可以形成Ω閘極或四閘極。例如，第15B圖繪示了Ω閘極，其中橫向地凹陷介電質條部位124之頂端部位，以及介電質條部位124之凹陷部位的側壁為大體上垂直的。第15C圖繪示了另一Ω閘極，其中橫向地凹陷介電質條部位124之頂端部位，以及介電質條部位124之凹陷部位的側壁為傾斜的，並且可以為大體上直的。第15D圖繪示了Ω閘極，其中橫向地凹陷整個介電質條部位124，以及介電質條部位124之側壁為大體上垂直的。第15E圖繪示了四閘極，其中完全地去除介電質條部位124(參考第15D圖作為基準)。所得替換閘極84包括接觸鰭片部位127之頂表面、底表面、左邊側壁及右邊側壁的四個部位(因此命名四閘極)。藉由形成Ω閘極或四閘極，改進FinFET之短溝道控制。在第15B圖、第15C圖、第15D圖及第15E圖中，鰭片部位127形成FinFET之溝道區。
根據本揭示案之一些實施方式，介電質條部位124之高度在約5奈米與約15奈米之間的範圍中。介電質條部位124之頸縮部位之高度b(第15B圖及第15C圖)在約3奈米與約15奈米之間的範圍中。介電質條部位124之頸縮部位之橫向 凹陷距離c(第15B圖、第15C圖及第25D圖)在約1奈米與約3奈米之間的範圍中。
第15F圖繪示了在裝置區域200中之P型FinFET的替換閘極84的剖面圖。鰭片部位234形成FinFET之溝道區。
在形成如在第15A圖中繪示之結構之後，蝕刻ILD 78及CESL 76以形成接觸開口。可以使用例如反應離子蝕刻(Reactive Ion Etch；RIE)執行蝕刻。在後續步驟中，如在第16圖中繪示，形成源極/汲極接觸塞88。各別步驟亦經繪示為在第18圖中繪示之流程圖中的步驟324。在形成接觸塞88之前，首先蝕刻暴露於接觸口之CESL 76的部位，從而露出磊晶區域172及磊晶區域272。隨後矽化物區域90在磊晶區域172及磊晶區域272上形成。根據本揭示案之一些實施方式，接觸塞88包括阻障層及在各別阻障層上方之含金屬材料。根據本揭示案之一些實施方式，接觸塞88之形成包括形成毯覆阻障層及在毯覆阻障層上方之含金屬材料，以及執行平坦化以去除毯覆阻障層及含金屬材料之多餘部位。阻障層可以由諸如氮化鈦或氮化鉭之金屬氮化物形成。含金屬材料可以由鎢、鈷、銅等等形成。因此形成N型FinFET 192及P型FinFET 292。
第17A圖繪示了作為N型FinFET之半導體鰭片的寬度的函數(例如，參考第7B圖中之寬度W1及寬度W2)之電子遷移率。線90A繪示了從(110)晶圓(其中鰭片之側壁在(100)平面上)及(100)R45晶圓獲得的兩個結果。根據繪示，當鰭片之寬度小於約3奈米時，電子遷移率很低，以及當寬度高於約3奈米時電子遷移率很高。因此，基於大於約3奈米之鰭片寬度形成的FinFET可以具有良好效能。作為比較，在(110) 晶圓(其中鰭片之頂表面及側壁兩者在(110)平面上)之情況下，如藉由線90B所示，電子遷移率比線90A低得多，以及電子遷移率不增大直到鰭片寬度增加到約6奈米。結果指示在(100)R45及(110)上形成之N型FinFET具有良好效能。
第17B圖繪示了作為P型FinFET之半導體鰭片的寬度的函數(例如，參考第7B圖中之寬度W1及寬度W2)之電洞遷移率。線92A繪示了從晶圓處獲得的結果，此晶圓具有在(100)平面上之頂表面及在(110)平面上之鰭片的側壁。線92B繪示了從晶圓獲得的結果，此晶圓具有在(110)平面上之鰭片的頂表面及側壁表面兩者。線92C繪示了從晶圓獲得的結果，此晶圓具有在(100)平面上之鰭片的頂表面及側壁表面兩者。結果指示線92A具有比線92B及線92C更好的結果。因此，在第17A圖及第17B圖中繪示之結果組合指示在(100)R45或(110)頂表面上之N型FinFET具有好的效能，以及在(100)頂表面上之P型FinFET具有良好的效能。N型FinFET及P型FinFET兩者當根據本揭示案之實施方式形成於混合基板20上時，其效能由此改進。
本揭示案之實施方式具有一些有利的特徵。藉由從混合基板開始形成N型FinFET及P型FinFET，改良N型FinFET及P型FinFET兩者的效能。分隔N型及P型裝置區域之間隔物的去除有利地除去藉由間隔物之破裂導致之缺陷。
根據本揭示案之一些實施方式，方法包括蝕刻混合基板以形成延伸進混合基板之凹陷。混合基板包括具有第一表面取向之第一半導體層，在第一半導體層上方之介電質層，及具有不同於第一表面取向之第二表面取向之第二半導體 層。在蝕刻之後，第一半導體層之頂表面暴露於凹陷。間隔物在凹陷上形成。間隔物接觸介電質層之側壁及第二半導體層之側壁。執行磊晶以從第一半導體層生長磊晶半導體區域。去除間隔物。在實施方式中，在去除間隔物之後，執行第一圖案化步驟，其中第二半導體層、介電質層、及第一半導體層經圖案化以藉由第一圖案化步驟形成第一半導體條。在實施方式中，當執行第一圖案化步驟時，同時執行第二圖案化步驟，其中圖案化磊晶半導體區域及第一半導體層以形成第二半導體條。在實施方式中，在第一圖案化步驟期間，在去除之間隔物正下方之第一半導體層的部位經凹陷以形成從第一半導體層之頂表面向下延伸之凹口，以及第一半導體層之頂表面延伸至凹口之相對側。在實施方式中，方法進一步包括在第一半導體條之相對側上形成隔離區；凹陷隔離區，其中第一半導體條之頂端部位比隔離區之剩餘部位之頂表面突出更高以形成鰭片；以及基於鰭片形成鰭式場效電晶體(FinFET)。在實施方式中，在濕式蝕刻步驟中執行去除間隔物。在實施方式中，在去除間隔物之後，形成縫隙以將磊晶半導體區域與介電質層及第二半導體層之剩餘部位分隔。
根據本揭示案之一些實施方式，方法包括蝕刻混合基板以形成凹陷，其中凹陷穿透上部半導體層及介電質層，其中在介電質層底下之下部半導體層的頂表面暴露於凹陷；在凹陷之側壁上形成垂直間隔物；執行磊晶以從下部半導體層生長磊晶半導體區域；蝕刻垂直間隔物使得磊晶半導體區域與上部半導體層及介電質層分開一縫隙；以及執行圖案化步驟以形成第一條及第二條，其中第一條包含上部半導體層之部位、介 電質層之部位及下部半導體層之部位，以及第二條包含磊晶半導體區域之部位。在實施方式中，方法進一步包括在蝕刻垂直間隔物之後及在圖案化步驟之前，在上部半導體層及磊晶半導體區域上方沉積矽層。在實施方式中，方法進一步包括在第一條及第二條之每個的相對側上形成隔離區；以及凹陷隔離區，其中第一條及第二條之頂端部位比隔離區之剩餘部位之頂表面突出更高以分別地形成第一鰭片及第二鰭片。在實施方式中，方法進一步包括在第一條中蝕刻介電質層之部位以將第一條中之上部半導體層之部位與第一條中之下部半導體層之部位分隔。在實施方式中，方法進一步包括執行磊晶以生長額外半導體材料，其中額外半導體材料包含：從第一條中之上部半導體層的部位生長的第一部位、及從第一條中之下部半導體層的部分生長的第二部位，其中額外半導體材料之第一部位及第二部位具有不同的頂表面取向，並且彼此合併。在實施方式中，圖案化步驟導致在第一條與第二條之間形成的縫隙，其中下部半導體層之頂表面在凹陷之正下方並暴露於凹陷，以及形成凹口以從下部半導體層之頂表面向下延伸進下部半導體層中。在實施方式中，凹口處在蝕刻之垂直間隔物正下方的位置處。
根據本揭示案之一些實施方式，裝置包括具有第一頂表面取向之塊材半導體層；在塊材半導體層上方並連接至塊材半導體層之第一半導體條及第二半導體條，其中第一半導體條及第二半導體條具有不同的頂表面取向；在第一半導體條與第二半導體條之間的隔離區，此隔離區包含從隔離區之底表面向下突出之突出部位，其中底表面在隔離區之突出部位的相 對側上；與第一半導體條重疊之第一源極/汲極區，其中第一源極/汲極區為N型FinFET之部位；以及與第二半導體條重疊之第二源極/汲極區，其中第二源極/汲極區為P型FinFET之部位。在實施方式中，第二源極/汲極區具有第一頂表面取向，以及第一源極/汲極區具有不同於第一頂表面取向的第二頂表面取向。在實施方式中，第一源極/汲極區具有(110)頂表面取向，以及第二源極/汲極區具有(100)頂表面取向。在實施方式中，第一源極/汲極區具有(100)R45頂表面取向，以及第二源極/汲極區具有(100)頂表面取向。在實施方式中，第一源極/汲極區包含：上部及下部，其中上部及下部具有不同的頂表面取向，其中上部與下部之連接高於隔離區之頂表面。在實施方式中，隔離區之突出部位在第一半導體條與第二半導體條之間的中間。
根據本揭示案之一些實施方式，方法包括形成垂直間隔物以將第一半導體區域與第二半導體區域分隔；蝕刻垂直間隔物以在第一半導體區域與第二半導體區域之間形成縫隙；形成分別與第一半導體區域及第二半導體區域重疊之第一遮罩及第二遮罩；以及使用第一遮罩及第二遮罩作為蝕刻遮罩以蝕刻第一半導體區域及第二半導體區域，其中第一半導體區域及第二半導體區域之剩餘部位分別地形成第一條及第二條的部位，其中第一條及第二條藉由凹陷分隔開，以及形成從凹陷向下延伸進底下半導體層中的凹口。在實施方式中，方法進一步包括形成第一半導體區域，此形成第一半導體區域包含：對混合基板執行磊晶，其中混合基板包含第一半導體層、在第一半導體層上方之介電質層、及介電質層上方之第二半導體 層，其中在磊晶中，額外半導體層從第一半導體層生長。在實施方式中，方法進一步包括形成第二半導體區域，此形成第二半導體區域包含：蝕刻半導體層及在半導體層底下之介電質層以形成凹陷；以及從凹陷磊晶生長第二半導體區域。在實施方式中，方法進一步包括基於第一條及第二條分別地形成N型FinFET及P型FinFET。
根據本揭示案之一些實施方式，裝置包括N型FinFET，此N型FinFET包括形成N型FinFET之第一通道的第一半導體材料、及藉由第一半導體材料重疊之第一半導體條；P型FinFET，此P型FinFET包含形成P型FinFET之第二通道的第二半導體材料，其中第一半導體材料及第二半導體材料具有不同的頂表面取向、及藉由第二半導體材料重疊之第二半導體條；及STI區域，此STI區域在第一半導體條與第二半導體條之間並接觸第一半導體條及第二半導體條，其中STI區域包含在第一半導體條及第二半導體條之中間的突出部位，以及突出部位延伸低於STI區域之相對底表面。在實施方式中，第一半導體條及第二半導體條具有與第二半導體材料相同的頂表面取向。在實施方式中，第一半導體條及第二半導體條具有不同於第一半導體材料的頂表面取向。
根據本揭示案之一些實施方式，裝置包括N型FinFET，此N型FinFET包含第一半導體條、與第一半導體條重疊之第一半導體鰭片、及與第一半導體鰭片之部位重疊之第一閘極堆疊；P型FinFET，此P型FinFET包含第二半導體條、與第二半導體條重疊之第二半導體鰭片、及與第一半導體鰭片之部位重疊之第二閘極堆疊；及STI區域，此STI區域在第一半 導體條與第二半導體條之間，其中STI區域包含從STI區域之塊部分向下突出的突出部位，以及在裝置之俯視圖中，突出部位具有平行於第一半導體條及第二半導體條之縱向的縱向。在實施方式中，第一半導體條及第二半導體條具有與第二半導體鰭片相同的頂表面取向，以及第一半導體條及第二半導體條具有不同於第一半導體鰭片的頂表面取向。在實施方式中，突出部位具有在約5奈米與約40奈米之間的高度。
上文概述若干實施方式之特徵，使得熟習此項技術者可更好地理解本揭示案之態樣。熟習此項技術者應瞭解，可輕易使用本揭示案作為設計或修改其他製程及結構的基礎，以便實施本文所介紹之實施方式的相同目的及/或實現相同優勢。熟習此項技術者亦應認識到，此類等效結構並未脫離本揭示案之精神及範疇，且可在不脫離本揭示案之精神及範疇的情況下產生本文的各種變化、替代及更改。

Claims (20)

  1. 一種半導體元件製造方法，包含：蝕刻一混合基板以形成延伸進該混合基板之一凹陷，其中該混合基板包含：一第一半導體層，具有一第一表面取向；一介電質層，在該第一半導體層上方；以及一第二半導體層，具有不同於該第一表面取向之一第二表面取向，其中在該蝕刻之後，該第一半導體層之一頂表面暴露於該凹陷；在該凹陷之一側壁上形成一間隔物，其中該間隔物接觸該介電質層之一側壁及該第二半導體層之一側壁；執行一磊晶步驟以從該第一半導體層生長一磊晶半導體區域；以及去除該間隔物。
  2. 如請求項1所述之半導體元件製造方法，進一步包含：在該間隔物去除之後，執行一第一圖案化步驟，其中該第二半導體層、該介電質層及該第一半導體層係藉由該第一圖案化步驟圖案化以形成一第一半導體條。
  3. 如請求項2所述之半導體元件製造方法，進一步包含： 當該第一圖案化被執行時，同時執行一第二圖案化步驟，其中該磊晶半導體區域以及該第一半導體層被圖案化以形成一第二半導體條。
  4. 如請求項2所述之半導體元件製造方法，其中在該第一圖案化步驟期間，位於被移除的該間隔物正下方的該第一半導體層的一部分被下凹以形成一凹口，該凹口由該第一半導體層的複數個頂部表面往下延伸，且該第一半導體層的該些頂部表面往該凹口的相對側延伸。
  5. 如請求項2所述之半導體元件製造方法，進一步包含：在該第一半導體條之相對側上形成隔離區；下凹該些隔離區，其中該第一半導體條之一頂端部位比該些隔離區之剩餘部位之頂表面突出更高以形成一鰭片；以及基於該鰭片形成一鰭式場效電晶體。
  6. 如請求項1所述之半導體元件製造方法，其中該移除該間隔物係在一濕式蝕刻步驟中執行。
  7. 如請求項1所述之半導體元件製造方法，其中在該移除該間隔物後，一間隔被形成以將該磊晶半導體區分隔自該介電層之一剩餘部位以及該第二半導體層。
  8. 一種半導體元件製造方法，包含：蝕刻一混合基板以形成一凹陷，其中該凹陷穿透一上部半導體層及一介電質層，其中位於該介電質層底下之一下部半導體層之一頂表面暴露於該凹陷；在該凹陷之一側壁上形成一垂直間隔物；執行一磊晶步驟以從該下部半導體層生長一磊晶半導體區域；蝕刻該垂直間隔物使得該磊晶半導體區域藉由一縫隙與該上部半導體層及該介電質層分隔；以及執行一圖案化步驟以形成一第一條及一第二條，其中該第一條包含該上部半導體層之一部位、該介電質層之一部位以及該下部半導體層之一部位，以及該第二條包含該磊晶半導體區域之一部位。
  9. 如請求項8所述之半導體元件製造方法，進一步包含：在該蝕刻該垂直間隔物之後，以及在該圖案化步驟之前，沉積一矽層於該上部半導體層以及該磊晶半導體區域上方。
  10. 如請求項8所述之半導體元件製造方法，進一步包含：在該第一條及該第二條中之每一者之相對側上形成複數個隔離區；以及 下凹該些隔離區，其中該第一條及該第二條之複數個頂端部位突出高於該些隔離區之剩餘部位之頂表面以分別形成一第一鰭片及一第二鰭片。
  11. 如請求項10所述之半導體元件製造方法，進一步包含：蝕刻該介電質層之該部位，以將該上部半導體層於該第一條中之該部位與該下部半導體層於該第一條中之該部位分隔。
  12. 如請求項11所述之半導體元件製造方法，進一步包含執行一磊晶步驟以生長一額外半導體材料，其中該額外半導體材料包含：一第一部位，由該上部半導體層於該第一條中之該部位生長出；以及一第二部位，由該下部半導體層於該第一條中之該部位生長出，其中該額外半導體材料之該第一部位以及該第二部位具有不同之表面取向，且彼此合併。
  13. 如請求項8所述之半導體元件製造方法，其中該圖案化步驟造成一間隙形成於該第一條以及該第二條之間，使得該下部半導體層之一頂表面位於凹陷的正下方且暴露於該凹陷，且一凹口係形成以由該下部半導體層之該頂部表面往下延伸進入該下部半導體層中。
  14. 如請求項13所述之半導體元件製造方法，其中該凹口位於被蝕刻之該垂直間隔物正下方。
  15. 一種半導體元件，包含：一塊材半導體層，具有一第一頂表面取向；一第一半導體條及一第二半導體條，在該塊材半導體層上方並連接至該塊材半導體層，其中該第一半導體條與該第二半導體條具有不同之頂表面取向；一隔離區，在該第一半導體條與該第二半導體條之間，該隔離區包含從該隔離區之底表面向下突出之一突出部分，其中該些底表面在該隔離區之該突出部分之相對側上；一第一源極/汲極區，與該第一半導體條重疊，其中該第一源極/汲極區為一N型鰭式場效電晶體之一部位；以及一第二源極/汲極區，與該第二半導體條重疊，其中該第二源極/汲極區為一P型鰭式場效電晶體之一部位。
  16. 如請求項15所述之半導體元件，其中該第二源極/汲極區域具有該第一頂表面取向，且該第一源極/汲極區域具有與該第一頂部表面取向不同之一第二頂表面取向。
  17. 如請求項16所述之半導體元件，其中該第一源極/汲極區域具有一(110)頂表面取向，且該第二源極/汲極區域具有一(100)頂表面取向。
  18. 如請求項16所述之半導體元件，其中該第一源極/汲極區域具有一(100)R45頂表面取向，且該第二源極/汲極區域具有一(100)頂表面取向。
  19. 如請求項15所述之半導體元件，其中該第一源極/汲極區包含：一上部及一下部，其中該上部及該下部具有不同的頂表面取向，其中該上部與該下部之一連接處比該隔離區之一頂表面更高。
  20. 如請求項15所述之半導體元件，其中該隔離區之該突出部位在該第一半導體條與該第二半導體條之間的中間。
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