CN111463276B - 半导体结构及其形成方法 - Google Patents

半导体结构及其形成方法 Download PDF

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CN111463276B
CN111463276B CN201910053550.2A CN201910053550A CN111463276B CN 111463276 B CN111463276 B CN 111463276B CN 201910053550 A CN201910053550 A CN 201910053550A CN 111463276 B CN111463276 B CN 111463276B
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region
fin structure
opening
side wall
forming
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CN111463276A (zh
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张海洋
纪世良
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Priority to CN202311016517.5A priority Critical patent/CN117038460A/zh
Priority to CN201910053550.2A priority patent/CN111463276B/zh
Priority to CN202311016497.1A priority patent/CN117038459A/zh
Priority to US16/711,548 priority patent/US11329144B2/en
Publication of CN111463276A publication Critical patent/CN111463276A/zh
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Abstract

一种半导体结构及其形成方法，其中方法包括：提供衬底，所述衬底包括第一区，所述第一区衬底表面具有若干相互分立的第一初始鳍部结构，所述衬底上具有横跨所述第一初始鳍部结构的伪栅极结构；在所述衬底表面形成介质层，所述介质层覆盖伪栅极结构的侧壁表面且暴露出所述伪栅极结构的顶部表面；去除所述伪栅极结构，在所述介质层内形成第一开口，所述第一开口暴露出第一初始鳍部结构的部分顶部表面和侧壁表面；对第一开口暴露出的第一初始鳍部结构进行至少一次修剪工艺处理以形成第一鳍部结构，所述第一鳍部结构宽度小于第一初始鳍部结构的宽度。所述方法形成的半导体结构的性能较好。

Description

半导体结构及其形成方法
技术领域
本发明涉及半导体技术领域，尤其涉及一种半导体结构及其形成方法。
背景技术
随着集成电路制造技术的快速发展，促使集成电路中的半导体器件的尺寸不断地缩小，使整个集成电路的运作速度将因此而能有效地提升。但是当元件的尺寸再进一步缩小，传统的平面式的MOS晶体管对沟道电流的控制能力变弱，短沟道效应(short channeleffect，简称SCE)日趋严重。而鳍式场效应晶体管(Fin FET)是一种新兴的多栅器件，其栅极对沟道具有很好的控制能力，在小尺寸领域被广泛使用。
目前，通过形成两种关键尺寸的鳍部可以抑制漏致势垒降低效应(DIBL，DrainInduced Barrier Lowering)。
然而，现有技术形成的具有两种宽度鳍部的半导体结构的性能较差。
发明内容
本发明解决的技术问题是提供一种半导体结构及其形成方法，以提高半导体结构的性能。
为解决上述技术问题，本发明实施例提供一种半导体结构的形成方法，包括：提供衬底，所述衬底包括第一区，所述第一区衬底表面具有若干相互分立的第一初始鳍部结构，所述衬底上具有横跨所述第一初始鳍部结构的伪栅极结构，且所述伪栅极结构位于所述第一初始鳍部结构的部分顶部表面和侧壁表面；在所述衬底表面形成介质层，所述介质层覆盖伪栅极结构的侧壁表面且暴露出所述伪栅极结构的顶部表面；去除所述伪栅极结构，在所述介质层内形成第一开口，所述第一开口暴露出第一初始鳍部结构的部分顶部表面和侧壁表面；对第一开口暴露出的第一初始鳍部结构进行至少一次修剪工艺处理以形成第一鳍部结构，所述第一鳍部结构宽度小于第一初始鳍部结构的宽度。
可选的，所述第一鳍部结构的厚度小于所述第一初始鳍部结构的厚度。
可选的，所述修剪工艺的方法包括：在所述第一区第一开口的侧壁表面形成牺牲层，所述牺牲层覆盖第一区第一开口内的第一初始鳍部结构的部分顶部和侧壁表面；以所述牺牲层以及介质层为掩膜，刻蚀第一区第一开口内的第一初始鳍部结构的部分顶部表面和侧壁表面，形成所述第一鳍部结构。
可选的，刻蚀第一区第一开口内的第一初始鳍部结构的部分顶部表面和侧壁表面的工艺为干法刻蚀工艺；所述刻蚀工艺的参数包括：采用的气体包括HBr、O2、Cl2、CH4、以及CF4，HBr的流量为10标准毫升/分钟～500标准毫升/分钟，O2的流量为0标准毫升/分钟～100标准毫升/分钟，Cl2的流量为0标准毫升/分钟～500标准毫升/分钟，CH4的流量为0标准毫升/分钟～100标准毫升/分钟，CF4的流量为0标准毫升/分钟～100标准毫升/分钟，压强为5毫托～200毫托，源功率为100伏～1500伏，偏置功率为0伏～1000伏，时间为10秒～600秒。
可选的，所述牺牲层的形成方法包括：在所述第一区第一开口的侧壁和底部表面形成牺牲膜，所述牺牲膜还覆盖第一区第一开口内的第一初始鳍部结构顶部表面和侧壁表面；回刻蚀所述牺牲膜，直至暴露出第一区第一开口内的第一初始鳍部结构的顶部表面，形成所述牺牲层。
可选的，所述衬底还包括：与所述第一区相邻的第二区，所述第二区衬底表面具有若干相互分立的第二鳍部结构，所述伪栅极结构还延伸至所述第二区衬底上并横跨所述第二鳍部结构，且所述伪栅极结构位于所述第二鳍部结构的部分顶部表面和侧壁表面；所述介质层还位于第二区衬底上，所述介质层位于所述第二区伪栅极结构的侧壁表面且暴露出第二区伪栅极结构的顶部表面；去除所述伪栅极结构之后，所述第一开口还暴露出所述第二鳍部结构的部分顶部和侧壁表面。
可选的，形成所述第一开口之后，形成第一鳍部结构之前，还包括：在所述第一区第一开口内形成第一掩膜层，所述第一掩膜层位于第二鳍部结构的顶部和侧壁表面；所述第一鳍部结构的形成方法包括：以所述第一掩膜层以及介质层为掩膜，对第一区第一开口内的第一初始鳍部结构顶部和侧壁表面进行至少一次修剪工艺处理，形成所述第一鳍部结构。
可选的，所述修剪工艺的次数为一次；采用一次修剪工艺形成第一鳍部结构的步骤包括：在所述第一区第一开口的侧壁表面形成第一牺牲层，所述第一牺牲层覆盖第一区第一开口内第一初始鳍部结构的部分顶部和侧壁表面；以所述第一掩膜层、第一牺牲层以及介质层为掩膜，刻蚀第一区第一开口内的第一初始鳍部结构的部分顶部表面和侧壁表面，形成所述第一鳍部结构。
可选的，所述修剪工艺的次数为两次；采用两次修剪工艺形成第一鳍部结构的方法包括：第一修剪工艺以及所述第一修剪工艺之后的第二修剪工艺；所述第一修剪工艺的方法包括：在第一区第一开口的侧壁表面形成第一牺牲层；以所述第一掩膜层、第一牺牲层以及介质层为掩膜，刻蚀第二区第一开口内的第一初始鳍部结构的部分顶部表面和侧壁表面，形成初始第一鳍部结构；所述第二修剪工艺的方法包括：在第一区第一开口内的第一牺牲层侧壁表面形成第二牺牲层；以所述第一掩膜层、第一牺牲层、位于第一牺牲层侧壁表面的第二牺牲层以及介质层为掩膜，刻蚀第一区第一开口内的初始第一鳍部结构的部分顶部表面和侧壁表面，形成所述第一鳍部结构。
可选的，还包括：位于所述伪栅极结构两侧侧壁表面的侧墙结构。
可选的，所述第一初始鳍部结构包括沿衬底表面法线方向堆叠的若干层复合初始鳍部层，所述复合初始鳍部层包括第一初始鳍部层以及位于第一初始鳍部层表面的第二初始鳍部层，所述第一初始鳍部层和第二初始鳍部层的材料不同。
可选的，所述第一开口的形成方法包括：去除所述伪栅极结构，在所述介质层内形成初始开口；去除初始开口侧壁暴露出的第一初始鳍部层，形成所述第一开口，所述第一开口暴露出悬空的第二初始鳍部层。
可选的，所述第一鳍部结构的宽度为2纳米～10纳米。
可选的，所述第一鳍部结构的厚度为5纳米～50纳米。
可选的，形成所述第一鳍部结构之后，还包括：去除第二区第一开口内的第一掩膜层，在介质层内形成第二开口；在所述第二开口内形成横跨第一区第一鳍部结构和第二区第二鳍部结构的栅极结构。
相应的，本发明还提供一种半导体结构，包括：衬底，所述衬底包括第一区，所述第一区衬底表面具有第一鳍部结构；位于衬底表面的介质层，所述介质层内具有第一开口，所述第一开口暴露出第一区第一鳍部结构的顶部表面和侧壁表面。
可选的，所述衬底还包括：与所述第一区相邻的第二区，所述第二区衬底表面具有若干相互分立的第二鳍部结构；所述第一开口还暴露出所述第二鳍部结构的顶部表面和侧壁表面。
可选的，所述第一鳍部结构的部分宽度小于第二鳍部结构的宽度；所述第一鳍部结构的部分厚度小于所述第二鳍部结构的厚度。
可选的，第一鳍部结构的宽度为2纳米～10纳米；所述第一鳍部结构的厚度为5纳米～50纳米。
与现有技术相比，本发明实施例的技术方案具有以下有益效果：
本发明技术方案提供的半导体结构的形成方法中，通过去除伪栅极结构，在介质层内形成第一开口；对第一区第一开口暴露出的第一初始鳍部结构顶部和侧壁进行至少一次修剪工艺处理，形成第一鳍部结构，所述第一鳍部结构的宽度小于第一初始鳍部结构的的宽度。由于所述第一鳍部结构被第一开口暴露的部分通过进行所述修剪工艺处理形成的，则所述第一鳍部结构被第一开口暴露的部分宽度小于所述第一鳍部结构未被第一开口暴露的部分宽度，且所述第一鳍部结构被第一开口暴露的部分与所述第一鳍部结构未被第一开口暴露的部分相连，则第一鳍部结构未被第一开口暴露的部分能够支撑所述第一鳍部结构被第一开口暴露的部分，有利于降低第一鳍部结构发生变形，甚至第一鳍部结构出现断裂的可能性，从而使形成的半导体结构的性能较好。
进一步，通过两次以上所述修剪工艺在第一区第一开口内形成的第一鳍部结构的宽度是逐渐减小的，能够大幅降低器件漏电流的产生，从而使形成的半导体结构的性能较好。
进一步，所述衬底还包括：与所述第一区相邻的第二区，所述第二区衬底表面具有若干相互分立的第一初始鳍部结构。由于第二区第二鳍部结构被第一掩膜层掩盖，未经过所述修剪工艺处理，即，第二区第二鳍部结构的宽度未被减小，从而所述半导体结构具有两种不同宽度的第一鳍部结构和第二鳍部结构，具有不同宽度的第一鳍部结构和第二鳍部结构可以满足不同的性能要求，形成性能较好的半导体结构。
附图说明
图1是一种半导体结构的结构示意图；
图2至图16是本发明一实施例中半导体结构形成方法的各步骤的结构示意图。
具体实施方式
正如背景技术所述，半导体结构的性能较差。
以下结合附图进行详细说明，半导体结构的性能较差的原因，图1是一种半导体结构的结构示意图。
请参考图1，衬底100，所述衬底100包括第二区B和第一区A，所述第二区B和第一区A相邻，所述第一区A衬底100表面具有若干相互分立的第一鳍部110，所述第二区B衬底100表面具有若干相互分立的第二鳍部120。
上述半导体结构中，所述第二鳍部120沿垂直于第一鳍部110延伸方向上的尺寸小于第一鳍部110沿垂直于第二鳍部120延伸方向上的尺寸，且第二鳍部120沿平行于衬底100表面法线方向上的尺寸小于第一鳍部110沿平行于衬底100表面法线方向上的尺寸。所述半导体结构具有两种不同宽度的第一鳍部110和第二鳍部120，不同尺寸的第一鳍部110和第二鳍部120可以满足不同的性能要求，形成的半导体结构性能较好。
然而，由于所述第二区B内的第二鳍部120宽度和厚度均较小，较容易发生变形，甚至出现断裂，因此，所述半导体及结构的性能仍较差。
需要说明的是，所述宽度指第二鳍部120沿垂直于第一鳍部110延伸方向上的尺寸；所述厚度指第二鳍部120沿平行于衬底100表面法线方向上的尺寸。
为解决所述技术问题，本发明提供了一种半导体结构的形成方法，包括：对第一开口暴露出的第一初始鳍部结构进行至少一次修剪工艺处理以形成第一鳍部结构，所述第一鳍部结构宽度小于第一初始鳍部结构的宽度。所述方法形成的半导体结构的性能较好。
为使本发明的上述目的、特征和有益效果能够更为明显易懂，下面结合附图对本发明的具体实施例做详细的说明。
图2至图16是本发明一实施例中半导体结构形成方法的各步骤的结构示意图。
请参考图2和图3，图2是图3沿X-X1切线方向上的截面示意图，图3是图2沿Y-Y1切线方向上的截面示意图，提供衬底200，所述衬底200包括第一区A，所述第一区A衬底200表面具有若干相互分立的第一初始鳍部结构210，位于第一区A衬底200表面的伪栅极结构220，所述伪栅极结构220覆盖第一初始鳍部结构210的部分顶部表面和侧壁表面。
在本实施例中，所述衬底200的材料为硅。硅的成本较低，有利于降低半导体器件的制造成本。
在其他实施例中，所述衬底的材料包括锗或者硅锗。
在本实施例中，所述第一区A衬底200表面具有一个所述第一初始鳍部结构210。
在本实施例中，所述第一初始鳍部结构210包括沿衬底200表面法线方向堆叠的若干层复合初始鳍部层(图中未示出)，所述复合初始鳍部层包括第一初始鳍部层211以及位于第一初始鳍部层211表面的第二初始鳍部层212，所述第一初始鳍部层211和第二初始鳍部层212的材料不同。
所述第一初始鳍部层211和第二初始鳍部层212的材料不同，则第一初始鳍部层211和第二初始鳍部层212具有不同的刻蚀选择比，则后续去除部分第一初始鳍部层211时，对第二初始鳍部层212的损伤较少。
在本实施例中，所述衬底200和第二初始鳍部层212的材料为硅，所述第一初始鳍部层211的材料为硅锗。
在其他实施例中，所述第一初始鳍部层的材料包括：碳化硅，所述第二初始鳍部层的材料包括：Ⅲ-Ⅴ族元素、InGaAS或者锗。
在本实施例中，所述伪栅极结构220包括：覆盖第一初始鳍部结构210部分顶部和侧壁表面的伪栅介质层(图中未示出)和位于伪栅介质层表面的伪栅极层(图中未示出)、以及位于伪栅介质层和伪栅极层侧壁的侧墙结构221。
所述侧墙结构221的材料包括：氧化硅、氮化硅、碳氮化硅、碳化硅、氧化铝、氧化铪、氮氧化硅或碳氧化硅。在本实施例中，所述侧墙结构221的材料为氮化硅。
在本实施例中，所述衬底200还包括：与第一区A相邻的第二区B，所述第二区B衬底200表面具有若干相互分立的第二鳍部结构213；所述伪栅极结构220还延伸至所述第二区B衬底200上并横跨所述第二鳍部结构213，且所述伪栅极结构220位于所述第二鳍部结构213的部分顶部表面和侧壁表面。
在本实施例中，所述第二区B衬底200表面具有一个所述第二鳍部结构213。
在本实施例中，所述第二区B形成的半导体器件类型与第一区A形成的半导体器件类型不同。所述第二区B用于形成PMOS晶体体管，所述第二区B衬底200内掺杂有N型离子，例如：砷离子或磷离子。所述第一区A用于形成NMOS晶体管，所述第一区A衬底200内掺杂有P型离子，例如：例如：硼离子或BF2-离子。
在其他实施例中，所述第一区形成的半导体器件类型与第二区形成的半导体器件类型相同。
请参考图4，在所述衬底200表面形成介质层230，所述介质层230覆盖第一初始鳍部结构210的顶部和侧壁、以及伪栅极结构220的侧壁表面，且所述介质层230暴露出所述伪栅极结构220的顶部表面。
所述介质层230还位于第二区B衬底200上，所述介质层230位于所述第二区B伪栅极结构220的侧壁表面且暴露出第二区B伪栅极结构220的顶部表面。
在本实施例中，所述介质层230覆盖第一区A和第二区B伪栅极结构220两侧的侧墙结构221侧壁表面，且暴露出所述第一区A和第二区B伪栅极结构220顶部表面、以及侧墙结构221顶部表面。
所述介质层230的形成方法包括：在衬底200表面形成介质膜(图中未示出)，所述介质膜覆盖第一初始鳍部结构210的顶部和侧壁、以及伪栅极结构220侧壁表面，且所述介质膜顶部表面高于伪栅极结构220顶部表面；平坦化所述介质膜，直至暴露出所述伪栅极结构220顶部表面，形成所述介质层230。
形成所述介质膜的工艺包括：化学气相沉积工艺或者物理气相沉积工艺。
所述介质层230的材料包括：氧化硅、氮化硅、碳氮化硅、碳化硅、氧化铝、氧化铪、氮氧化硅或碳氧化硅。在本实施例中，所述介质层230的材料为氮化硅。
请参考图5和图6，图6是图5沿Z方向上的俯视示意图，图5是图6沿W-W1切线方向上的截面示意图，去除所述伪栅极结构220，在所述介质层230内形成第一开口240，所述第一开口240暴露出第一区A第一初始鳍部结构210的部分顶部表面和侧壁表面。
需要说明的是，图5和图4的视图方向相同。
在本实施例中，所述第一开口240还暴露出第二区B第二鳍部结构213的部分顶部和侧壁表面。
在本实施例中，所述第一开口240的形成方法包括：去除所述伪栅极结构220，在所述介质层230内形成初始第一开口(图中未示出)；去除所述初始第一开口侧壁暴露出的第一初始鳍部层211，形成所述第一开口240，所述第一开口240暴露出悬空的第二初始鳍部层212。
去除所述伪栅极结构220的工艺包括：湿法刻蚀工艺和干法刻蚀工艺中的一种或者两种组合。
去除初始第一开口侧壁暴露出的第一初始鳍部层211的工艺包括：湿法刻蚀工艺和干法刻蚀工艺中的一种或者两种组合。
在本实施例中，去除所述伪栅极结构220仅去除位于第一初始鳍部结构210和第二鳍部结构213部分顶部表面和侧壁表面的伪栅介质层和位于伪栅介质层表面的伪栅极层。所述第一开口240暴露出侧墙结构221的侧壁表面。
请参考图7和图8，图7是图8沿Z方向上的俯视示意图，图8是图沿C-C1切线方向上的截面示意图，形成所述第一开口240之后，在所述第二区B第一开口240内形成第一掩膜层250，所述第一掩膜层250覆盖第二区B第二鳍部结构213的顶部和侧壁表面。
所述第一掩膜层250的形成方法包括：在所述第一开口240内填充满第一掩膜材料形成第一掩膜材料层(图中未示出)，所述第一掩膜材料层顶部表面与介质层230表面齐平；在所述第一掩膜材料层表面形成图形化层(图中未示出)，所述图形化层暴露出第一区A第一掩膜材料层表面；以所述图形化层为掩膜，刻蚀所述第一掩膜材料层，直至暴露出第一区A衬底200表面，在第二区B第一开口240内形成所述第一掩膜层250。
所述第一掩膜材料层的材料包括：有机材料，相应的，所述第一掩膜层250的材料包括：有机材料。
形成所述第一掩膜材料层的工艺包括：旋涂工艺。
刻蚀所述第一掩膜材料层的工艺包括：湿法刻蚀工艺、干法刻蚀工艺和灰化工艺中的一种或者几种。
对第一区第一开口内的第一初始鳍部结构进行至少一次修剪工艺处理，形成第一鳍部结构，所述第一鳍部结构的宽度小于第一初始鳍部结构的宽度。
所述修剪工艺的步骤包括：在所述第一区第一开口的侧壁表面形成牺牲层，所述牺牲层覆盖第一区第一开口内的第一初始鳍部结构的部分顶部和侧壁表面；以所述牺牲层以及介质层为掩膜，刻蚀第一区第一开口内的第一初始鳍部结构的部分顶部表面和侧壁表面，形成所述第一鳍部结构。
由于所述第一鳍部结构被第一开口暴露的部分通过进行所述修剪工艺处理形成的，则所述第一鳍部结构被第一开口暴露的部分宽度小于所述第一鳍部结构未被第一开口暴露的部分宽度，且所述第一鳍部结构被第一开口暴露的部分与所述第一鳍部结构未被第一开口暴露的部分相连，则第一鳍部结构未被第一开口暴露的部分能够支撑所述第一鳍部结构被第一开口暴露的部分，有利于降低第一鳍部结构发生变形，甚至第一鳍部结构出现断裂的可能性，从而使形成的半导体结构的性能较好。
在本实施例中，每次的修剪工艺的步骤包括：在所述第一区第一开口的侧壁表面形成牺牲层，所述牺牲层覆盖第一区第一开口内的第一初始鳍部结构两端顶部表面；以所述第一掩膜层、牺牲层以及介质层为掩膜，刻蚀第一区第一开口内的第一初始鳍部结构的部分顶部表面和侧壁表面，形成所述第一鳍部结构。
在本实施例中，所述修剪工艺的次数为两次采用两次修剪工艺形成第一鳍部结构的方法包括：第一修剪工艺以及所述第一修剪工艺之后的第二修剪工艺；所述第一修剪工艺的方法包括：在第一区第一开口的侧壁表面形成第一牺牲层；以所述第一掩膜层、第一牺牲层以及介质层为掩膜，刻蚀第二区第一开口内的第一初始鳍部结构的部分顶部表面和侧壁表面，形成初始第一鳍部结构；所述第二修剪工艺的方法包括：在第一区第一开口内的第一牺牲层侧壁表面形成第二牺牲层；以所述第一掩膜层、第一牺牲层、位于第一牺牲层侧壁表面的第二牺牲层以及介质层为掩膜，刻蚀第一区第一开口内的初始第一鳍部结构的部分顶部表面和侧壁表面，形成所述第一鳍部结构。具体请结合图9至图16，对所述第一鳍部结构的形成过程进行详细说明，其中，图9至图12为第一修剪工艺，图13至图16为第二修剪工艺。
请参考图9和图10，图9是图10沿Z方向上的俯视示意图，图10是图9沿D-D1切线方向上的截面示意图，在第一区A第一开口240的侧壁表面形成第一牺牲层261。
在本实施例中，所述伪栅极结构220两侧侧壁表面具有侧墙结构221。所述第一牺牲层261的形成方法包括：在所述第一区A第一开口240的侧壁和底部表面形成第一牺牲膜(图中未示出)，所述第一牺牲膜覆盖侧墙结构221侧壁表面，且覆盖第一区A第一开口240内的第一初始鳍部结构210的部分顶部表面和侧壁表面；回刻蚀所述第一牺牲膜，直至暴露出第一区A第一开口240内的第一初始鳍部结构210的顶部表面，形成所述第一牺牲层261。
所述第一牺牲膜的形成工艺包括：化学气相沉积工艺或物理气相沉积工艺或热氧化工艺。
所述第一牺牲膜的材料包括：氧化硅、氮化硅或氮氧化硅。在本实施例中，所述第一牺牲膜的材料为氧化硅，相应的，所述第一牺牲层261的材料为氧化硅。
在本实施例中，所述第一牺牲层的形成工艺为热氧化工艺。所述热氧化工艺有利于在第一开口240内形成所述第一牺牲膜。
在其他实施例中，所述第一牺牲层的形成工艺包括：化学气相沉积工艺和物理气相沉积工艺。
请参考图11和图12，图11是图12沿Z方向上的俯视示意图，图12是图11沿D-D1方向上的截面示意图，以所述第一牺牲层261以及介质层230为掩膜，刻蚀第一区A第一开口240内的第一初始鳍部结构210(图8中所示)的部分顶部表面和侧壁表面，形成初始第一鳍部结构271。
在本实施例中，以所述第一掩膜层250、侧墙结构221、位于侧墙结构221侧壁表面的第一牺牲层261、以及介质层230为掩膜，刻蚀第一区A第一开口240内的第一初始鳍部结构210的部分顶部表面和侧壁表面，形成所述初始第一鳍部结构271。
刻蚀第一区A第一开口240内的第一初始鳍部结构210的部分顶部表面和侧壁表面的工艺包括：湿法刻蚀工艺和干法刻蚀工艺中的一种或者两种组合。
在本实施例中，刻蚀第一区A第一开口240内的第一初始鳍部结构210的部分顶部表面和侧壁表面的工艺为干法刻蚀工艺。具体工艺参数包括：采用的气体包括HBr、O2、Cl2、CH4、以及CF4，HBr的流量为10标准毫升/分钟～500标准毫升/分钟，O2的流量为0标准毫升/分钟～100标准毫升/分钟，Cl2的流量为0标准毫升/分钟～500标准毫升/分钟，CH4的流量为0标准毫升/分钟～100标准毫升/分钟，CF4的流量为0标准毫升/分钟～100标准毫升/分钟，压强为5毫托～200毫托，源功率为100伏～1500伏，偏置功率为0伏～1000伏，时间为10秒～600秒。
请参考图13和图14，图13是图14沿Z方向上的俯视示意图，图14是图13沿E-E1方向上的截面示意图，在第一区A第一开口240内的第一牺牲层261侧壁表面形成第二牺牲层262。
所述第二牺牲层262的形成方法包括：在所述第一牺牲层261侧壁表面形成第二牺牲膜(图中未示出)，所述第二牺牲膜覆盖第一区A第一开口240内的初始第一鳍部结构271两端顶部表面和侧壁表面；回刻蚀所述第二牺牲膜，直至暴露出第一区A第一开口240内的初始第一鳍部结构271的顶部表面，形成所述第二牺牲层262。
所述第二牺牲层262和第一牺牲层261的材料相同或者不同。
在本实施例中，所述第二牺牲层262和第一牺牲层261的材料相同，所述第二牺牲层的材料为氧化硅，有利于后续形成第二开口时同时去除所述第一牺牲层261和第二牺牲层262，从而简化工艺，节约成本。
请参考图15和图16，图15是图16沿Z方向上的俯视示意图，图16是图15沿F-F1方向上的截面示意图，以所述第一牺牲层261、位于第一牺牲层261侧壁表面的第二牺牲层262以及介质层230为掩膜，刻蚀第一区A第一开口240内的初始第一鳍部结构271的部分顶部表面和侧壁表面，形成所述第一鳍部结构272。
在本实施例中，以所述第一掩膜层250、侧墙结构221、位于侧墙结构221侧壁表面的第一牺牲层261、位于第一牺牲层261侧壁表面的第二牺牲层262以及介质层230为掩膜，刻蚀第一区A第一开口内的初始第一鳍部结构271的部分顶部表面和侧壁表面，形成所述第一鳍部结构272。
刻蚀第一区A第一开口240内的初始第一鳍部结构271的部分顶部表面和侧壁表面的工艺包括：湿法刻蚀工艺和干法刻蚀工艺中的一种或者两种组合。
在本实施例中，刻蚀第一区A第一开口240内的初始第一鳍部结构271的部分顶部表面和侧壁表面的工艺和刻蚀第一区A第一开口240内的第一初始鳍部结构210的部分顶部表面和侧壁表面的工艺是相同的，在此不再赘述。
所述第一鳍部结构272的宽度为：2纳米～10纳米。
选择所述第一鳍部结构272宽度范围的意义在于：若所述第一鳍部结构272的宽度小于2纳米，则宽度过小的第一鳍部结构272容易发生断裂，形成的半导体结构性能较差；若所述第一鳍部结构272的宽度大于10纳米，则第一鳍部结构272的宽度减小程度不明显，和第一初始鳍部结构210的宽度差别不大，仍然无法满足用于不同性能需求的目的，形成的半导体结构性能仍较差。
所述第一鳍部结构272的厚度为：5纳米～50纳米。
选择所述第一鳍部结构272厚度范围的意义在于：若所述第一鳍部结构272的厚度小于5纳米，则形成的半导体结构产生的漏电流较大，形成的半导体结构的性能较差；若所述第一鳍部结构272的厚度大于50纳米，则后续在第二开口内形成栅极结构的难度较大，且容易在形成的栅极结构中产生孔洞，导致电阻不稳定，从而半导体结构的阈值电压不稳定，使形成半导体结构的良率较低。
由于所述第一鳍部结构272被第一开口240暴露的部分通过进行所述修剪工艺处理形成的，则所述第一鳍部结构272被第一开口240暴露的部分宽度小于所述第一鳍部结构272未被第一开口240暴露的部分宽度，且所述第一鳍部结构272被第一开口240暴露的部分与所述第一鳍部结构272未被第一开口240暴露的部分相连，则第一鳍部结构272未被第一开口240暴露的部分能够支撑所述第一鳍部结构272被第一开口240暴露的部分，有利于降低第一鳍部结构272发生变形，甚至第一鳍部结构272出现断裂的可能性，从而使形成的半导体结构的性能较好。
在本实施例中，通过两次所述修剪工艺在第一区A第一开口240内形成的第一鳍部结构272的宽度是逐渐减小的，能够大幅降低器件漏电流的产生，从而使形成的半导体结构的性能较好。
在其他实施例中，所述修剪工艺的次数为一次；采用一次修剪工艺形成第一鳍部结构的步骤包括：在所述第一区第一开口的侧壁表面形成第一牺牲层，所述第一牺牲层覆盖第一区第一开口内的第一初始鳍部结构部分顶部表面；以所述第一掩膜层、第一牺牲层以及介质层为掩膜，刻蚀第一区第一开口内的第一初始鳍部结构的部分顶部表面和侧壁表面，形成所述第一鳍部结构。
由于第二区B第二鳍部结构213被第一掩膜层250掩盖，未经过所述修剪工艺处理，即，第二区B第二鳍部结构213的宽度未被减小，从而所述半导体结构具有两种不同宽度的第一鳍部结构272和第二鳍部结构213，具有不同宽度的第一鳍部结构272和第二鳍部结构213可以满足不同的性能要求，形成性能较好的半导体结构。
在本实施例中，形成所述第一鳍部结构272之后，还包括：去除第二区B第一开口240内的第一掩膜层250，在所述介质层230内形成第二开口；形成所述第二开口，在所述第二开口内形成环绕第一区第一鳍部结构272和第二区B第二鳍部结构213的栅极结构。
在本实施例中，所述第二开口的形成方法还包括：去除位于侧墙结构221侧壁表面的第一牺牲层261以及位于第一牺牲层261侧壁表面的第二牺牲层262。
相应的，本发明还提供一种半导体结构，请参考图15，包括：衬底200，所述衬底200包括第一区A，所述第一区A衬底200表面具有第一鳍部结构272；位于衬底200表面的介质层230，所述介质层230内具有第一开口240，所述第一开口240暴露出第一区A第一鳍部结构272的顶部表面和侧壁表面。
以下结合附图进行详细说明。
所述衬底200还包括：第二区B，所述第二区B和第一区A相邻，所述第二区B衬底200表面具有若干相互分立的第二鳍部结构213；所述第一开口240还暴露出第二区B第二鳍部结构213的顶部表面和侧壁表面。
所述第一鳍部结构272的部分宽度小于第二鳍部结构213的宽度；所述第一鳍部结构272的部分厚度小于所述第二鳍部结构213的厚度。
所述第一鳍部结构272的宽度为：2纳米～10纳米。
所述第一鳍部结构272的厚度为：5纳米～50纳米。
所述第二区B内形成的器件类型和第一区A内形成的器件类型相同或者不相同。
在本实施例中，所述第二区B形成的半导体器件类型与第一区A形成的半导体器件类型不同。
虽然本发明披露如上，但本发明并非限定于此。任何本领域技术人员，在不脱离本发明的精神和范围内，均可作各种更动与修改，因此本发明的保护范围应当以权利要求所限定的范围为准。

Claims (11)

1.一种半导体结构的形成方法，其特征在于，包括：
提供衬底，所述衬底包括第一区以及与所述第一区相邻的第二区，所述第一区衬底表面具有若干相互分立的第一初始鳍部结构，所述第二区衬底表面具有若干相互分立的第二鳍部结构，所述衬底上具有横跨所述第一初始鳍部结构的伪栅极结构，且所述伪栅极结构位于所述第一初始鳍部结构的部分顶部表面和侧壁表面，所述伪栅极结构还延伸至所述第二区衬底上并横跨所述第二鳍部结构，且所述伪栅极结构位于所述第二鳍部结构的部分顶部表面和侧壁表面；
在所述衬底表面形成介质层，所述介质层覆盖伪栅极结构的侧壁表面且暴露出所述伪栅极结构的顶部表面；所述介质层还位于第二区衬底上，所述介质层位于所述第二区伪栅极结构的侧壁表面且暴露出第二区伪栅极结构的顶部表面；
去除所述伪栅极结构，在所述介质层内形成第一开口，所述第一开口暴露出第一初始鳍部结构的部分顶部表面和侧壁表面，所述第一开口还暴露出所述第二鳍部结构的部分顶部和侧壁表面；
对第一开口暴露出的第一初始鳍部结构进行至少一次修剪工艺处理以形成第一鳍部结构，所述第一鳍部结构宽度小于第一初始鳍部结构的宽度，所述第一鳍部结构的宽度与所述第二鳍部结构的宽度不同。
2.如权利要求1所述的半导体结构的形成方法，其特征在于，所述第一鳍部结构的厚度小于所述第一初始鳍部结构的厚度。
3.如权利要求1所述的半导体结构的形成方法，其特征在于，所述修剪工艺的方法包括：在所述第一区第一开口的侧壁表面形成牺牲层，所述牺牲层覆盖第一区第一开口内的第一初始鳍部结构的部分顶部和侧壁表面；以所述牺牲层以及介质层为掩膜，刻蚀第一区第一开口内的第一初始鳍部结构的部分顶部表面和侧壁表面，形成所述第一鳍部结构。
4.如权利要求3所述的半导体结构的形成方法，其特征在于，刻蚀第一区第一开口内的第一初始鳍部结构的部分顶部表面和侧壁表面的工艺为干法刻蚀工艺；所述刻蚀工艺的参数包括：采用的气体包括HBr、O2、Cl2、CH4、以及CF4，HBr的流量为10标准毫升/分钟～500标准毫升/分钟，O2的流量为0标准毫升/分钟～100标准毫升/分钟，Cl2的流量为0标准毫升/分钟～500标准毫升/分钟，CH4的流量为0标准毫升/分钟～100标准毫升/分钟，CF4的流量为0标准毫升/分钟～100标准毫升/分钟，压强为5毫托～200毫托，源功率为100伏～1500伏，偏置功率为0伏～1000伏，时间为10秒～600秒。
5.如权利要求3所述的半导体结构的形成方法，其特征在于，所述牺牲层的形成方法包括：在所述第一区第一开口的侧壁和底部表面形成牺牲膜，所述牺牲膜还覆盖第一区第一开口内的第一初始鳍部结构顶部表面和侧壁表面；回刻蚀所述牺牲膜，直至暴露出第一区第一开口内的第一初始鳍部结构的顶部表面，形成所述牺牲层。
6.如权利要求1所述的半导体结构的形成方法，其特征在于，形成所述第一开口之后，形成第一鳍部结构之前，还包括：在所述第一区第一开口内形成第一掩膜层，所述第一掩膜层位于第二鳍部结构的顶部和侧壁表面；所述第一鳍部结构的形成方法包括：以所述第一掩膜层以及介质层为掩膜，对第一区第一开口内的第一初始鳍部结构顶部和侧壁表面进行至少一次修剪工艺处理，形成所述第一鳍部结构。
7.如权利要求6所述的半导体结构的形成方法，其特征在于，所述修剪工艺的次数为一次；采用一次修剪工艺形成第一鳍部结构的步骤包括：在所述第一区第一开口的侧壁表面形成第一牺牲层，所述第一牺牲层覆盖第一区第一开口内第一初始鳍部结构的部分顶部和侧壁表面；以所述第一掩膜层、第一牺牲层以及介质层为掩膜，刻蚀第一区第一开口内的第一初始鳍部结构的部分顶部表面和侧壁表面，形成所述第一鳍部结构。
8.如权利要求6所述的半导体结构的形成方法，其特征在于，所述修剪工艺的次数为两次；采用两次修剪工艺形成第一鳍部结构的方法包括：第一修剪工艺以及所述第一修剪工艺之后的第二修剪工艺；所述第一修剪工艺的方法包括：在第一区第一开口的侧壁表面形成第一牺牲层；以所述第一掩膜层、第一牺牲层以及介质层为掩膜，刻蚀第二区第一开口内的第一初始鳍部结构的部分顶部表面和侧壁表面，形成初始第一鳍部结构；所述第二修剪工艺的方法包括：在第一区第一开口内的第一牺牲层侧壁表面形成第二牺牲层；以所述第一掩膜层、第一牺牲层、位于第一牺牲层侧壁表面的第二牺牲层以及介质层为掩膜，刻蚀第一区第一开口内的初始第一鳍部结构的部分顶部表面和侧壁表面，形成所述第一鳍部结构。
9.如权利要求1所述的半导体结构的形成方法，其特征在于，还包括：位于所述伪栅极结构两侧侧壁表面的侧墙结构。
10.如权利要求1所述的半导体结构的形成方法，其特征在于，所述第一鳍部结构的宽度为2纳米～10纳米。
11.如权利要求1所述的半导体结构的形成方法，其特征在于，所述第一鳍部结构的厚度为5纳米～50纳米。
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