TW201913737A - 具有介電隔離之多鰭高度 - Google Patents

具有介電隔離之多鰭高度 Download PDF

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TW201913737A
TW201913737A TW106138125A TW106138125A TW201913737A TW 201913737 A TW201913737 A TW 201913737A TW 106138125 A TW106138125 A TW 106138125A TW 106138125 A TW106138125 A TW 106138125A TW 201913737 A TW201913737 A TW 201913737A
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layer
fin
fins
epitaxial layer
semiconductor substrate
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TWI660407B (zh
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吳旭昇
亓屹
彭建偉
羅先慶
顧四朋
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美商格芯（美國）集成電路科技有限公司
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Abstract

一種形成有不同鰭高度且與底下半導體基板介電隔離之半導體鰭片的方法。藉由蝕刻設置於基板上面的活性磊晶層可形成該等鰭片。中介犧牲磊晶層可用來模塑活性磊晶層的成長，然後移除它且用隔離介電層回填。該隔離介電層可設置在該等鰭片的底面與基板之間，而且例如可在用來界定該等鰭片的蝕刻製程之後沉積。在基板的不同區域內，有不同高度的介電隔離鰭片可具有實質共面的頂面。

Description

具有介電隔離之多鰭高度
本申請案大體有關於半導體裝置的製造，且更特別的是，有關於形成具有不同鰭高度之電隔離鰭片的FinFET。
例如鰭式場效電晶體(FinFET)的全空乏裝置為致能縮小下一代閘極長度至14奈米及以下的候選者。鰭式場效電晶體(FinFET)為使電晶體通道在半導體基板的表面上隆起而不是使通道位在或略低於該表面的三維架構。用隆起的通道，閘極可纏繞通道的側面，這提供裝置的改良靜電控制。
FinFET的製造通常利用自對準製程以使用選擇性蝕刻技術在基板的表面上產生極薄的鰭片，例如，20奈米寬或更小。然後，沉積接觸各鰭片之多個表面的閘極結構以形成多閘極架構。
使用閘極最先(gate-first)或閘極最後(gate-last)製程可形成該閘極結構。為了避免功能閘極材料暴露於與激活相關的熱預算(thermal budget)，例如取代金 屬閘極(replacement metal gate；RMG)製程的閘極最後製程使用在裝置激活之後被功能閘極取代的犧牲或虛擬閘極，亦即，在鰭片之源極/汲極區的摻雜物植入及相關驅入退火(drive-in anneal)之後。
相較於與基板相連的鰭片，本案申請人已觀察到，介電隔離FinFET有優異的靜電控制而不需要外延的子鰭片穿通終止摻雜(extensive sub-fin punch-through stop doping)。此一隔離結構增加裝置可變性且改善洩露特性。
有不同高度的鰭片可用來在同一個基板上局部界定不同裝置的通道長度。不過，儘管近來的發展，在同一個基板上形成也有不同鰭高度的隔離半導體鰭片仍然是個挑戰。
根據本申請案的具體實施例，提供一種形成具有多鰭高度且介電隔離之多個鰭片的製造方法。
形成此一結構的方法包括：沉積一第一磊晶層於一半導體基板上，以及沉積一第二磊晶層於該第一磊晶層上。形成穿過該第二磊晶層及該第一磊晶層的數個開口，在此該等開口延伸進入該半導體基板。然後，在該等開口內沉積一介電層。
在該介電層的上側壁表面上面形成側壁間隔體層，且使用該側壁間隔體層作為蝕刻遮罩，蝕刻該第二磊晶層以形成各自設置於該介電層之側壁表面上面的複 數個半導體鰭片。藉由從該等鰭片下面移除該第一磊晶層且沉積在該等鰭片下面的隔離層來提供該等鰭片的介電隔離。
又根據數個具體實施例，一種結構包括：設置於一半導體基板之一隆起區上面的一第一鰭片，以及設置於該半導體基板之一下凹區上面的一具有大於該第一鰭片的高度的第二鰭片。在該半導體基板與該第一鰭片及該第二鰭片中之每一者之間設置一隔離層。
100‧‧‧基板或半導體基板
200‧‧‧硬遮罩或硬遮罩層
300‧‧‧矽鍺、矽鍺層、犧牲層、犧牲矽鍺層或犧牲鍺層
310‧‧‧底切區
400‧‧‧矽層、活性磊晶層、矽磊晶層、磊晶矽層或半導體層
420‧‧‧鰭片或半導體鰭片
422‧‧‧通道區
424‧‧‧源極/汲極區
440‧‧‧源極/汲極接面
500‧‧‧覆蓋層
600‧‧‧介電層
700‧‧‧側壁間隔體
800‧‧‧隔離氧化物或隔離氧化物層
910‧‧‧閘極介電質
920‧‧‧閘極導體
930‧‧‧閘極帽蓋
h1、h2‧‧‧高度
閱讀時結合下列附圖可充分明白以下本申請案之特定具體實施例的詳細說明，其中類似的結構用相同的元件符號表示。
第1圖的示意橫截面圖圖示於沉積及圖案化在半導體基板上面之硬遮罩且凹陷蝕刻(recess etch)以形成階狀基板之後在中間製造階段的FinFET結構；第2圖圖示在移除硬遮罩之後的階狀基板；第3圖圖示犧牲磊晶層直接於階狀基板上面的沉積與活性磊晶層直接於犧牲磊晶層上面的沉積；第4圖圖示在平坦化步驟之後的第3圖的結構；第5圖圖示覆蓋層於第4圖的平坦化架構上面的沉積；第6圖圖示延伸穿過覆蓋層及磊晶層之開口的形成與介電層於開口內的沉積； 第7圖圖示移除覆蓋層以暴露介電層的頂部，接著是形成側壁間隔體於暴露的介電層側壁上面；第8圖圖示蝕刻活性及犧牲磊晶層以從活性磊晶層形成有不同高度的半導體鰭片；第9圖圖示從鰭片下面選擇性移除犧牲磊晶層以形成側向錨定鰭片；第10圖圖示沉積及平坦化在鰭片之間及下面的隔離氧化物；第11圖圖示凹陷蝕刻隔離氧化物之後的第10圖的結構；第12圖圖示移除側壁間隔體以暴露有不同高度且透過隔離氧化物與半導體基板分離之半導體鰭片的頂面；第13圖的示意橫截面圖圖示於形成閘極介電質及閘極導體層於有不同高度之隔離鰭片上面後在中間製造階段的FinFET結構；第14圖的橫截面示意圖示具有較短鰭片的FinFET裝置之一部份；以及第15圖的橫截面示意圖示FinFET裝置之一部份，其具有毗鄰有較短鰭片之FinFET裝置的較長鰭片，在此較短及較長鰭片的頂面實質共面。
此時參考本申請案之專利標的之各種具體實施例的更詳細細節，附圖圖示本發明的一些具體實施 例。諸圖用相同的元件符號表示相同或類似的部件。
描述於本文的是一種形成有不同鰭高度之多個半導體鰭片的方法，以及包括此類鰭片的裝置結構。形成該等鰭片可藉由蝕刻設置於半導體基板上面的半導體層，以及可用隔離介電層與基板電氣隔離。例如，在用來界定鰭片的蝕刻製程之後，在鰭片的底面與基板之間可設置該隔離介電層，並可以沉積。
根據某些具體實施例，該多個鰭片各自有實質共面的頂面，同時在底下半導體基板上面設置有不同高度的底面。
第1圖為在初始製造階段之裝置結構的示意橫截面圖，其圖示形成帶圖案的硬遮罩200於半導體基板100上面，且凹陷蝕刻該半導體基板以形成階狀基板。在不同的具體實施例中，台階高度可在5至20奈米之間，亦即5、10、15或20奈米，包括在前述數值中之任一者之間的範圍。
基板100可包括半導體材料，例如矽，例如單晶矽或多晶矽，或含矽材料。含矽材料包括但不限於：單晶矽鍺(SiGe)、多晶矽鍺、摻碳矽(Si：C)、非晶矽、以及由彼等組成的組合及多層。如本文所使用的，用語“單晶”表示晶形固體，其中整個固體的晶格實質連續且固體的邊緣實質完整不間斷且實質無晶界。
不過，基板100不限於含矽材料，因為基板100可包含其他半導體材料，包括鍺(Ge)及化合物半導 體，包括III-V族化合物半導體，例如GaAs、InAs、GaN、GaP、InSb、ZnSe及ZnS，以及II-VI族化合物半導體，例如CdSe、CdS、CdTe、ZnSe、ZnS及ZnTe。
基板100可為塊狀基板或合成基板，例如絕緣體上半導體(semiconductor-on-insulator；SOI)基板，從下到上其包含處理(handle)部、隔離層(例如，埋藏氧化物層)及半導體材料層。在圖示具體實施例中，只圖示此基板的最上面半導體材料層。
基板100可具有本技藝中常用的尺寸且可包含例如半導體晶圓。示範晶圓直徑包括但不限於：50、100、150、200、300及450毫米。總基板厚度可在250微米至1500微米之間，然而在特定具體實施例中，基板厚度在725至775微米的範圍內，其對應至常用於矽CMOS加工的厚度尺寸。例如，半導體基板100可包含(100)定向矽或(111)定向矽。
可用例如微影的圖案化製程界定該階狀基板，例如，包括形成硬遮罩200於基板上面且在硬遮罩200上面形成一層光阻材料(未圖示)。硬遮罩層200可包括例如氮化矽或氮氧化矽的材料，且可用習知沉積製程沉積，例如，CVD或電漿增強式CVD(PECVD)。
該光阻材料可包括正型(positive-tone)光阻組成物，負型(negative-tone)光阻組成物，或混合型(hybrid-tone)光阻組成物。可用例如旋轉塗佈(spin-on coating)的沉積製程形成一層光阻材料。
然後，沉積光阻經受一輻射圖案，且用習知阻劑顯影劑(resist developer)顯影露出的光阻材料。此後，用至少一圖案轉印蝕刻製程，將由帶圖案的光阻材料所提供的圖案轉印到硬遮罩200中，然後轉印到基板100中。
該圖案轉印蝕刻製程通常為異向性蝕刻。在某些具體實施例中，可使用乾蝕刻製程，例如，反應性離子蝕刻(reactive ion etching；RIE)。在其他具體實施例中，可使用濕化學蝕刻劑。又在其他具體實施例中，可使用乾蝕刻與濕蝕刻的組合。如第2圖所示，在蝕刻半導體基板後，可移除硬遮罩200以顯露階狀結構。
請參考第3圖，在半導體基板100上面形成矽鍺300的磊晶層，然後在矽鍺層300上面形成矽400的磊晶層。在不同的具體實施例中，矽鍺層300包含第一磊晶層且矽層400包含第二磊晶層。
用語“磊晶(epitax)”、“磊晶(epitaxial)”及/或“磊晶成長及/或沉積”係指形成半導體材料層於半導體材料的沉積表面上，其中被成長的半導體材料層採取與沉積表面之半導體材料相同的結晶習性。例如，在磊晶沉積製程中，控制由氣體源所提供的化學反應物且設定系統參數，使得沉積原子都落在沉積表面上且經由表面擴散仍然充分活躍以根據沉積表面中之原子的晶向來確定方向。因此，磊晶半導體材料會採取與形成於其上之沉積表面相同的結晶體特性。例如，沉積於(100)晶面上的磊晶半導體材 料會有(100)取向。
在本方法中，直接形成於基板100之頂面上面的矽鍺層300用作分離活性磊晶層400與基板100的間隔體層。應瞭解，矽鍺層300為也用來模塑(template)活性磊晶層400之磊晶沉積的犧牲層。
磊晶層(亦即，犧牲層300與半導體層400)可用減壓分子束磊晶(molecular beam epitaxy；MBE)或化學氣相沉積(chemical vapor deposition；CVD)製程形成，例如，以450-700℃的基板溫度與0.1-700托的成長壓力(亦即，腔壓)。矽源可包括矽烷氣體(SiH4)，以及SiGex磊晶的鍺源可包括鍺烷氣體(GeH4)。氫可用作載體氣體。
根據各種具體實施例，矽鍺(SiGex)層300係磊晶成長於半導體基板100上。在一示範製程期間，矽前驅物(例如，矽烷)與載體氣體(例如，H2及/或N2)及鍺源(例如，GeH4)同時地流入處理室。例如，矽源的流率可在5立方公分/分鐘(sccm)至500立方公分/分鐘之間，鍺源的流率可在0.1立方公分/分鐘至10立方公分/分鐘之間，以及載體氣體的流率可在1,000立方公分/分鐘至60,000立方公分/分鐘之間，然而可使用更小或更大的流率。
應瞭解，矽的其他合適氣體源包括四氯化矽(SiCl4)、二氯矽烷(SiH2Cl2)、三氯矽烷(SiHCl3)，以及其他減氫氯矽烷(hydrogen-reduced chlorosilane,SiHxCl4-x)。代替鍺烷，其他鍺源或前驅物可用來形成磊晶矽鍺層。較高的鍺烷包括有經驗公式GexH(2x+2)的化合物， 例如二鍺烷(Ge2H6)、三鍺烷(Ge3H8)及四鍺烷(Ge4H10)及其他。有機鍺烷包括有經驗公式RyGexH(2x+2-y)的化合物，在此R=甲基、乙基、丙基或丁基，例如甲基鍺烷((CH3)GeH3)、二甲基鍺烷((CH3)2GeH2)、乙基鍺烷((CH3CH2)GeH3)、甲基二鍺烷((CH3)Ge2H5)，二甲基二鍺烷((CH3)2Ge2H4)及六甲基二鍺烷((CH3)6Ge2)。處理室可維持在0.1托至700托的壓力，同時基板100維持在450℃至700℃之間的溫度。進行根據某些具體實施例的製程以形成厚度在5至20奈米之間的初始矽鍺層。矽鍺(SiGex)層300的鍺含量可在25至50原子百分比之間。根據各種具體實施例，矽鍺層300有組成均勻性。
在沉積矽鍺層300後，直接形成磊晶矽層400於矽鍺層300上面。根據一示範方法，在沉積矽層400期間，矽前驅物(例如，矽烷)與載體氣體(例如，H2及/或N2)同時地流入處理室。矽烷的流率可在5立方公分/分鐘至500立方公分/分鐘之間，以及載體氣體的流率可在1,000立方公分/分鐘至60,000立方公分/分鐘之間，然而可使用更小或更大的流率。
用於沉積磊晶矽層400的處理室可維持在0.1托至700托的壓力，同時基板100維持在450℃至700℃之間的溫度。進行根據某些具體實施例的製程以形成厚度在30至80奈米之間的矽層400。
請參考第4圖，CMP製程可用來平坦化矽層400的頂面。該CMP製程可移除磊晶矽層400在基板之 隆起區及基板之下凹區兩者上面的部份。化學機械研磨法(chemical mechanical polishing；CMP)為使用化學反應及機械力來移除材料及平坦化表面的材料移除製程。“平坦化”係指至少運用例如磨擦媒介物之機械力以產生實質二維表面的材料移除製程。
請參考第5圖，沉積覆蓋層500於經平坦化的矽層400上面。覆蓋層500的形成或沉積可能涉及一或更多層形成或沉積技術，例如化學氣相沉積(CVD)、低壓化學氣相沉積(LPCVD)、電漿增強式化學氣相沉積(PECVD)、金屬有機CVD(MOCVD)、原子層沉積(ALD)、以及物理氣相沉積(PVD)技術，例如濺鍍或蒸鍍。應瞭解，除了覆蓋層500以外，前述技術中的一或多個可用來形成界定於本文的其他層及結構。
覆蓋層500可具有10至30奈米的厚度，且可包含對於矽及二氧化矽兩者有蝕刻選擇性的材料。示範覆蓋層材料包括氮化矽與碳化矽。
請參考第6圖，如上述，微影製程用來形成延伸穿過第一磊晶層及第二磊晶層且部份進入階狀半導體基板的開口。在不同的具體實施例中，該等開口包含平行的溝槽且各自可具有在15至30奈米之間的寬度。請再參考第6圖，該等開口用例如原子層沉積填滿介電層600。應瞭解，在磊晶矽層400的頂面上方，介電層600會用作心軸以從磊晶矽層400形成複數個鰭片，在此介電層600的寬度為鰭片至鰭片的間隔。
請參考第7圖，對於磊晶矽層400及介電層600選擇性地移除覆蓋層500而暴露介電層600的頂部。然後，形成側壁間隔體700於介電層600的暴露側壁(垂直面)上面，亦即，在磊晶矽層400上方。側壁間隔體700的形成可藉由毯覆(共形)沉積間隔體材料(例如，使用原子層沉積製程)，接著是有向(異向性)蝕刻，例如反應性離子蝕刻(RIE)，以移除水平面的間隔體材料。在某些具體實施例中，側壁間隔體的厚度為5至20奈米，例如5、10、15或20奈米，包括在前述數值中之任一者之間的範圍。
合適側壁間隔體材料包括氧化物、氮化物及氮氧化物，例如二氧化矽、氮化矽、氮氧化矽和低電介質常數(低k)材料，例如非晶碳、SiOC、SiOCN及SiBCN，以及低k電介質材料。如本文所使用的，低k材料有小於二氧化矽的電介質常數。
示範低k材料包括但不限於：非晶碳、摻氟氧化物或摻碳氧化物。市售低k電介質產品及材料包括道康寧(Dow Corning)的SiLKTM及多孔SiLKTM，應用材料的Black DiamondTM，德州儀器的CoralTM，以及台積電(TSMC)的Black DiamondTM及CoralTM。
在不同的具體實施例中，側壁間隔體700及介電層600由彼此有蝕刻選擇性的材料形成。在特定具體實施例中，介電層600包含二氧化矽且側壁間隔體700包含氮化矽或SiOCN。
如本文所使用的，化合物二氧化矽及氮化 矽有各自以SiO2及Si3N4之名義表示的組合物。用語二氧化矽及氮化矽不僅是指這些化學計量組合物，也指偏離該等化學計量組合物的氧化物及氮化物組合物。
請參考第8圖，使用側壁間隔體700作為蝕刻遮罩，矽磊晶層400的異向性蝕刻暴露矽鍺層300且界定複數個鰭片420。在此製造階段，在移除犧牲層300之前，用介電層600側向支撐且用矽鍺層300從下面支撐鰭片420。
請參考第9圖，可用任何適當蝕刻製程達成犧牲矽鍺層300的移除，例如乾或濕蝕刻。在一實施例中，可使用等向乾蝕刻，例如離子束蝕刻、電漿蝕刻或等向RIE。在另一實施例中，等向濕蝕刻可使用對於經受移除之材料有選擇性的蝕刻溶液。在移除矽鍺層300以形成底切區(undercut region)310後，半導體鰭片420仍然被直接接觸半導體基板100的介電層600側向支撐。
請參考第10圖，隔離氧化物層800沉積於該等鰭片之間及下面，亦即，於先前被犧牲鍺層300填充的空間中，然後加以平坦化。該隔離氧化物可包含例如二氧化矽。在不同的具體實施例中，隔離氧化物800的平坦化暴露側壁間隔體700的頂面。有利的是，犧牲層300的移除及隔離氧化物800的沉積與閘極長度無關，這允許沉積隔離氧化物而不形成空洞。
第11圖圖示在凹陷蝕刻隔離氧化物以顯露鰭片420之後的第10圖的結構。對鰭片420及側壁間隔體 700選擇性地蝕刻隔離氧化物600可包含有向(異向性)蝕刻。
第12圖圖示移除側壁間隔體以暴露有不同高度且用隔離氧化物800與半導體基板100分離的半導體鰭片420之頂面。在圖示具體實施例中，該多個鰭片有實質共面的頂面。亦即，形成於基板隆起區上面之較矮鰭片的頂面與形成於基板下凹區上面之較高鰭片的頂面實質共面。
第13圖的示意橫截面圖圖示在形成閘極介電質910及閘極導體層920後具有高度不同之隔離鰭片420的FinFET結構。如熟諳此藝者所周知，也參考第14圖及第15圖，閘極係形成於半導體鰭片420在源極/汲極區424之間的通道區422上面，在此閘極介電質910直接設置於通道區上面且閘極導體920設置於閘極介電質上面。
在不同的具體實施例中，該閘極包括形成於鰭片之暴露頂面及側壁表面上面的共形閘極介電質910，以及形成於該閘極介電質上面的閘極導體920。
閘極介電質910可包括二氧化矽、氮化矽、氮氧化矽、高k電介質、或其他合適材料。如本文所使用的，高k材料有大於二氧化矽的電介質常數。高k電介質可包括二元或三元化合物，例如氧化鉿(HfO2)。其他示範高k電介質包括但不限於：ZrO2、La2O3、Al2O3、TiO2、SrTiO3、BaTiO3、LaAlO3、Y2O3、HfOxNy、HfSiOxNy、 ZrOxNy、La2OxNy、Al2OxNy、TiOxNy、SrTiOxNy、LaAlOxNy、Y2OxNy、SiOxNy、SiNx、彼等之矽酸鹽、以及彼等之合金。各x值可分別在0.5至3之間變換，以及各y值可分別在0至2之間變換。閘極介電質的厚度可在1奈米至10奈米之間，例如1、2、4、6、8或10奈米，包括在前述數值中之任一者之間的範圍。
閘極導體920可包括導電材料，例如多晶矽、矽鍺、導電金屬，例如鋁(Al)、鎢(W)、銅(Cu)、鈦(Ti)、鉭(Ta)、鎢(W)、鈷(Co)、鉑(Pt)、銀(Ag)、金(Au)、釕(Ru)、銥(Ir)、銠(Rh)及錸(Re)，導電金屬的合金，例如，鋁銅(Al-Cu)，導電金屬的矽化物，例如，矽化鎢及矽化鉑或其他導電金屬化合物，例如TiN、TiC、TiSiN、TiTaN、TaN、TaAlN、TaSiN、TaRuN、WSiN、NiSi、CoSi，以及彼等之組合。閘極導體可包含此類材料的一或更多層，例如，包括功函數金屬層及/或導電內襯及填充金屬(未單獨圖示)的金屬堆疊。在某些具體實施例中，閘極導體920包含直接在閘極介電質910上面的氮化鈦(TiN)層以及在氮化鈦層上面的鎢或鈷填充層。在圖示結構中，各個鰭片420的頂面係實質共面。請再參考第13圖，例如一層氮化矽的閘極帽蓋930可形成於閘極上面。
第14圖的橫截面示意圖示包括有高度h1之鰭片420的FinFET結構之一部份，同時第15圖的橫截面示意圖示有高度h2(h2>h1)之較高鰭片420的FinFET結構之一部份。在數個示範具體實施例中，較矮鰭片可具有 在30至50奈米之間的高度h1，例如30、35、40、45或50奈米，包括在前述數值中之任一者之間的範圍，同時較高鰭片可具有在40至70奈米之間的高度h2，例如40、45、50、55、60、65或70奈米，包括在前述數值中之任一者之間的範圍。
隆起的源極/汲極接面440形成於鰭片420與通道區422側向毗鄰的源極/汲極區424上面。在形成閘極之前，可用離子植入或選擇性磊晶來形成源極/汲極接面440，視需要使用犧牲閘極(未圖示)作為對準遮罩。例如，可在界定於在相鄰犧牲閘極之間之鰭片上面的自對準空腔中用選擇性磊晶來形成源極/汲極接面440。
應瞭解，第14圖及第15圖的橫截面圖與第1圖至第13圖的橫截面圖正交，同時分別圖示可代表形成於同一個半導體基板100上的較矮及較高鰭片。
如本文所使用的，英文單數形式“一(a)”、“一(an)”、及“該(the)”旨在也包括複數形式，除非上下文中另有明確指示。因此，例如，“鰭片”的引用包括有兩個或更多此類“鰭片”的實施例，除非上下文中另有明確指示。
除非另有明文規定，決非旨在提及於本文的任何方法被理解為它的步驟需要按照特定的順序執行。相應地，在方法請求項沒有實際列舉其步驟將會遵循的順序或請求項或說明中沒有另外特別說明該等步驟受限於特定順序時，決非旨在暗示任何特定順序。任一請求項中的任何列舉單一或多個特徵或方面可與任何其他請求項或數 個請求項中的任何其他列舉特徵或方面排列或組合。
應瞭解，當指例如層、區域或基板的元件形成、沉積或設置於另一元件“上”或“上面”時，它可直接在該另一元件上或者也可存在中介元件。相比之下，當指一元件“直接”在另一元件“上”或“上面”時，不存在中介元件。
儘管使用傳統片語“包含(comprising)”可揭示特定具體實施例的各種特徵、元件或步驟，然而應瞭解，替代具體實施例暗示包括可用傳統片語“由...組成(consisting)”或“實質由…組成(consisting essentially of)”描述者。因此，例如，包含二氧化矽之隔離氧化物的隱示替代具體實施例包括隔離氧化物實質由二氧化矽組成的具體實施例與隔離氧化物由二氧化矽組成的具體實施例。
熟諳此藝者明白，本發明可做出各種修改及變體而不脫離本發明的精神及範疇。由於熟諳此藝者可能想到體現本發明精神及主旨的修改、組合、次組合及變體，因此本發明應被視為涵蓋在隨附申請專利範圍及其等效陳述之範疇內的任何事物。

Claims (17)

  1. 一種形成結構之方法，其包含：沉積一第一磊晶層於一半導體基板上；沉積一第二磊晶層於該第一磊晶層上；形成穿過該第二磊晶層及該第一磊晶層的數個開口，其中，該等開口伸入該半導體基板；在該等開口內沉積一介電層；在該介電層的上側壁表面上面形成一側壁間隔體層；使用該側壁間隔體層作為一蝕刻遮罩來蝕刻該第二磊晶層以形成各自設置於該介電層之一側壁表面上面的數個半導體鰭片；從該等鰭片下面移除該第一磊晶層；以及沉積在該等鰭片下面的一隔離層。
  2. 如申請專利範圍第1項所述之方法，其中，該第一磊晶層包含矽鍺且該第二磊晶層包含矽。
  3. 如申請專利範圍第1項所述之方法，更包含在形成該等開口之前，平坦化該第二磊晶層。
  4. 如申請專利範圍第1項所述之方法，更包含在形成該等開口之前，形成一覆蓋層於該第二磊晶層上面。
  5. 如申請專利範圍第4項所述之方法，其中，形成該側壁間隔體層包含移除該覆蓋層以暴露該介電層的該上側壁表面。
  6. 如申請專利範圍第1項所述之方法，其中，該等開口 包含平行的溝槽。
  7. 如申請專利範圍第1項所述之方法，其中，該半導體基板包括一隆起區與毗鄰該隆起區的一下凹區，以及該等鰭片在該隆起區上面有一第一高度且在該下凹區上面有大於該第一高度的一第二高度。
  8. 如申請專利範圍第7項所述之方法，其中，在該隆起區上面的該等鰭片之頂面與在該下凹區上面的該等鰭片之頂面實質共面。
  9. 如申請專利範圍第1項所述之方法，其中，該第一磊晶層有5至20奈米的厚度。
  10. 如申請專利範圍第1項所述之方法，其中，該介電層包含二氧化矽且該側壁間隔體層包含氮化矽。
  11. 一種結構，其包含：第一鰭片，設置於一半導體基板之一隆起區上面；以及第二鰭片，設置於該半導體基板之一下凹區上面的一具有大於該第一鰭片的高度，其中，在該半導體基板與該第一鰭片之間以及在該半導體基板與該第二鰭片之間設置一隔離層。
  12. 如申請專利範圍第11項所述之結構，其中，該第一鰭片的一頂面與該第二鰭片的一頂面實質共面。
  13. 如申請專利範圍第11項所述之結構，其中，該第一鰭片的底面高於該第二鰭片的底面。
  14. 如申請專利範圍第11項所述之結構，其中，該第一鰭 片的高度為30至50奈米且該第二鰭片的高度為40至70奈米。
  15. 如申請專利範圍第11項所述之結構，其中，該隔離層直接接觸該第一鰭片的底面與該第二鰭片的底面。
  16. 如申請專利範圍第11項所述之結構，其中，該隔離層包含二氧化矽。
  17. 如申請專利範圍第11項所述之結構，更包含設置於該第一鰭片及該第二鰭片上面的一閘極介電層，以及設置於該閘極介電層上面的一閘極導體層。
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CN109887845B (zh) * 2017-12-06 2022-03-18 中芯国际集成电路制造(上海)有限公司 半导体器件及其形成方法
US10991584B2 (en) * 2017-12-19 2021-04-27 International Business Machines Corporation Methods and structures for cutting lines or spaces in a tight pitch structure
US11220424B2 (en) * 2018-08-09 2022-01-11 Honeywell International Inc. Methods for increasing aspect ratios in comb structures
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US7560785B2 (en) * 2007-04-27 2009-07-14 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device having multiple fin heights
US8263462B2 (en) * 2008-12-31 2012-09-11 Taiwan Semiconductor Manufacturing Company, Ltd. Dielectric punch-through stoppers for forming FinFETs having dual fin heights
US9257325B2 (en) * 2009-09-18 2016-02-09 GlobalFoundries, Inc. Semiconductor structures and methods for forming isolation between Fin structures of FinFET devices
US8101486B2 (en) 2009-10-07 2012-01-24 Globalfoundries Inc. Methods for forming isolated fin structures on bulk semiconductor material
US8993402B2 (en) * 2012-08-16 2015-03-31 International Business Machines Corporation Method of manufacturing a body-contacted SOI FINFET
US8766363B2 (en) * 2012-11-07 2014-07-01 International Business Machines Corporation Method and structure for forming a localized SOI finFET
US9000522B2 (en) 2013-01-09 2015-04-07 International Business Machines Corporation FinFET with dielectric isolation by silicon-on-nothing and method of fabrication
US9331201B2 (en) * 2013-05-31 2016-05-03 Globalfoundries Inc. Multi-height FinFETs with coplanar topography background
US9006077B2 (en) 2013-08-21 2015-04-14 GlobalFoundries, Inc. Gate length independent silicon-on-nothing (SON) scheme for bulk FinFETs
US9041062B2 (en) 2013-09-19 2015-05-26 International Business Machines Corporation Silicon-on-nothing FinFETs
US9190466B2 (en) * 2013-12-27 2015-11-17 International Business Machines Corporation Independent gate vertical FinFET structure
US9269814B2 (en) 2014-05-14 2016-02-23 Taiwan Semiconductor Manufacturing Co., Ltd. Sacrificial layer fin isolation for fin height and leakage control of bulk finFETs
US9385023B1 (en) * 2015-05-14 2016-07-05 Globalfoundries Inc. Method and structure to make fins with different fin heights and no topography
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