TWI667699B - 具有氣隙間隔件之finfet及其形成方法 - Google Patents
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- TWI667699B TWI667699B TW106122849A TW106122849A TWI667699B TW I667699 B TWI667699 B TW I667699B TW 106122849 A TW106122849 A TW 106122849A TW 106122849 A TW106122849 A TW 106122849A TW I667699 B TWI667699 B TW I667699B
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- dielectric
- layer
- gate structure
- air gap
- isolation
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Classifications
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
- H01L21/845—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28247—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon passivation or protection of the electrode, e.g. using re-oxidation
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/7682—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
- H01L23/53295—Stacked insulating layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
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Abstract
本發明涉及具有氣隙間隔件的FINFET及其形成方法,鰭式場效應電晶體(FinFET)包括位於相鄰的金屬接觸件之間及/或位於金屬接觸件與電晶體柵極之間的氣隙。該氣隙在非共形沉積一隔離介電質的期間並結合一先金屬工藝而形成,以形成該導電結構。
Description
本申請案通常涉及半導體裝置的製造,尤指用於電性隔離的氣隙的形成以及在先進的FinFET節點(例如相鄰的金屬接觸件之間以及金屬接觸件與電晶體柵極之間)內的寄生電容和電感耦合的最小化。
形成接觸金屬化(contact metallization)的傳統方法是使用連續蝕刻以及沉積步驟以首先在一層間介電質中形成接觸通孔。然後用一導電材料填充該接觸通孔。然而,這樣一個工藝(process)的強健性(robustness)和重複性正受到裝置尺寸減小的挑戰,例如,在一7奈米節點的小於50奈米的接觸件至接觸件的間隔處以及小於20奈米的接觸件至柵極(contact-to-gate)的間隔處的圖案化限制可導致高漏電流及短路,其至少部分歸因於相鄰的導電結構之間介電質隔離的不足以及橋接導電體之間的間隙的剩餘導電材料。而一個或多個金屬化材料的一額外的凹槽蝕刻可用於移除表面殘留,這種附加工藝不利於增加工藝的額外製造步驟。
應該認識到需要一種具有成本效益的整合方法以在先進的節點上提供有效的電性隔離。
根據本申請案的各種實施例,揭露了一種於鰭式場效應電晶體的柵極結構周圍形成氣隙(air-gap)的方法。該氣隙可結合於沉積一隔離介電層而形成,並且可以駐留於柵極的頂部及兩側的上方。該氣隙提供有效的金屬間隔離。
具體而言,所公開的方法包括首先形成例如一鎢層的一金屬層於被接觸的一表面上,蝕刻該金屬層以打開隔離孔並定義金屬接觸件,然而用以介電層回填該隔離孔。該介電層的非共形沉積可用於形成氣隙於被接觸的該表面的頂部上方及/或暴露側壁上方。有利的是,先金屬(metal-first)方法不涉及額外的掩膜或蝕刻步驟。
一種形成一半導體裝置的方法包括:形成一柵極結構於一半導體鰭片的一通道區域的上方,該半導體鰭片具有位於該通道區域的相對側上的一源極區域與一漏極區域。形成介電間隔件於該柵極結構的側壁上方以及一介電蓋體於該柵極結構的該頂部上方。形成一導電層於該介電蓋體的上方以及相鄰的介電間隔件之間的該源極區域與漏極區域的上方,以及然後形成通過該導電層的一孔(aperture)以暴露該介電蓋體的一表面。形成一共形或非共形介電層於該孔中。
一種半導體裝置,例如一鰭式場效應電晶 體(FinFET)包括位於一半導體基板上方的一半導體鰭片以及位於該鰭片的一通道區域上方的一柵極結構。源極與漏極區域(source and drain regions)設置於該通道區域的相對兩側上。介電間隔件位於該柵極結構的側壁上方以及一介電蓋體位於該柵極結構頂部的上方。一導電層形成於位於相鄰的介電間隔件之間的該源極區域與該漏極區域的上方。一隔離介電質具有至少部分位於該柵極結構的上方的一氣隙。該隔離介電質可從該柵極與該導電層之間的該側壁間隔件的上方延伸。
100‧‧‧基板或半導體基板
110‧‧‧支撐基板
120‧‧‧隔離層或絕緣體層
150‧‧‧空腔
202‧‧‧鰭片或半導體鰭片
310a‧‧‧凸起有源區域或凸起源極區域
310b‧‧‧凸起有源區域或凸起漏極區域
400‧‧‧柵極結構、柵極堆疊或柵極
410‧‧‧柵極電極層
420‧‧‧金屬柵極導電體
510‧‧‧氮化物間隔件
520‧‧‧氮化物蓋體、覆蓋氮化層或氮化層
850、852、854‧‧‧氣隙
600‧‧‧源極/漏極區域、外延源極/漏極區域或外延層
650‧‧‧犧牲氧化物層
700‧‧‧金屬層
700a、700b、700c‧‧‧金屬接觸件
710‧‧‧矽化物區域或源極/漏極矽化物區域
810‧‧‧掩膜層
820‧‧‧光阻層
830‧‧‧開口
840‧‧‧隔離孔
842‧‧‧延伸隔離孔
900‧‧‧隔離介電層、隔離介電質、介電材料或介電層
d‧‧‧深度
H‧‧‧高度
S‧‧‧間隔
t‧‧‧厚度
W、w1、w2‧‧‧寬度
通過與下述圖式進行結合,以最好地理解下述的本申請的具體實施例的詳細描述,其中,相似的結構用相似的元件符號予以表示。
第1圖為使用一先金屬沉積法而形成的具有溝槽矽化物接觸件的一FinFET柵極結構的一示意圖;第2圖為根據各種實施例所示的於製造的一中間階段的一半導體裝置架構的一透視圖;第3A至3I圖為根據各種實施例所示的靠近一鰭式場效應電晶體形成氣隙的一示例工藝;第4圖顯示了位於電晶體柵極結構的側壁上方的具有一介電質絕緣層的一部分的一FinFET柵極結構;第5圖為根據一實施例顯示FinFET柵極之間的氣隙以及靠近該柵極側壁的溝槽金屬化; 第6圖為根據一實施例顯示一FinFET柵極的頂部上方的該絕緣介電質內部的氣隙的示意圖;第7圖為顯示具有在該柵極側壁上方延伸的該絕緣介電質的一FinFET柵極的該頂部上方的該絕緣介電質內部的氣隙;第8圖為根據各種實施例顯示的位於一FinFET柵極的該頂部的上方以及位於該柵極與該溝槽金屬化之間的該柵極側壁上方的該絕緣介電質內部的氣隙;以及第9圖顯示了位於一FinFET柵極堆疊的該頂部上方以及位於該柵極與該溝槽金屬化之間的該柵極側壁上方的合併的氣隙。
現在將對本申請案的主題的各個實施例更詳細地進行說明,在附圖中說明了其中的一些實施例。同樣的元件符號將在整個圖式中指代相同或相似的部分。應注意的是,該圖示僅為了說明的目的而提供,其並為按照比例予以繪製。
在下面的描述中,所列出的許多具體細節,例如特徵的結構、元件、材料、尺寸、處理步驟以及技術,用於提供針對本申請案的各種實施例進行理解。然而,本領域的技術人員應當瞭解本申請案的各種實施例可在沒有這些具體細節的情況下予以實施。在其他情況下,已知的結構或處理步驟未予以詳細的描述以避免模糊本申 請案。
本申請案的各實施例通常涉及半導體裝置的製造,尤其是鰭式場效應電晶體(FinFET)的製造。典型地裝置包括具有在相鄰的金屬接觸件之間及/或金屬接觸件與電晶體柵極之間的一個或多個氣隙的鰭式場效應電晶體。氣隙可在非共形沉積一隔離介電質結合一先金屬工藝以形成導電結構的期間形成。如本文所使用的術語"氣隙"包括含有空氣或含有其他氣體介電質(例如惰性氣體)的間隙或通孔,以及含有至少一部分真空的間隙。
參考第1圖,根據各種實施例,一半導體裝置包括具有多個電晶體柵極結構400形成於其上的一半導體基板100。該柵極結構400與同樣形成於基板上的多個鰭片(未予圖示)正交排列。
半導體基板100可以為例如矽或含矽材料的一半導體材料,包括一塊體基板。含矽材料包括但不限於單晶矽、多晶矽、單晶矽鍺(SiGe)、或多晶矽鍺、摻雜碳的矽(Si:C)、非晶矽、以及上述各種材料的組合及多層。本文所使用的術語"單晶"表示一晶體固定,其中整個樣品的晶格基本上是連續的,並與基本沒有晶粒邊界(grain boundaries)的樣品的邊緣基本上連續。樣品矽基板包括絕緣體上矽(silicon-on-insulator;SOI)基板、藍寶石上矽(silicon-on-sapphire;SOS)基板等。
基板100不限於含矽材料,基板100可以包含其他半導體材料,包括Ge以及化合物半導體,如GaAs、 InAs以及其他類似的半導體。在所示的實施例中,基板100為一絕緣體上半導體(SOI)基板,其從底部至頂部具有一支撐基板110、一隔離層120、以及一半導體材料層(未予圖示)。
基板100可具有本領域中通常使用的尺寸。基板可以包括一半導體晶圓(wafer)。示例性晶圓直徑包括但不限於50、100、150、200、300及450毫米(mm),包括上述任何數值之間的範圍。總體的基板厚度的範圍可從250微米至1500微米,雖然在具體的實施例中,基板厚度對應於矽CMOS工藝中通常使用的厚度尺寸,在725至775微米的範圍內。該支撐基板110可例如包括(100)取向的矽或(111)取向的矽。
隔離層120可包括一絕緣體上半導體(SOI)基板的埋置氧化物(buried oxide;BOX)層,或一塊矽基板的一氧化層。隔離層120的厚度範圍可從30至300奈米,例如30、50、100、150、200、250或300奈米,包括上述任意數值之間的範圍。隔離層120可例如包括二氧化矽(SiO2)。可替換的,隔離層120可包括氮化矽、氮氧化矽、低K材料,或這些材料的任意適合的組合。
典型地低K材料包括但不限於無定形碳(amorphous carbon),氟摻雜氧化物,碳摻雜氧化物,SiCOH或SiBCN。市售的低K介電質產品和材料包括道康寧(Dow Corning)的SiLKTM以及porous SiLKTM,實用材料公司(Applied Materials)的Black DiamondTM,德克薩斯儀器公司 (Texas Instrument)的CoralTM以及臺灣積體電路製造公司(TSMC)的Black DiamondTM及CoralTM。如本文所述,低K材料具有小於二氧化矽的介電常數的一介電常數。設置於隔離層120上方的是一半導體材料層,其可被圖案化以限定多個鰭片。
設置於隔離層120上方的半導體材料層可以包括與基板100關聯的上述任何半導體材料。形成半導體材料層並可用於形成半導體鰭片的示例性半導體材料包括矽(Si)、鍺(Ge)、矽鍺(SiGe)、第III-V族化合物半導體(如GaAs,GaN,GaP,InAs,InSb,ZnSe與ZnS)、以及第II-VI族化合物半導體(如CdSe,CdS,CdTe,ZnSe,ZnS與ZnTe)。
支撐基板110和絕緣體層120共同作為一基板,其上設置有多個半導體鰭片。在各種實施例中,多個半導體鰭片中的每一個沿著與所示的具有一基本矩形垂直截面形狀的一柵極堆疊400正交的一垂直方向延伸。如本文所述,一"基本矩形形狀"是一種與一矩形形狀不同的一種形狀,這僅僅是由於光刻及其工藝不超過3奈米。該基本矩形垂直橫截面形狀是包括一垂直方向以及一橫向方向的一平面內的一形狀。多個鰭片可以具有相同或基本相同的尺寸,即高度及/或寬度。如本文所述,基本相同尺寸的變化小於10%,例如小於5%、2%或1%。
如本文所述,一"鰭片"指代具有彼此平行的一對垂直側壁的一連續的半導體材料。如本文所述,如果存在一個垂直平面,其表面不超過表面的均方根粗糙度三 倍以上,則該表面使"垂直"的。多個鰭片中的每一個可以包括沿縱向延伸的一單晶半導體材料。如本文所述,一"縱向"是沿一物體無盡延伸的一水準方向。一"橫向"是垂直於該縱向的一水準方向。
各鰭片的該基本矩形垂直的橫截面形狀平行於絕緣體層120的一頂面的一水準介面。如第1圖所示,根據某些實施例,鰭片高度用一虛線表示,該虛線低於外延源極/漏極區域(source/drain regions)600的高度。
形成鰭片的半導體材料可以摻雜、未摻雜、或者包含其中的摻雜和未摻雜區域。半導體鰭片中的各摻雜區域可以具有相同或不同的摻雜濃度及/或導電率。存在的摻雜區域可以通過例如離子植入、氣相摻雜而形成,或通過存在於用於形成鰭片的材料中的摻雜劑而形成。例如,由半導體材料層所定義的鰭片可以包括於形成鰭片之前的一摻雜劑。舉例來說,半導體層及由此形成的鰭片可進行初步且均勻的摻雜,並具有1×1015atoms/cm3(原子/立方釐米)至1×1018atoms/cm3的一摻雜濃度範圍。
如本領域技術人員所悉知,一柵極結構400形成於鰭片的頂面及相對側壁的上方。柵極結構包括一柵極介電質以及一柵極導電體。柵極介電層可通過熱氧化而形成,一般在750至800℃,或者,可以通過沉積一共形介電層而形成。術語"共形層"以及"共形沉積層(conformally deposited layer)"表示一個層,其具有不超過該層的一平均厚度的20%(例如小於5%,10%或20%)的一厚度。根據某 些實施例中,柵極介電層可以包括二氧化矽、氮化矽、氮氧化矽、高K介電質、及/或其他適合材料。
如本文所述,一高K材料具有大於二氧化矽的介電常數的一介電常數。一高K介電質可以包括二元或三元化合物,例如氧化鉿(HfO2)。其他典型地高K介電質包括但不限於ZrO2,La2O3,Al2O3,TiO2,SrTiO3,BaTiO3,LaAlO3,Y2O3,HfOxNy,HfSiOxNy,ZrOxNy,La2OxNy,Al2OxNy,TiOxNy,SrTiOxNy,LaAlOxNy,Y2OxNy,SiOxNy,SiN,及其矽酸鹽,或其合金。x的每個值可以獨立地從0.5到3不等,y的每個值可以獨立地從0到2不等。
柵極介電質可以通過一適當的工藝進行沉積,例如原子層沉積(atomic layer deposition;ALD)、化學氣相沉積(chemical vapor deposition;CVD)、物理氣相沉積(physical vapor deposition;PVD)、熱氧化、紫外臭氧氧化(UV-ozone oxidation)、或其組合。柵極介電質的厚度範圍可從1奈米至10奈米,例如1奈米、2奈米、4奈米、6奈米、8奈米或10奈米,包括上述任意一個數值之間的範圍。於各種實施例中,柵極介電質包括二氧化矽的一薄層(例如0.5奈米)或高K介電材料的一上覆層。
一柵極電極形成於一個(或多個)柵極介電層的上方。該柵極電極可包括一導電材料,例如多晶矽,也可以使用非晶矽、非晶矽與多晶矽的一組合,多晶矽鍺,或任何其他適合的材料。當該柵極電極層為一矽材料時,其可作為一摻雜層(原位摻雜)予以沉積。
此外,在一些實施例中,其可能有利於採用一金屬柵極導電體層,例如Al、W、Cu、Ti、Ta、W、Pt、Ag、Au、Ru、Ir、Rh以及Re,導電材料的合金,例如Al-Cu,一導電材料的矽化物,例如W矽化物、以及Pt矽化物,或其他導電金屬化合物,例如TiN、TiC、TiSiN、TiTaN、TaN、TaAlN、TaSiN、TaRuN、WSiN、NiSi、CoSi及其組合。柵極電極可以包括一個或多個這樣的材料層,例如,包括一共函數金屬層及/或一襯墊層的一金屬堆疊。於各種實施例中,功函數金屬層的厚度為3至5奈米。在圖式中,例如為一鎢層的一金屬柵極導電體420覆蓋統一標識為410的柵極介電質以及功函數金屬層。
柵極電極(例如功函數金屬層)可以是形成於結構的暴露表面上方的一共形層,然後進行選擇性移除以定義所需的幾何形狀。柵極電極可使用一傳統沉積工藝而形成,如ALD、CVD、金屬有機化學氣相沉積(metalorganic chemical vapor deposition;MOCVD)、分子束外延(molecular beam epitaxy;MBE)、PVD、濺射、電鍍、蒸鍍、離子束沉積、電子束沉積、鐳射輔助沉積、或化學溶液沉積。
根據某些實施例,下一步驟是形成一薄的低K介電層於柵極導電體的側壁上以及形成一介電層於柵極堆疊400的頂部的上方。氮化物間隔件510形成於柵極400的側壁上,一氮化物蓋體520形成於柵極400的頂面的上方。於不同的實施例中,氮化物間隔件510包括矽碳氮化合物(silicon carbon nitride;SiCN),且氮化物蓋體520包括氮化矽(例如Si3N4)。非晶氫化矽碳氮化合物膜可由例如矽烷、甲烷和氮氣的氣體混合物通過RF-PECVD予以製備。
一選擇性蝕刻可用於在鄰接鰭片、氮化物間隔件510、以及柵極堆疊400的半導體層(未圖示)內形成空腔150。該空腔形成蝕刻可以是各向同性(isotropic)或各向異性(anisotropic)的蝕刻,其不會完全削低鰭片。在各種實施例中,空腔150通過半導體層(未圖示)完整地延伸至隔離層120。
然後,使用一選擇性外延工藝,使用一半導體材料回填空腔150以形成如第1圖所示的鄰接鰭片的源極與漏極區域600,應當瞭解的是,當一個區域被定義為一源極區域或一漏極區域時,其僅是為了方便源極區域以及漏極區域可以進行互換,正如本領域技術人員所悉知。
術語"外延"、"外延的"及/或"外延生長及/或沉積"指代一半導體材料的一沉積表面上的一半導體材料層的形成,其中,所生長的半導體材料層與沉積表面的半導體材料具有相同的結晶習性。例如,在一外延沉積工藝中,由源氣體提供的化學反應物的控制以及系統參數的設置使得沉積原子落至沉積表面上,並保持通過表面擴散的足夠的流動性,以根據沉積表面的原子的結晶方向進行自我定向。因此,一外延半導體材料與形成於其上的沉積表面具有相同的結晶特性。例如,沉積於一(100)晶體表面的一外延半導體材料將具有一(100)的取向。源極/漏極區域600可以包括矽、矽鍺、或其他適合的半導體材料。
用於形成矽源極(或漏極)區域的一示例性矽外延工藝使用一氣體混合物,其在600至800℃的沉積(如基板)溫度下包括氫氣(H2)和二氯矽烷(SiH2Cl2)。其他用於矽外延的適合的氣源包括四氯化矽(SiCl4)、矽烷(SiH4)、三氯氫矽(SiHCl3)、和其他氫還原氯矽烷(SiHxCl4-x)。
在各種實施例中,該選擇性外延工藝將一外延層直接沉積在空腔150內暴露的隔離層120上。選擇性外延層可使用適於選擇性外延的分子束外延或化學氣相沉積工藝而形成。源極與漏極區域600的厚度範圍可從15至40奈米,例如15、20、25、30、35、或40奈米,包括上述任意數值之間的範圍。
在各種實施例中,源極與漏極區域被摻雜。例如,在外延生長期間可能發生摻雜,即,源極與漏極區域被原位摻雜。正如本領域技術人員所悉知,摻雜改變了一固有半導體在熱平衡中的電子和空穴載流子(hole carrier)濃度。一摻雜層或區域可為p型或n型。一p型摻雜用於製造一PFET,以及一n型摻雜用於製造一NFET。
如本文所述,"p型"是指在一本征半導體中加入雜質,從而產生價電子的不足。對於矽,例如p型摻雜劑,及雜質,包括但不限於硼、鋁、鎵和銦。如本文所述,"n型"指在一本征半導體中加入自由電子的雜質。對於矽,例如n型摻雜劑,即雜質,包括但不限於銻、砷、和磷。摻雜劑可以通過等離子體(plasma)摻雜被引入,或通 過例如原位摻雜,即在用於形成該層的工藝序列期間被引入。
例如,一摻雜區域(如源極及/或漏極區域)可原位摻雜砷或磷以形成一n型區域。源極與漏極區域600內的摻雜濃度範圍可從1×1019atoms/cm3至1×1022atoms/cm3,例如1×1020atoms/cm3至1×1021atoms/cm3。於其他實施例中,一摻雜區域被原位摻雜硼以形成一p型區域。源極與漏極區域內的摻雜濃度範圍可從1×1019atoms/cm3至1×1022atoms/cm3,例如1×1020atoms/cm3至1×1021atoms/cm3。
一可選的推進退火(drive-in annealing)可用於擴散摻雜劑種類並生成一期望的摻雜分佈。於各種實施例中,源極與漏極區域600內的摻雜原子可以使用一後外延退火(例如在600至1400℃的溫度)而擴散到相鄰的鰭片中以生成靠近源極與漏極區域600的鰭片內的一摻雜分佈。鰭片內的摻雜分佈可以是恒定的或可變的。例如,在鰭片內的摻雜濃度可以隨著沿鰭片的一中心軸的一最小摻雜濃度(例如1×1019至1×1022atoms/cm3)以及其相對表面上的一最大摻雜濃度(例如1×1019至1×1022atoms/cm3)而橫向變化。
參考第2圖,根據另一實施例中,一半導體結構包括一基板100,其具有形成於該基板的一隔離層120上的多個鰭片202。於所述的實施例中,外延源極與漏極區域包括形成於位於其相對兩端的鰭片202上方的凸起(raised)有源區域310a,310b,同時一柵極堆疊400形成於定 義源極與漏極區域之間的一通道的鰭片202的上方。
未轉換為一源極區域或一漏極區域的各半導體鰭片202的部分構成一通道區域。通道區域整體上作為一場效應電晶體的一通道。源極區域包括整體上作為場效應電晶體的一源極的凸起源極區域310a。漏極區域包括整體上作為場效應電晶體的一漏極的凸起漏極區域310b。
可以形成與源極、漏極以及柵極形成接觸的電性接觸件。根據各種實施例中,形成接觸件的方法參考第3A至3I圖予以描述。顯示電接觸件的典型結構在第1圖以及第4圖至第9圖中予以顯示,其為垂直於鰭片的橫截面視圖。
參考第3A圖,其為顯示製造具有設置於半導體基板100上方的柵極堆疊400以及設置於鄰接柵極堆疊400的基板的隔離層120上方的外延源極/漏極區域600的一中間階段的一後替換金屬柵極(post-replacement metal gate;RMG)裝置架構的一橫截面圖,包括柵極電極層410以及金屬柵極導電體420的柵極堆疊400在氮化物間隔件510以及一犧牲氧化物層650的頂面下方被凹陷。
如第3B圖所示,一覆蓋氮化層520沉積於第3A圖的結構的上方,即直接位於犧牲氧化物層650以及凹陷的柵極堆疊400的上方。氮化層520使用一化學機械拋光工藝進行平坦化。化學機械拋光(chemical mechanical polishing;CMP)是同時使用化學反應以及機械力兩者以移除材料並平坦化一表面的一材料移除工藝。犧牲氧化物層 650可以作為一平坦化蝕刻停止層,其露出犧牲氧化物層650的一頂面。
如第3C圖所示,犧牲氧化物層650使用一選擇性蝕刻予以移除,露出外延層600的頂面。可用於相對於柵極以及源極/漏極區域選擇性移除犧牲氧化物層650的典型地蝕刻工藝包括一緩衝氧化物(buffered oxide;HF)濕蝕刻或一SiconiTM等離子體刻蝕。位於相鄰的柵極結構之間的間隔(S)的範圍從10奈米至50奈米,例如10、20、30、40或50奈米,包括上述任意數值之間的範圍。
源極/漏極矽化物區域710形成於源極/漏極區域600上。矽化物區域710的形成可以包括一自對準矽化物(自對準多晶矽化物)工藝。矽化物工藝包括一金屬層(未予圖示)的覆蓋沉積,隨後是退火以使金屬層與源極/漏極區域600內的底層矽之間發生一反應。可選的,可以移除金屬層的未反應部分。金屬層可包括鈦、鎳、鈷、氮化鈦等,及它們的組合。例如,金屬層可以包括一鈦層(5奈米)以及一氮化鈦層(10奈米)。在退火期間,鈦金屬與矽反應生成矽化鈦。
參考第3D圖,然後沉積一覆蓋金屬層700於柵極堆疊400的上方,即與氮化物間隔件510以及氮化物蓋體520接觸,以及位於接觸源極/漏極區域600的上方並接觸矽化物區域710。金屬層700可通過蒸發、濺射沉積、或其他已知的物理氣相沉積(PVD)技術予以沉積,然後使用化學機械拋光進行平坦化。
參考第3E圖,一掩膜層810以及光阻層820相繼沉積於金屬層700的上方。掩膜層810可具有10至100奈米的一厚度,並包括例如SiON,SiN或SiO2。光阻層820可包括一正色調光致抗蝕劑組合物、一負色調光致抗蝕劑組合物、或一混合色調光刻抗蝕劑組合物。該層的光阻材料可以通過一沉積工藝(例如旋塗)而形成。
沉積的光阻最後進行一照射圖案化,並使用一傳統抗蝕顯影劑顯影曝光的光阻材料。由圖案化的光阻材料所提供的開口830的圖案隨後利用至少一圖案轉移蝕刻工藝被轉移至底層材料層或材料層中。
圖案轉移蝕刻工藝可以為一各向同性蝕刻或一各向異性蝕刻。在各種實施例中,一乾蝕刻工藝,可以使用例如反應離子蝕刻(reactive ion etching;RIE)。於其他實施例中,可以使用一濕化學蝕刻劑。在其他的實施例中,可以使用乾蝕刻以及濕蝕刻的組合。如第3F圖所示,金屬層700的一基本各向異性的圖案轉移蝕刻止於氮化物間隔件510以及氮化物蓋體520上以定義隔離孔840。圖案化的光阻可在蝕刻工藝期間被消耗,在完成蝕刻金屬層之後予以剝離,或通過灰化予以移除。
根據各種實施例,可使用一氮等離子體處理以形成位於金屬層700的暴露的表面上方(即隔離孔內部)的一薄(例如2至4奈米)的氮化物鈍化層。如第1圖以及第4圖至第9圖所示,然後隔離孔840可至少部分地被填充一共形或非共形隔離介電質900。根據各種實施例,隔離介電質900的共形沉積基本上填充了隔離孔840,而隔離介電質900的非共形沉積將部分填充形成位於其中的一氣隙的隔離孔840。
例如,電性穩定的二氧化矽的共形層可在氧化亞氮的高流量下使用矽烷(SiH4)和氧化亞氮(N2O)源氣體通過化學氣相沉積予以沉積。在圖示中,金屬層700的剩餘部分提供與源極與漏極區域600接觸的接觸結構。雖然沒有說明,但應可理解,金屬層700的其他剩餘部分可提供與柵極的接觸。
於第3E圖及第3F圖所示的實施例中,隔離孔840的寬度(w1)小於或等於柵極堆疊400的寬度(W)。於將一介電材料900共形填充隔離孔840之後的一相應結構如第1圖所示,其中,介電材料900基本填充隔離孔840,並設於柵極堆疊400的上方。一化學機械拋光步驟可相對掩膜層810的一頂面或金屬層700的一頂面而平坦化該介電層900。
根據另一實施例中,如第3G圖至第3I圖所示,隔離孔840的寬度(w2)大於柵極堆疊400的寬度(W)。因此,如第3H圖所示,作為一實施例,金屬層700的一各向異性圖案轉移蝕刻可停止於定義柵極堆疊400上方的隔離孔840的氮化物間隔件510與氮化物蓋體520上。參考第3I圖,各向異性圖案轉移蝕刻也可以選擇性移除相鄰於柵極堆疊400的金屬層700的部分,並使隔離孔840延伸至柵極堆疊400的一頂面下方的一深度(d),其中,假設蝕刻圖案與柵極堆疊對齊,延伸隔離孔842的厚度(t)可以表示為(w2-W)/2。然而,用一隔離介電質900填充該隔離孔840與該延伸(extended)隔離孔842。
於共形填充隔離孔840以及延伸隔離孔842之後的一相應結構如第4圖所示,其中,介電材料900設於柵極堆疊400的上方以及柵極堆疊側壁的一部分的上方,即直接位於柵極與金屬層之間的氮化物間隔件510的上方。應理解的是,延伸隔離孔842自柵極堆疊400的頂面的下方延伸,延伸隔離孔842的深度(d)小於源極/漏極區域600上方的柵極堆疊的高度,使得介電材料900不直接接觸源極/漏極區域600或源極/漏極矽化物區域710。
如第5圖所示,氣隙852可以使用一定向沉積工藝相鄰於柵極堆疊400形成於延伸隔離孔842內,使得介電材料900填充隔離孔840以及僅該延伸隔離孔842的一上部。在各種實施例中,氣隙852的寬度可為1至10奈米。
根據另一實施例,作為設置於柵極400的側面的上方的氣隙的替代品,或除了柵極400的側面的上方的氣隙,氣隙可形成於柵極的頂部的上方。具有設置於柵極堆疊的頂部的上方的隔離介電質900內的一氣隙的示例性裝置結構如第6圖至第9圖所示。
第6圖至第8圖所示的結構類似於第1圖、第4圖及第5圖所示的結構。然而,一非共形介電層沉積位於柵極400的頂部上方以及金屬層700的暴露側壁上方的隔離孔840內,以代替共形沉積介電層900以基本填充隔離孔840。如第6圖所示,例如,非共形工藝將形成位於柵極上方的相鄰金屬接觸件700a,700b,700c之間的一氣隙850。在不同實施例中,對裝置架構進行配置使得金屬接觸件700a,700b,700c位於柵極的一頂面的上方。
根據不同的實施例中,一非共形介電層可包括一等離子增強化學氣相沉積(plasma-enhanced chemical vapor deposited;PECVD)氧化物,其將沉積於氮化物蓋體520的頂面上方以及隔離孔840內的金屬層700的側壁上方。可替換的,一非共形介電層可使用一高密度等離子體(high density plasma;HDP)沉積工藝予以沉積。
參考第7圖及第8圖,氣隙850及852具有一高度H以及一寬度W。氣隙的高度範圍可例如從15至50奈米。氣隙的寬度(W)範圍例如從1至50奈米。在各種實施例中,氣隙852的高度(H)為柵極堆疊的高度的30%至95%。在不同實施例中,氣隙852的寬度(W)是側壁間隔件510至金屬接觸件的距離的30%至100%。
參考第9圖,其顯示了另一實施例,其中,介電層900向形成從柵極的上方延伸至柵極側壁的一互連的氣隙854的隔離孔中部分延伸。這樣一個合併的氣隙854或離散的氣隙850,852提供相鄰的導電元件之間穩定的電性隔離,以減少中間接觸電容從而提高半導體裝置(包括FinFET裝置)的性能。
本申請案的FinFET可以與各種不同的電路結合,例如高性能邏輯、低功耗邏輯或高密度存儲裝置,包括高密度多十億位元(multi-gigabit)DRAM。此外,基於FinFET的裝置可以結合其他元件,例如電容器、電阻器、二極體、記憶單元等。
本申請案提供了一種裝置架構以及製造方法,克服了傳統結構以及方法的許多不足之處。具體而言,該裝置結構是通過一個穩定的方法啟用的,並提供了形成表現出最小信號路徑電容的先進節點的FinFET裝置的能力。
文本描述了與一FinFET裝置有關的涉及形成氣隙的各種實施例,應瞭解的是,先金屬工藝及其相應結構可與其他邏輯平臺(包括平面(二維)電晶體結構)的製造一起使用。
如本文所述,單數形式的"一"、"一個"以及"該"包括複數指代,除非上下文另有明確規定。因此,例如,一"介電層"包括具有兩個或多個這樣的"介電層"的示例,除非上下文另有清楚的指示。
除非另有明確說明,否則本文所闡述的任何方法絕不意味著要求以特定循序執行其步驟。因此,如果一方法申請專利範圍實際上沒有按照其步驟進行說明,或者在申請專利範圍或者說明書中沒有具體說明步驟僅限於一特定順序,則不意味著任何特定的順序。任何一個申請專利範圍中任何列舉的單個或多個特徵或方面可以與任何其他申請專利範圍中的任何其他列列舉的特徵或方便進 行組合或置換。
如本文所述,一元件例如位於一基板或其他層"上"或"上方"或"上方所設置"的一層或區域是指形成該基板或層的一表面的上方、或接觸該基板或層的一表面。例如,當被記載或描述為一層設置於一基板或其他的上方,應該設想在該層與該基板之間可選擇地存在中間結構層。相反,當一元件被稱為"直接位於另一元件上",或"直接位於另一元件的上方"則沒有中間元件的存在。還應瞭解的是,當一元件被稱為"位於另一元件之下"或"另一元件的下方",其可以是直接位於另一元件之下或另一元件的下方,或可能存在中間元件。相仿,當一元件被稱為"直接位於另一元件之下"或"直接位於另一元件的下方",則沒有中間元件的存在。
雖然實施方案的各種特徵、元件、或步驟是通過使用替換短語"包括"予以揭露,應理解的是,其也意味著包括在替換性實施例中,上述各種特徵、元件、或步驟可以通過使用替換短語"主要由"或"組成"予以描述。因此,在例如在替換實施方案中,由二氧化矽和一高K介電質組成的一柵極介電質意味著包括主要由二氧化矽以及一高K介電質所組成的一柵極介電質的實施例,以及由二氧化矽以及一高K介電質所組成的一柵極介電質的實施例。
對於本領域技術人員顯而易見的是,在不脫離所示實施例的精神或範圍的情況下,可以進行各種修改和變化。通過所公開的結合本發明的精神和實質的各具體實施例的組合,子組合和變形,本領域技術人員可以想到,本發明應被解釋為包括在所附申請專利範圍範圍及其等價範圍內的所有內容。
Claims (11)
- 一種形成半導體裝置的方法,包括:形成一柵極結構於一半導體鰭片的一通道區域的上方,其中,一源極區域與一漏極區域位於該通道區域的相對側上;形成介電間隔件於該柵極結構的側壁上方以及一介電蓋體於該柵極結構的一頂部上方;形成一導電層於該介電蓋體的上方以及於相鄰的柵極結構的該介電間隔件之間的該源極區域與該漏極區域的上方;形成通過該導電層至該介電蓋體的一頂面的一隔離孔;以及形成一介電層於該隔離孔內,其中,於該介電層形成期間,一第一氣隙形成於該介電層內,且其中,該隔離孔從該介電間隔件的側壁上方延伸,且形成該介電層包括非共形沉積該介電層於該隔離孔內以及形成該第一氣隙於該柵極結構的該頂部上方的該介電層內以及形成一第二氣隙於該介電間隔件的側壁上方。
- 如申請專利範圍第1項所述的方法,其中,該第一氣隙被該介電層完全包圍。
- 如申請專利範圍第1項所述的方法,其中,形成該介電層包括向該隔離孔中非共形沉積該介電層,並形成該第二氣隙於位於該介電間隔件的側壁上方的該介電層下方中。
- 如申請專利範圍第1項所述的方法,其中,該柵極結構的該頂部上方的該氣隙與該介電間隔件的該側壁上方的該氣隙合併。
- 一種半導體裝置,包括:一半導體鰭片,其位於一半導體基板的上方;一柵極結構,其位於該半導體鰭片的一通道區域的上方;源極區域與漏極區域,其位於該通道區域的相對側上;介電間隔件,其位於該柵極結構的側壁上方,及一介電蓋體,其位於該柵極結構的該頂部上方;一導電層,其位於相鄰的柵極結構的該介電間隔件之間的該源極區域與該漏極區域的上方;以及一隔離介電質,其位於該柵極結構的該頂部的上方且從該介電間隔件的側壁上方延伸,其中,該隔離介電質包括一第一氣隙,其位於該柵極結構的該頂部上方並被該隔離介電質完全包圍,以及一第二氣隙,其位於該介電間隔件的側壁上方。
- 如申請專利範圍第5項所述的半導體裝置,其中,該氣隙的一寬度的範圍為該柵極結構的一寬度的30%至95%。
- 如申請專利範圍第5項所述的半導體裝置,其中,從該介電間隔件的該側壁上方延伸的該隔離介電質不接觸該源極區域與漏極區域。
- 如申請專利範圍第5項所述的半導體裝置,其中,位於該介電間隔件的該側壁上方的該氣隙的高度的範圍為該柵極結構的高度的30%至95%。
- 如申請專利範圍第5項所述的半導體裝置,其中,該導電層的一頂面位於該柵極結構的一頂面的上方。
- 如申請專利範圍第5項所述的半導體裝置,其中,該介電間隔件包括矽碳氮化合物以及該介電蓋體包括氮化矽。
- 如申請專利範圍第5項所述的半導體裝置,其中,該隔離介電質包括二氧化矽。
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Families Citing this family (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9892961B1 (en) * | 2016-08-09 | 2018-02-13 | International Business Machines Corporation | Air gap spacer formation for nano-scale semiconductor devices |
US10074558B1 (en) | 2017-09-28 | 2018-09-11 | Taiwan Semiconductor Manufacturing Co., Ltd. | FinFET structure with controlled air gaps |
US10833165B2 (en) * | 2018-04-30 | 2020-11-10 | International Business Machines Corporation | Asymmetric air spacer gate-controlled device with reduced parasitic capacitance |
US10418285B1 (en) * | 2018-05-30 | 2019-09-17 | Globalfoundries Inc. | Fin field-effect transistor (FinFET) and method of production thereof |
US10580685B2 (en) * | 2018-07-27 | 2020-03-03 | Globalfoundries Inc. | Integrated single diffusion break |
US10510622B1 (en) * | 2018-07-27 | 2019-12-17 | Globalfoundries Inc. | Vertically stacked complementary-FET device with independent gate control |
US11508827B2 (en) | 2018-09-26 | 2022-11-22 | Taiwan Semiconductor Manufacturing Co., Ltd. | Air spacer for a gate structure of a transistor |
US10861746B2 (en) * | 2018-11-30 | 2020-12-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of manufacturing a semiconductor device |
TWI700816B (zh) * | 2019-01-14 | 2020-08-01 | 華邦電子股份有限公司 | 半導體裝置及其製造方法 |
US10903331B2 (en) | 2019-03-25 | 2021-01-26 | International Business Machines Corporation | Positioning air-gap spacers in a transistor for improved control of parasitic capacitance |
US11552169B2 (en) * | 2019-03-27 | 2023-01-10 | Intel Corporation | Source or drain structures with phosphorous and arsenic co-dopants |
US11018140B2 (en) | 2019-04-19 | 2021-05-25 | Winbond Electronics Corp. | Semiconductor device and method for manufacturing the same |
US10957760B2 (en) * | 2019-08-14 | 2021-03-23 | Nanya Technology Corporation | Semiconductor structure having air gap dielectric and method of preparing the same |
US11094794B2 (en) * | 2019-09-27 | 2021-08-17 | Globalfoundries U.S. Inc. | Air spacer structures |
US12009266B2 (en) * | 2019-12-18 | 2024-06-11 | Taiwan Semiconductor Manufacturing Co., Ltd. | Structure for fringing capacitance control |
US11417750B2 (en) * | 2020-01-31 | 2022-08-16 | Taiwan Semiconductor Manufacturing Co., Ltd. | Gate air spacer for fin-like field effect transistor |
US20210249310A1 (en) * | 2020-02-11 | 2021-08-12 | Nanya Technology Corporation | Semiconductor device with porous dielectric structure and method for fabricating the same |
US11563001B2 (en) * | 2020-03-30 | 2023-01-24 | Taiwan Semiconductor Manufacturing Co., Ltd. | Air spacer and capping structures in semiconductor devices |
GB202008892D0 (en) * | 2020-06-11 | 2020-07-29 | Spts Technologies Ltd | Method of deposition |
CN113809044B (zh) * | 2020-06-12 | 2024-06-21 | 联华电子股份有限公司 | 半导体元件 |
US11251074B2 (en) | 2020-07-16 | 2022-02-15 | Nanya Technology Corporation | Integrated circuit structure and method for preparing the same |
US11557510B2 (en) * | 2020-07-30 | 2023-01-17 | Taiwan Semiconductor Manufacturing Co., Ltd. | Spacers for semiconductor devices including backside power rails |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20120037962A1 (en) * | 2010-08-11 | 2012-02-16 | International Business Machines Corporation | Semiconductor structure having a contact-level air gap within the interlayer dielectrics above a semiconductor device and a method of forming the semiconductor structure using a self-assembly approach |
US20150069532A1 (en) * | 2013-09-09 | 2015-03-12 | Global Foundries Inc. | Methods of forming finfet semiconductor devices with self-aligned contact elements using a replacement gate process and the resulting devices |
US20150255556A1 (en) * | 2014-03-05 | 2015-09-10 | International Business Machines Corporation | Semiconductor device with low-k gate cap and self-aligned contact |
US20160035864A1 (en) * | 2014-01-14 | 2016-02-04 | International Business Machines Corporation | Fin end spacer for preventing merger of raised active regions |
US9397008B1 (en) * | 2015-04-21 | 2016-07-19 | United Microelectronics Corp. | Semiconductor device and manufacturing method of conductive structure in semiconductor device |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
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KR102395073B1 (ko) * | 2015-06-04 | 2022-05-10 | 삼성전자주식회사 | 반도체 소자 |
KR102403741B1 (ko) * | 2015-06-16 | 2022-05-30 | 삼성전자주식회사 | 반도체 장치 |
KR102326120B1 (ko) * | 2015-06-29 | 2021-11-15 | 삼성전자주식회사 | 배선 구조물 및 그 형성 방법, 및 상기 배선 구조물을 갖는 반도체 장치 |
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-
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- 2017-07-07 TW TW106122849A patent/TWI667699B/zh active
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Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20120037962A1 (en) * | 2010-08-11 | 2012-02-16 | International Business Machines Corporation | Semiconductor structure having a contact-level air gap within the interlayer dielectrics above a semiconductor device and a method of forming the semiconductor structure using a self-assembly approach |
US20150069532A1 (en) * | 2013-09-09 | 2015-03-12 | Global Foundries Inc. | Methods of forming finfet semiconductor devices with self-aligned contact elements using a replacement gate process and the resulting devices |
US20160035864A1 (en) * | 2014-01-14 | 2016-02-04 | International Business Machines Corporation | Fin end spacer for preventing merger of raised active regions |
US20150255556A1 (en) * | 2014-03-05 | 2015-09-10 | International Business Machines Corporation | Semiconductor device with low-k gate cap and self-aligned contact |
US9397008B1 (en) * | 2015-04-21 | 2016-07-19 | United Microelectronics Corp. | Semiconductor device and manufacturing method of conductive structure in semiconductor device |
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