CN109473478B - 具有介电隔离的多鳍高度 - Google Patents

具有介电隔离的多鳍高度 Download PDF

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CN109473478B
CN109473478B CN201811044898.7A CN201811044898A CN109473478B CN 109473478 B CN109473478 B CN 109473478B CN 201811044898 A CN201811044898 A CN 201811044898A CN 109473478 B CN109473478 B CN 109473478B
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layer
semiconductor
epitaxial layer
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CN109473478A (zh
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吴旭升
亓屹
彭建伟
罗先庆
顾四朋
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GlobalFoundries US Inc
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Abstract

本发明涉及具有介电隔离的多鳍高度，揭示一种形成有不同鳍高度且与底下半导体衬底介电隔离的半导体鳍片的方法。通过蚀刻设置于衬底上面的活性外延层可形成所述鳍片。中介牺牲外延层可用来模塑活性外延层的成长，然后移除它且用隔离介电层回填。该隔离介电层可设置在所述鳍片的底面与衬底之间，而且例如可在用来界定所述鳍片的蚀刻工艺之后沉积。在衬底的不同区域内，有不同高度的介电隔离鳍片可具有实质共面的顶面。

Description

具有介电隔离的多鳍高度
技术领域
本申请案大体涉及半导体装置的制造，且更特别的是，涉及形成具有不同鳍高度的电隔离鳍片的FinFET。
背景技术
例如鳍式场效晶体管(FinFET)的全空乏装置为致能缩小下一代栅极(gate)长度至14纳米及以下的候选者。鳍式场效晶体管(FinFET)为使晶体管通道在半导体衬底的表面上隆起而不是使通道位在或略低于该表面的三维架构。用隆起的信道，栅极可缠绕通道的侧面，这提供装置的改良静电控制。
FinFET的制造通常利用自对准工艺以使用选择性蚀刻技术在衬底的表面上产生极薄的鳍片，例如，20纳米宽或更小。然后，沉积接触各鳍片的多个表面的栅极结构以形成多栅极架构。
使用栅极最先(gate-first)或栅极最后(gate-last)工艺可形成该栅极结构。为了避免功能栅极材料暴露于与激活相关的热预算(thermal budget)，例如取代金属栅极(replacement metal gate；RMG)工艺的栅极最后工艺使用在装置激活之后被功能栅极取代的牺牲或虚拟栅极，亦即，在鳍片的源极/漏极区的掺杂物植入及相关驱入退火(drive-in anneal)之后。
相比于与衬底相连的鳍
片，本案申请人已观察到，介电隔离FinFET有优异的静电控制而不需要外延的子鳍片穿通终止掺杂(extensive sub-fin punch-through stop doping)。此一隔离结构增加装置可变性且改善泄露特性。
有不同高度的鳍片可用来在同一个衬底上局部界定不同装置的信道长度。不过，尽管近来的发展，在同一个衬底上形成也有不同鳍高度的隔离半导体鳍片仍然是个挑战。
发明内容
根据本申请案的具体实施例，提供一种形成具有多鳍高度且介电隔离的多个鳍片的制造方法。
形成此一结构的方法包括：沉积一第一外延层于一半导体衬底上，以及沉积一第二外延层于该第一外延层上。形成穿过该第二外延层及该第一外延层的数个开口，在此所述开口延伸进入该半导体衬底。然后，在所述开口内沉积一介电层。
在该介电层的上侧壁表面上面形成侧壁间隔体层，且使用该侧壁间隔体层作为蚀刻掩模，蚀刻该第二外延层以形成各自设置于该介电层的侧壁表面上面的复数个半导体鳍片。通过从所述鳍片下面移除该第一外延层且沉积在所述鳍片下面的隔离层来提供所述鳍片的介电隔离。
又根据数个具体实施例，一种结构包括：设置于一半导体衬底的一隆起区上面的一第一鳍片，以及设置于该半导体衬底的一下凹区上面的一具有大于该第一鳍片的高度的第二鳍片。在该半导体衬底与该第一鳍片及该第二鳍片中的每一者之间设置一隔离层。
附图说明
阅读时结合下列附图可充分明白以下本申请案的特定具体实施例的详细说明，其中类似的结构用相同的附图标记表示。
图1的示意横截面图图标于沉积及图案化在半导体衬底上面的硬掩模且凹陷蚀刻(recess etch)以形成阶状衬底之后在中间制造阶段的FinFET结构；
图2图示在移除硬掩模之后的阶状衬底；
图3图示牺牲外延层直接于阶状衬底上面的沉积与活性外延层直接于牺牲外延层上面的沉积；
图4图示在平坦化步骤之后的图3的结构；
图5图示覆盖层于图4的平坦化架构上面的沉积；
图6图示延伸穿过覆盖层及外延层的开口的形成与介电层于开口内的沉积；
图7图示移除覆盖层以暴露介电层的顶部，接着是形成侧壁间隔体于暴露的介电层侧壁上面；
图8图示蚀刻活性及牺牲外延层以从活性外延层形成有不同高度的半导体鳍片；
图9图示从鳍片下面选择性移除牺牲外延层以形成侧向锚定鳍片；
图10图示沉积及平坦化在鳍片之间及下面的隔离氧化物；
图11图示凹陷蚀刻隔离氧化物之后的图10的结构；
图12图示移除侧壁间隔体以暴露有不同高度且透过隔离氧化物与半导体衬底分离的半导体鳍片的顶面；
图13的示意横截面图图示于形成栅极介电质与栅极导体层于有不同高度的隔离鳍片上面后在中间制造阶段的FinFET结构；
图14的横截面示意图示具有较短鳍片的FinFET装置的一部分；以及
图15的横截面示意图标FinFET装置的一部分，其具有毗邻有较短鳍片的FinFET装置的较长鳍片，在此较短及较长鳍片的顶面实质共面。
主要附图标记说明
100 衬底或半导体衬底
200 硬掩模或硬掩模层
300 硅锗、硅锗层、牺牲层、牺牲硅锗层或牺牲锗层
310 底切区
400 硅层、活性外延层、硅外延层、外延硅层或半导体层
420 鳍片或半导体鳍片
422 通道区
424 源极/漏极区
440 源极/漏极接面
500 覆盖层
600 介电层
700 侧壁间隔体
800 隔离氧化物或隔离氧化物层
910 栅极介电质
920 栅极导体
930 栅极帽盖
h1、h2 高度。
具体实施方式
此时参考本申请案的专利目标的各种具体实施例的更详细细节，附图图示本发明的一些具体实施例。各附图中用相同的附图标记表示相同或类似的部件。
描述于本文的是一种形成有不同鳍高度的多个半导体鳍片的方法，以及包括此类鳍片的装置结构。形成所述鳍片可通过蚀刻设置于半导体衬底上面的半导体层，以及可用隔离介电层与衬底电气隔离。例如，在用来界定鳍片的蚀刻工艺之后，在鳍片的底面与衬底之间可设置该隔离介电层，并可以沉积。
根据某些具体实施例，该多个鳍片各自有实质共面的顶面，同时在底下半导体衬底上面设置有不同高度的底面。
图1为在初始制造阶段的装置结构的示意横截面图，其图标形成带图案的硬掩模200于半导体衬底100上面，且凹陷蚀刻该半导体衬底以形成阶状衬底。在不同的具体实施例中，台阶高度可在5至20纳米之间，亦即5、10、15或20纳米，包括在前述数值中的任一者之间的范围。
衬底100可包括半导体材料，例如硅，例如单晶硅或多晶硅，或含硅材料。含硅材料包括但不限于：单晶硅锗(SiGe)、多晶硅锗、掺碳硅(Si：C)、非晶硅、以及由这些组成的组合及多层。如本文所使用的，用语“单晶”表示晶形固体，其中整个固体的晶格实质连续且固体的边缘实质完整不间断且实质无晶界。
不过，衬底100不限于含硅材料，因为衬底100可包含其他半导体材料，包括锗(Ge)及化合物半导体，包括III-V族化合物半导体，例如GaAs、InAs、GaN、GaP、InSb、ZnSe及ZnS，以及II-VI族化合物半导体，例如CdSe、CdS、CdTe、ZnSe、ZnS及ZnTe。
衬底100可为块状衬底或合成衬底，例如绝缘体上半导体(semiconductor-on-insulator；SOI)衬底，从下到上其包含处理(handle)部、隔离层(例如，埋藏氧化物层)及半导体材料层。在图标具体实施例中，只图示此衬底的最上面半导体材料层。
衬底100可具有本领域中常用的尺寸且可包含例如半导体晶圆。示范晶圆直径包括但不限于：50、100、150、200、300及450毫米。总衬底厚度可在250微米至1500微米之间，然而在特定具体实施例中，衬底厚度在725微米至775微米的范围内，其对应至常用于硅CMOS加工的厚度尺寸。例如，半导体衬底100可包含(100)定向硅或(111)定向硅。
可用例如光刻的图案化工艺界定该阶状衬底，例如，包括形成硬掩模200于衬底上面且在硬掩模200上面形成一层光阻材料(未图示)。硬掩模层200可包括例如氮化硅或氮氧化硅的材料，且可用习知沉积工艺沉积，例如，CVD或电浆增强式CVD(PECVD)。
该光阻材料可包括正型(positive-tone)光阻组成物，负型(negative-tone)光阻组成物，或混合型(hybrid-tone)光阻组成物。可用例如旋转涂布(spin-on coating)的沉积工艺形成一层光阻材料。
然后，沉积光阻经受一辐射图案，且用习知阻剂显影剂(resist developer)显影露出的光阻材料。此后，用至少一图案转印蚀刻工艺，将由带图案的光阻材料所提供的图案转印到硬掩模200中，然后转印到衬底100中。
该图案转印蚀刻工艺通常为异向性蚀刻。在某些具体实施例中，可使用干蚀刻工艺，例如，反应性离子蚀刻(reactive ion etching；RIE)。在其他具体实施例中，可使用湿化学蚀刻剂。又在其他具体实施例中，可使用干蚀刻与湿蚀刻的组合。如图2所示，在蚀刻半导体衬底后，可移除硬掩模200以显露阶状结构。
请参考图3，在半导体衬底100上面形成硅锗300的外延层，然后在硅锗层300上面形成硅400的外延层。在不同的具体实施例中，硅锗层300包含第一外延层且硅层400包含第二外延层。
用语“外延(epitax)”、“外延(epitaxial)”及/或“外延成长及/或沉积”系指形成半导体材料层于半导体材料的沉积表面上，其中被成长的半导体材料层采取与沉积表面之半导体材料相同的结晶习性。例如，在外延沉积工艺中，控制由气体源所提供的化学反应物且设定系统参数，使得沉积原子都落在沉积表面上且经由表面扩散仍然充分活跃以根据沉积表面中的原子的晶向来确定方向。因此，外延半导体材料会采取与形成于其上的沉积表面相同的结晶体特性。例如，沉积于(100)晶面上的外延半导体材料会有(100)取向。
在本方法中，直接形成于衬底100之顶面上面的硅锗层300用作分离活性外延层400与衬底100的间隔体层。应了解，硅锗层300为也用来模塑(template)活性外延层400之外延沉积的牺牲层。
外延层(亦即，牺牲层300与半导体层400)可用减压分子束外延(molecular beamepitaxy；MBE)或化学气相沉积(chemical vapor deposition；CVD)工艺形成，例如，以450-700℃的衬底温度与0.1-700托的成长压力(亦即，腔压)。硅源可包括硅烷气体(SiH4)，以及SiGex外延的锗源可包括锗烷气体(GeH4)。氢可用作载体气体。
根据各种具体实施例，硅锗(SiGex)层300系外延成长于半导体衬底100上。在一示范工艺期间，硅前驱物(例如，硅烷)与载体气体(例如，H2及/或N2)及锗源(例如，GeH4)同时地流入处理室。例如，硅源的流率可在5立方公分/分钟(sccm)至500立方公分/分钟之间，锗源的流率可在0.1立方公分/分钟至10立方公分/分钟之间，以及载体气体的流率可在1,000立方公分/分钟至60,000立方公分/分钟之间，然而可使用更小或更大的流率。
应了解，硅的其他合适气体源包括四氯化硅(SiCl4)、二氯硅烷(SiH2Cl2)、三氯硅烷(SiHCl3)，以及其他减氢氯硅烷(hydrogen-reduced chlorosilane,SiHxCl4-x)。代替锗烷，其他锗源或前驱物可用来形成外延硅锗层。较高的锗烷包括有经验公式GexH(2x+2)的化合物，例如二锗烷(Ge2H6)、三锗烷(Ge3H8)及四锗烷(Ge4H10)及其他。有机锗烷包括有经验公式RyGexH(2x+2-y)的化合物，在此R＝甲基、乙基、丙基或丁基，例如甲基锗烷((CH3)GeH3)、二甲基锗烷((CH3)2GeH2)、乙基锗烷((CH3CH2)GeH3)、甲基二锗烷((CH3)Ge2H5)，二甲基二锗烷((CH3)2Ge2H4)及六甲基二锗烷((CH3)6Ge2)。处理室可维持在0.1托至700托的压力，同时衬底100维持在450℃至700℃之间的温度。进行根据某些具体实施例的工艺以形成厚度在5至20纳米之间的初始硅锗层。硅锗(SiGex)层300的锗含量可在25至50原子百分比之间。根据各种具体实施例，硅锗层300有组成均匀性。
在沉积硅锗层300后，直接形成外延硅层400于硅锗层300上面。根据一示范方法，在沉积硅层400期间，硅前驱物(例如，硅烷)与载体气体(例如，H2及/或N2)同时地流入处理室。硅烷的流率可在5立方公分/分钟至500立方公分/分钟之间，以及载体气体的流率可在1,000立方公分/分钟至60,000立方公分/分钟之间，然而可使用更小或更大的流率。
用于沉积外延硅层400的处理室可维持在0.1托至700托的压力，同时衬底100维持在450℃至700℃之间的温度。进行根据某些具体实施例的工艺以形成厚度在30至80纳米之间的硅层400。
请参考图4，CMP工艺可用来平坦化硅层400的顶面。该CMP工艺可移除外延硅层400在衬底的隆起区及衬底之下凹区两者上面的部分。化学机械研磨法(chemical mechanicalpolishing；CMP)为使用化学反应及机械力来移除材料及平坦化表面的材料移除工艺。“平坦化”系指至少运用例如磨擦媒介物的机械力以产生实质二维表面的材料移除工艺。
请参考图5，沉积覆盖层500于经平坦化的硅层400上面。覆盖层500的形成或沉积可能涉及一或更多层形成或沉积技术，例如化学气相沉积(CVD)、低压化学气相沉积(LPCVD)、电浆增强式化学气相沉积(PECVD)、金属有机CVD(MOCVD)、原子层沉积(ALD)、以及物理气相沉积(PVD)技术，例如溅镀或蒸镀。应了解，除了覆盖层500以外，前述技术中的一或多个可用来形成界定于本文的其他层及结构。
覆盖层500可具有10至30纳米的厚度，且可包含对于硅及二氧化硅两者有蚀刻选择性的材料。示范覆盖层材料包括氮化硅与碳化硅。
请参考图6，如上述，微影工艺用来形成延伸穿过第一外延层及第二外延层且部分进入阶状半导体衬底的开口。在不同的具体实施例中，所述开口包含平行的沟槽且各自可具有在15至30纳米之间的宽度。请再参考图6，所述开口用例如原子层沉积填满介电层600。应了解，在外延硅层400的顶面上方，介电层600会用作心轴以从外延硅层400形成复数个鳍片，在此介电层600的宽度为鳍片至鳍片的间隔。
请参考图7，对于外延硅层400及介电层600选择性地移除覆盖层500而暴露介电层600的顶部。然后，形成侧壁间隔体700于介电层600的暴露侧壁(垂直面)上面，亦即，在外延硅层400上方。侧壁间隔体700的形成可通过毯覆(共形)沉积间隔体材料(例如，使用原子层沉积工艺)，接着是有向(异向性)蚀刻，例如反应性离子蚀刻(RIE)，以移除水平面的间隔体材料。在某些具体实施例中，侧壁间隔体的厚度为5至20纳米，例如5、10、15或20纳米，包括在前述数值中的任一者之间的范围。
合适侧壁间隔体材料包括氧化物、氮化物及氮氧化物，例如二氧化硅、氮化硅、氮氧化硅和低电介质常数(低k)材料，例如非晶碳、SiOC、SiOCN及SiBCN，以及低k电介质材料。如本文所使用的，低k材料有小于二氧化硅的电介质常数。
示范低k材料包括但不限于：非晶碳、掺氟氧化物或掺碳氧化物。市售低k电介质产品及材料包括道康宁(Dow Corning)的SiLKTM及多孔SiLKTM，应用材料的Black DiamondTM，德州仪器的CoralTM，以及台积电(TSMC)的Black DiamondTM及CoralTM。
在不同的具体实施例中，侧壁间隔体700及介电层600由彼此有蚀刻选择性的材料形成。在特定具体实施例中，介电层600包含二氧化硅且侧壁间隔体700包含氮化硅或SiOCN。
如本文所使用的，化合物二氧化硅及氮化硅有各自以SiO2及Si3N4的名义表示的组合物。用语二氧化硅及氮化硅不仅是指这些化学计量组合物，也指偏离所述化学计量组合物的氧化物及氮化物组合物。
请参考图8，使用侧壁间隔体700作为蚀刻掩模，硅外延层400的异向性蚀刻暴露硅锗层300且界定复数个鳍片420。在此制造阶段，在移除牺牲层300之前，用介电层600侧向支撑且用硅锗层300从下面支撑鳍片420。
请参考图9，可用任何适当蚀刻工艺达成牺牲硅锗层300的移除，例如干或湿蚀刻。在一实施例中，可使用等向干蚀刻，例如离子束蚀刻、电浆蚀刻或等向RIE。在另一实施例中，等向湿蚀刻可使用对于经受移除的材料有选择性的蚀刻溶液。在移除硅锗层300以形成底切区(undercut region)310后，半导体鳍片420仍然被直接接触半导体衬底100的介电层600侧向支撑。
请参考图10，隔离氧化物层800沉积于所述鳍片之间及下面，亦即，于先前被牺牲锗层300填充的空间中，然后加以平坦化。该隔离氧化物可包含例如二氧化硅。在不同的具体实施例中，隔离氧化物800的平坦化暴露侧壁间隔体700的顶面。有利的是，牺牲层300的移除及隔离氧化物800的沉积与栅极长度无关，这允许沉积隔离氧化物而不形成空洞。
图11图示在凹陷蚀刻隔离氧化物以显露鳍片420之后的图10的结构。对鳍片420及侧壁间隔体700选择性地蚀刻隔离氧化物600可包含有向(异向性)蚀刻。
图12图示移除侧壁间隔体以暴露有不同高度且用隔离氧化物800与半导体衬底100分离的半导体鳍片420的顶面。在图示具体实施例中，该多个鳍片有实质共面的顶面。亦即，形成于衬底隆起区上面的较矮鳍片的顶面与形成于衬底下凹区上面的较高鳍片的顶面实质共面。
图13的示意横截面图图示在形成栅极介电质910与栅极导体层920后具有高度不同的隔离鳍片420的FinFET结构。如所属领域技术人员所周知，也参考图14及图15，栅极系形成于半导体鳍片420在源极/漏极区424之间的通道区422上面，在此栅极介电质910直接设置于通道区上面且栅极导体920设置于栅极介电质上面。
在不同的具体实施例中，该栅极包括形成于鳍片的暴露顶面及侧壁表面上面的共形栅极介电质910，以及形成于该栅极介电质上面的栅极导体920。
栅极介电质910可包括二氧化硅、氮化硅、氮氧化硅、高k电介质、或其他合适材料。如本文所使用的，高k材料有大于二氧化硅的电介质常数。高k电介质可包括二元或三元化合物，例如氧化铪(HfO2)。其他示范高k电介质包括但不限于：ZrO2、La2O3、Al2O3、TiO2、SrTiO3、BaTiO3、LaAlO3、Y2O3、HfOxNy、HfSiOxNy、ZrOxNy、La2OxNy、Al2OxNy、TiOxNy、SrTiOxNy、LaAlOxNy、Y2OxNy、SiOxNy、SiNx、这些的硅酸盐、以及这些的合金。各x值可分别在0.5至3之间变换，以及各y值可分别在0至2之间变换。栅极介电质的厚度可在1纳米至10纳米之间，例如1、2、4、6、8或10纳米，包括在前述数值中的任一者之间的范围。
栅极导体920可包括导电材料，例如多晶硅、硅锗、导电金属，例如铝(Al)、钨(W)、铜(Cu)、钛(Ti)、钽(Ta)、钨(W)、钴(Co)、铂(Pt)、银(Ag)、金(Au)、钌(Ru)、铱(Ir)、铑(Rh)及铼(Re)，导电金属的合金，例如，铝铜(Al-Cu)，导电金属的硅化物，例如，硅化钨及硅化铂或其他导电金属化合物，例如TiN、TiC、TiSiN、TiTaN、TaN、TaAlN、TaSiN、TaRuN、WSiN、NiSi、CoSi，以及这些的组合。栅极导体可包含此类材料的一或更多层，例如，包括功函数金属层及/或导电内衬及填充金属(未单独图标)的金属堆栈。在某些具体实施例中，栅极导体920包含直接在栅极介电质910上面的氮化钛(TiN)层以及在氮化钛层上面的钨或钴填充层。在图标结构中，各个鳍片420的顶面系实质共面。请再参考图13，例如一层氮化硅的栅极帽盖930可形成于栅极上面。
图14的横截面示意图示包括有高度h1的鳍片420的FinFET结构的一部分，同时图15的横截面示意图示有高度h2(h2>h1)的较高鳍片420的FinFET结构之一部分。在数个示范具体实施例中，较矮鳍片可具有在30至50纳米之间的高度h1，例如30、35、40、45或50纳米，包括在前述数值中的任一者之间的范围，同时较高鳍片可具有在40至70纳米之间的高度h2，例如40、45、50、55、60、65或70纳米，包括在前述数值中的任一者之间的范围。
隆起的源极/漏极接面440形成于鳍片420与通道区422侧向毗邻的源极/漏极区424上面。在形成栅极之前，可用离子植入或选择性外延来形成源极/漏极接面440，视需要使用牺牲栅极(未图示)作为对准掩模。例如，可在界定于在相邻牺牲栅极之间的鳍片上面的自对准空腔中用选择性外延来形成源极/漏极接面440。
应了解，图14及图15的横截面图与图1至图13的横截面图正交，同时分别图示可代表形成于同一个半导体衬底100上的较矮及较高鳍片。
如本文所使用的，英文单数形式“一(a)”、“一(an)”、及“该(the)”旨在也包括复数形式，除非上下文中另有明确指示。因此，例如，“鳍片”的引用包括有两个或更多此类“鳍片”的实施例，除非上下文中另有明确指示。
除非另有明文规定，决非旨在提及于本文的任何方法被理解为它的步骤需要按照特定的顺序执行。相应地，在方法权利要求没有实际列举其步骤将会遵循的顺序或权利要求或说明中没有另外特别说明所述步骤受限于特定顺序时，决非旨在暗示任何特定顺序。任一权利要求中的任何列举单一或多个特征或方面可与任何其他权利要求项或数个权利要求项中的任何其他列举特征或方面排列或组合。
应了解，当指例如层、区域或衬底的组件形成、沉积或设置于另一组件“上”或“上面”时，它可直接在该另一组件上或者也可存在中介组件。相比之下，当指一组件“直接”在另一组件“上”或“上面”时，不存在中介组件。
尽管使用传统词组“包含(comprising)”可揭示特定具体实施例的各种特征、组件或步骤，然而应了解，替代具体实施例暗示包括可用传统词组“由…组成(consisting)”或“实质由…组成(consisting essentially of)”描述者。因此，例如，包含二氧化硅的隔离氧化物的隐示替代具体实施例包括隔离氧化物实质由二氧化硅组成的具体实施例与隔离氧化物由二氧化硅组成的具体实施例。
所属领域技术人员明白，本发明可做出各种修改及变体而不脱离本发明的精神及范畴。由于所属领域技术人员可能想到体现本发明精神及主旨的修改、组合、次组合及变体，因此本发明应被视为涵盖在随附权利要求书及其等效陈述的范畴内的任何事物。

Claims (14)

1.一种形成半导体结构的方法，其包含：
沉积一第一外延层于一半导体衬底上；
沉积一第二外延层于该第一外延层上；
形成一覆盖层于该第二外延层上面；
形成穿过该覆盖层、该第二外延层及该第一外延层的数个开口，其中，所述开口伸入该半导体衬底；
在所述开口内沉积一介电层；
移除该覆盖层以暴露该介电层的上侧壁表面；
在该介电层的该上侧壁表面上面形成一侧壁间隔体层；
使用该侧壁间隔体层作为一蚀刻掩模来蚀刻该第二外延层以形成各自设置于该介电层的一侧壁表面上面的数个半导体鳍片；
从所述半导体鳍片下面移除该第一外延层；以及
沉积在所述半导体鳍片下面的一隔离层。
2.如权利要求1所述的方法，其特征在于，该第一外延层包含硅锗且该第二外延层包含硅。
3.如权利要求1所述的方法，进一步包含在形成所述开口之前，平坦化该第二外延层。
4.如权利要求1所述的方法，其特征在于，所述开口包含平行的沟槽。
5.如权利要求1所述的方法，其特征在于，该半导体衬底包括一隆起区与毗邻该隆起区的一下凹区，以及所述半导体鳍片在该隆起区上面有一第一高度且在该下凹区上面有大于该第一高度的一第二高度。
6.如权利要求5所述的方法，其特征在于，在该隆起区上面的所述半导体鳍片的顶面与在该下凹区上面的所述半导体鳍片的顶面实质共面。
7.如权利要求1所述的方法，其特征在于，该第一外延层有5至20纳米的厚度。
8.如权利要求1所述的方法，其特征在于，该介电层包含二氧化硅且该侧壁间隔体层包含氮化硅。
9.一种半导体结构，其包含：
第一鳍片，设置于一半导体衬底的一隆起区上面；
第二鳍片，设置于该半导体衬底的一下凹区上面的一具有大于该第一鳍片的高度，其中，在该半导体衬底与该第一鳍片之间以及在该半导体衬底与该第二鳍片之间设置一隔离层；
设置于该第一鳍片及该第二鳍片上面的一栅极介电层；以及
设置于该栅极介电层上面的一栅极导体层，其中，位于该第一鳍片的相对两侧的该栅极导体层的两个底面均低于该第一鳍片的底面。
10.如权利要求9所述的半导体结构，其特征在于，该第一鳍片的一顶面与该第二鳍片的一顶面实质共面。
11.如权利要求9所述的半导体结构，其特征在于，该第一鳍片的该底面高于该第二鳍片的底面。
12.如权利要求9所述的半导体结构，其特征在于，该第一鳍片的高度为30至50纳米且该第二鳍片的高度为40至70纳米。
13.如权利要求9所述的半导体结构，其特征在于，该隔离层直接接触该第一鳍片的该底面与该第二鳍片的底面。
14.如权利要求9所述的半导体结构，其特征在于，该隔离层包含二氧化硅。
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CN109887845B (zh) * 2017-12-06 2022-03-18 中芯国际集成电路制造(上海)有限公司 半导体器件及其形成方法
US10991584B2 (en) * 2017-12-19 2021-04-27 International Business Machines Corporation Methods and structures for cutting lines or spaces in a tight pitch structure
US11220424B2 (en) * 2018-08-09 2022-01-11 Honeywell International Inc. Methods for increasing aspect ratios in comb structures
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US7560785B2 (en) * 2007-04-27 2009-07-14 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device having multiple fin heights
US8263462B2 (en) * 2008-12-31 2012-09-11 Taiwan Semiconductor Manufacturing Company, Ltd. Dielectric punch-through stoppers for forming FinFETs having dual fin heights
US9257325B2 (en) * 2009-09-18 2016-02-09 GlobalFoundries, Inc. Semiconductor structures and methods for forming isolation between Fin structures of FinFET devices
US8101486B2 (en) 2009-10-07 2012-01-24 Globalfoundries Inc. Methods for forming isolated fin structures on bulk semiconductor material
US8993402B2 (en) * 2012-08-16 2015-03-31 International Business Machines Corporation Method of manufacturing a body-contacted SOI FINFET
US8766363B2 (en) * 2012-11-07 2014-07-01 International Business Machines Corporation Method and structure for forming a localized SOI finFET
US9000522B2 (en) * 2013-01-09 2015-04-07 International Business Machines Corporation FinFET with dielectric isolation by silicon-on-nothing and method of fabrication
US9331201B2 (en) * 2013-05-31 2016-05-03 Globalfoundries Inc. Multi-height FinFETs with coplanar topography background
US9006077B2 (en) 2013-08-21 2015-04-14 GlobalFoundries, Inc. Gate length independent silicon-on-nothing (SON) scheme for bulk FinFETs
US9041062B2 (en) 2013-09-19 2015-05-26 International Business Machines Corporation Silicon-on-nothing FinFETs
US9190466B2 (en) * 2013-12-27 2015-11-17 International Business Machines Corporation Independent gate vertical FinFET structure
US9269814B2 (en) 2014-05-14 2016-02-23 Taiwan Semiconductor Manufacturing Co., Ltd. Sacrificial layer fin isolation for fin height and leakage control of bulk finFETs
US9385023B1 (en) * 2015-05-14 2016-07-05 Globalfoundries Inc. Method and structure to make fins with different fin heights and no topography
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