TWI593101B - 半導體結構與其製造方法 - Google Patents
半導體結構與其製造方法 Download PDFInfo
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- TWI593101B TWI593101B TW105121427A TW105121427A TWI593101B TW I593101 B TWI593101 B TW I593101B TW 105121427 A TW105121427 A TW 105121427A TW 105121427 A TW105121427 A TW 105121427A TW I593101 B TWI593101 B TW I593101B
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- isolation region
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Classifications
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
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- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/7855—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with at least two independent gates
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- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
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- H01L29/0843—Source or drain regions of field-effect devices
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- H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
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- H01L29/4991—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material comprising an air gap
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
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- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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Description
本揭露是有關於一種半導體結構。
隨著半導體工業已發展步入奈米技術製程節點以追求更高裝置密度、更高效能及更低成本,來自製造問題與設計問題兩者的挑戰導致了三維設計(諸如鰭式場效電晶體(fin field effect transistor;FinFET))的發展。典型FinFET經製造具有自基板延伸的薄垂直「鰭片」(或鰭式結構),此鰭片藉由例如蝕刻掉基板之矽層的一部分形成。在此垂直鰭片中形成FinFET之通道。在鰭片上方提供(例如,包覆)閘極。在通道之兩側上具有閘極以允許通道自兩側之閘控制。然而,此類特徵與製程在半導體製造中之實施存在挑戰。
一實施方式係一種半導體結構,包含:基板上方的第一鰭片;基板上方的第二鰭片,第二鰭片與第一鰭片相鄰;圍繞第一鰭片與第二鰭片的隔離區域;沿第一鰭片與第二鰭片側壁且位於第一鰭片與第二鰭片之上表面上方的
閘極結構,閘極結構定義第一鰭片與第二鰭片中的通道區域;於第一鰭片與第二鰭片上且與閘極結構相鄰的源極/汲極區域;以及使源極/汲極區域與基板之頂表面分離的空氣間隙。
另一實施方式係一種半導體結構的製造方法,包含:形成基板之凸起部分;在基板之凸起部分上形成鰭片;形成隔離區域以圍繞鰭片,隔離區域之第一部分位於相鄰鰭片之間的基板之凸起部分之頂表面上;形成閘極結構在鰭片上方;以及在閘極結構之相對側上形成源極/汲極區域,源極/汲極區域中的至少一者具有使至少一個源極/汲極區域與隔離區域之第一部分分離的空氣間隙。
又一實施方式係一種半導體結構的製造方法,此方法包含:在基板上方形成第一鰭片;形成隔離區域以圍繞第一鰭片;形成第一閘極結構在第一鰭片上方;使第一閘極結構外部的第一鰭片形成凹陷以在隔離區域之頂表面下方具有頂表面;以及自第一閘極結構外部的凹陷第一鰭片磊晶生長第一源極/汲極區域,隔離區域限制第一源極/汲極區域之磊晶生長。
上述實施方式提供簡單且具有成本效益的製程流程,從而在FinFET中的至少FinFET之通道區域附近實現具有較少缺陷(諸如錯位)的磊晶源極/汲極以便裝置增強。
30‧‧‧鰭式場效電晶體、FinFET
32、50‧‧‧基板
34、62‧‧‧隔離區域
36‧‧‧鰭片
38、66‧‧‧閘極介電質
40‧‧‧閘電極
42、44‧‧‧源極/汲極區域
52、56‧‧‧遮罩層、硬遮罩
54‧‧‧部分
58‧‧‧冠結構
60‧‧‧半導體條帶
64‧‧‧半導體鰭片
68‧‧‧閘極
70‧‧‧遮罩
72‧‧‧閘極密封間隔層
76‧‧‧凹部
80‧‧‧源極/汲極區域、應力層
82‧‧‧空氣間隙
84‧‧‧帽蓋層
90‧‧‧層間介電質、ILD
92‧‧‧觸點
96‧‧‧緩衝層
B-B、C-C‧‧‧線
H1、H2、H3、H4、H5‧‧‧高度
S1‧‧‧間隔
T1、T2‧‧‧厚度
當結合隨附圖式閱讀時,自以下詳細描述將很好地理解本揭露之態樣。應注意,根據工業中的標準實務,各特徵並非按比例繪製。事實上,出於描述清晰之目的,可任意增加或減小各特徵之尺寸。
第1圖為一實施方式之FinFET的立體圖。
第2圖至第6圖、第7A圖至第7C圖、第8A圖至第8C圖及第9圖至第15圖係根據一些實施方式的FinFET製造中的中間階段的立體與剖面圖。
第16圖係根據示例性實施方式的FinFET製造中的中間階段之剖面圖。
第17圖係根據示例性實施方式的FinFET製造中的中間階段之剖面圖。
第18圖係根據示例性實施方式的FinFET製造中的中間階段之剖面圖。
以下揭露提供許多不同實施方式或範例,以便實施所提供標的之不同特徵。下文描述組件及排列之特定範例以簡化本揭露內容。當然,此等範例僅為示例性且並不欲為限制性。舉例而言,以下描述中在第二特徵上方或第二特徵上形成第一特徵可包含以直接接觸形成第一特徵及第二特徵的實施方式,且亦可包含可在第一特徵與第二特徵之間形成額外特徵以使得第一特徵及第二特徵可不處於直接接觸的實施方式。另外,本揭露可在各範例中重複元件符號與
/或字母。此重複係出於簡明性及清晰之目的,且本身並不指示所描述之各實施方式與/或配置之間的關係。
另外,為了便於描述,本文可使用空間相對性術語(諸如「之下」、「下方」、「下部」、「上方」、「上部」及類似者)來描述諸圖中所圖示一個元件或特徵與另一元件(或多個元件)或特徵(或多個特徵)之關係。類似地,本文可使用諸如「前側」及「背側」之術語來更容易地識別各組件,及可識別彼等組件例如位於另一組件之相對側。除了諸圖所描繪之定向外,空間相對性術語意欲包含使用或操作中裝置之不同定向。設備可經其他方式定向(旋轉90度或處於其他定向上)且因此可類似解讀本文所使用之空間相對性描述詞。
根據各實施方式提供鰭式場效電晶體(finFET)與形成這些鰭式場效電晶體之方法。圖示提供形成鰭式場效電晶體之中間階段。在使用前閘極(gate-first)製程所形成之FinFET的情境中描述本文所描述之一些實施方式。在其他實施方式中,可使用後閘極(gate-last)製程(有時稱為替換閘極製程)。一些實施方式的變化被討論。本技術領域中的一般技術者應將容易理解,可實行之其他修改涵蓋於其他實施方式之範疇內。儘管以特定次序描述方法實施方式,但是各種其他方法實施方式可以任何邏輯次序執行及可包含更少或更多的本文所描述之步驟。
在特定說明所繪示之實施方式之前,將大略說明本揭露所揭露之實施方式之某些有利特徵及態樣。大體而
言,本揭露係一種半導體裝置與形成此半導體裝置之方法,以提供簡單且具有成本效益的製程流程,從而在FinFET中的至少FinFET之通道區域附近實現具有較少缺陷(諸如錯位)的磊晶源極/汲極以便增強裝置。另外,此簡單且具有成本效益的製程流程可藉由減少相鄰鰭片之間的漏泄實現相鄰鰭片之間的較佳隔離且亦可減小對源極/汲極區域的接觸電阻。具體而言,實施方式(諸如下文所揭露之實施方式)包含利用FinFET冠結構的製程流程,其中在相鄰鰭片之間的冠之頂表面上留下隔離區域(例如,淺溝槽隔離(shallow trench isolation;STI)區域)之一些隔離材料。因為減小了相鄰鰭片之間的磊晶體積量,此剩餘隔離材料抑制錯位的產生。進一步地,隔離區域在冠結構之頂表面與磊晶源極/汲極區域之間形成空氣間隙,空氣間隙將減小介電常數(k值),進而可減小相鄰鰭片之間的寄生電容。此減小的寄生電容可允許裝置之較佳交流電(alternating current;AC)效能。進一步地,磊晶源極/汲極結構之上表面可具有非平面(例如,起伏與/或波浪狀)頂表面,從而可增加上層接觸的接觸表面積。此增加的接觸表面積可減小對源極/汲極區域的接觸電阻。
在一些實施方式中,所揭露之製程流程可用於靜態隨機存取記憶體(static random access memory;SRAM)裝置之形成。在這些實施方式中,相鄰鰭片之間的剩餘隔離材料可幫助限制源極/汲極區域之磊晶體積,從而減小相鄰SRAM電晶體之源極/汲極合併在一起的可能性。
此減小的合併可能性增加了裝置之良率,同時仍允許相鄰SRAM電晶體之間的所欲減小間隔。
第1圖為一實施方式之FinFET 30的立體圖。FinFET 30包含基板32上的鰭片36。基板32包含隔離區域34,且鰭片36自相鄰隔離區域34之間向上突出。閘極介電質38沿鰭片36之側壁且位於鰭片36之頂表面上方,且閘電極40位於閘極介電質38上方。源極/汲極區域42與44位於鰭片36針對閘極介電質38與閘電極40之相對側上。第1圖進一步圖示用於稍後圖式中的參考剖面線。剖面線B-B跨finFET 30之通道、閘極介電質38與閘電極40。剖面線C-C平行於剖面線B-B且橫跨源極/汲極區域42。為了清晰起見,後續圖式參考這些參考剖面線。
第2圖至第15圖係根據一些實施方式的FinFET製造中的中間階段的立體與剖面圖。第2圖至第13圖類似於第1圖中的FinFET 30之FinFET,不同處在於冠結構上的多個鰭片。在第7A圖至第8C圖中,以「A」結尾的圖式為立體圖;以「B」結尾的圖式圖示為剖面線B-B之面;以「C」結尾的圖式圖示剖面線C-C之面。第9圖至第15圖圖示剖面線C-C之面。
第2圖圖示基板50。基板50可為半導體基板,諸如塊體半導體、絕緣體上半導體(semiconductor-on-insulator;SOI)基板或類似者,這些半導體基板可為摻雜(例如,p型或n型摻雜劑)或無摻雜。基板50可為晶圓,諸如矽晶圓。大體而言,SOI基板包含形成
於絕緣體層上的半導體材料層。絕緣體層可為例如內埋氧化物(buried oxide;BOX)層、氧化矽層或類似者。在基板(通常為矽或玻璃基板)上提供絕緣體層。亦可使用其他基板,諸如多層或梯度基板。在一些實施方式,基板50之半導體材料可包含:矽;鍺;化合物半導體,包含碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦與/或銻化銦;合金半導體,包含矽鍺(SiGe)、磷砷鎵(GaAsP)、鋁銦砷(AlInAs)、鋁鎵砷(AlGaAs)、鎵銦砷(GaInAs)、鎵銦磷(GaInP)與/或鎵銦砷磷(GaInAsP)或上述之組合。
基板50可包含積體電路裝置(未圖示)。本技術領域中的一般技術者應將認識到,可在基板50中與/或上形成多種積體電路裝置,諸如電晶體、二極體、電容器、電阻器、類似者或上述之組合,以針對FinFET產生設計之結構與功能要求。可使用任何適宜方法形成積體電路裝置。
第2圖進一步繪示基板50上方的遮罩層52之形成以及利用遮罩層52圖案化基板50以形成基板50的圖案化部分54。在一些實施方式中,遮罩層52為硬遮罩,下文中可稱為硬遮罩52。硬遮罩52可由氮化矽、氧氮化矽、碳化矽、碳氮化矽、類似者或上述之組合形成。
在一些實施方式中,可藉由蝕刻位於圖案化遮罩層52外部的基板50以形成基板50之圖案化部分54。蝕刻可為任何可接受蝕刻製程,諸如反應性離子蝕刻(reactive ion etch;RIE)、中性束蝕刻(neutral beam etch;NBE)、類似者或上述之組合。蝕刻可為非等向性。
第3圖為冠結構58與冠結構58上方的半導體條帶60之形成。遮罩層56可形成在基板50之圖案化部分54上方並圖案化。在一些實施方式中,遮罩層56為硬遮罩,下文中可稱為硬遮罩56。硬遮罩56可由氮化矽、氧氮化矽、碳化矽、碳氮化矽、類似者或上述之組合形成。
在一些實施方式中,可藉由蝕刻硬遮罩56與基板50之圖案化部分54中的溝槽以形成冠結構58與半導體條帶60。半導體條帶60亦可稱為半導體鰭片60。蝕刻可為任何可接受蝕刻製程,諸如RIE、NBE、類似者或上述之組合。蝕刻可為非等向性。
第4圖繪示相鄰半導體條帶60之間的絕緣材料的形成以形成隔離區域62。絕緣材料可為氧化物(諸如氧化矽)、氮化物、類似者或上述之組合,且可藉由以下製程形成:高密度電漿化學氣相沉積(high density plasma chemical vapor deposition;HDP-CVD)、可流動CVD(flowable CVD;FCVD)(例如,在遠端電漿系統中基於CVD的材料沉積及後固化以使得材料轉換成諸如氧化物之另一材料)、類似者或上述之組合。可使用藉由任何可接受製程形成之其他絕緣材料。在圖示之實施方式中,絕緣材料為藉由流動式化學氣相沉積系統(FCVD)製程形成之氧化矽。一旦形成絕緣材料,可執行退火製程。進一步地,在第4圖中,平坦化製程(諸如化學機械研磨(chemical mechanical polish;CMP))可移除任何過量絕緣材料(且
若存在,硬遮罩56)與形成隔離區域62之頂表面及半導體條帶60之頂表面,兩個頂表面為共面。
第5圖繪示隔離區域62之凹陷,諸如以形成淺溝槽隔離(shallow trench isolation;STI)區域。使隔離區域62形成凹陷以使得半導體條帶60之上部部分自相鄰隔離區域62之間突出並形成半導體鰭片64。如圖所示,隔離區域62之一些部分留在相鄰半導體鰭片64之間的冠結構58之頂部上。進一步地,隔離區域62之頂表面可具有平坦表面(如圖所示)、凸形表面、凹形表面(諸如碟形)或上述之組合。可藉由適當蝕刻將隔離區域62之頂表面形成為平坦、凸形與/或凹形。可使用可接受蝕刻製程使隔離區域62形成凹陷,製程諸如對隔離區域62之材料選擇性蝕刻的製程。舉例而言,可使用化學氧化物移除,此製程使用CERTAS®蝕刻或應用材料公司SICONI工具或稀釋氟化氫(hydrofluoric;dHF)酸。
第5圖繪示半導體鰭片64上方的閘極結構之形成。在半導體鰭片64與隔離區域62上形成介電層(未圖示)。介電層可為例如氧化矽、氮化矽、上述之多層或類似者,且可根據可接受技術沉積或熱生長介電層。在一些實施方式中,介電層可為高k介電材料,且在這些實施方式中,介電層可具有大於約7.0的k值,及可包含鉿(Hf)、鋁(Al)、鋯(Zr)、鑭(La)、鎂(Mg)、鋇(Ba)、鈦(Ti)、鉛(Pb)之金屬氧化物或矽酸鹽、上述之多層或上述之組合。介電層之形成方法可包含分子束沉積(molecular-beam deposition;
MBD)、原子層沉積(atomic layer deposition;ALD)、電漿增強CVD(plasma-enhanced CVD;PECVD)及類似者。
在介電層上方形成閘極層(未圖示),且在閘極層上方形成遮罩層(未圖示)。可在介電層上方沉積閘極層及隨後諸如藉由他學機械研磨(CMP)平坦化閘極層。可在閘極層上方沉積遮罩層。閘極層可由例如多晶矽形成,但亦可使用其他材料。在一些實施方式中,閘極層可包含含金屬材料,諸如氮化鈦(TiN)、氮化鉭(TaN)、碳化鉭(TaC)、鈷(Co)、釕(Ru)、鋁(Al)、上述之組合或上述之多層。遮罩層可由例如氮化矽或類似者形成。
在形成層後,可使用可接受之光微影與蝕刻技術圖案化遮罩層以形成遮罩70。隨後可藉由可接受之蝕刻技術將遮罩70的圖案轉印至閘極層與介電層以形成閘極68與閘極介電質66。閘極68與閘極介電質66覆蓋半導體鰭片64之各別通道區域。閘極68亦可具有實質上垂直於各別半導體鰭片64之縱向的縱向。
第7A圖、第7B圖與第7C圖繪示隔離區域62、半導體鰭片64、閘極68與遮罩70之暴露表面上的閘極密封間隔層72之形成。熱氧化或沉積製程可形成閘極密封間隔層72。在一些實施方式中,閘極密封間隔層72可由氮化物形成,諸如氮化矽、氧氮化矽、碳化矽、碳氮化矽、類似者或上述之組合。閘極密封間隔層72之形成可繼之以非等向性蝕刻製程(諸如乾式蝕刻製程)以移除閘極結構之側壁外
部的閘極密封間隔層72之多個部分。在一些實施方式中,在蝕刻製程後,閘極密封間隔層72之一些部分留在相鄰半導體鰭片64之間的隔離區域62上(參看第9圖、第15圖與第17圖)。
第8A圖、第8B圖及第8C圖繪示閘極結構外部的半導體鰭片64之移除。閘極結構可在半導體鰭片64之移除期間用作遮罩以使得在半導體鰭片64與/或隔離區域62中形成凹部76。如圖所示,在半導體鰭片64之移除後,至少一部分之隔離區域62留在相鄰半導體鰭片64之間的冠結構58之頂表面上。
可藉由使用任何可接受蝕刻製程的蝕刻形成凹部76,製程諸如RIE、NBE、氫氧化四甲銨(tetramethyalammonium hydroxide;TMAH)、氫氧化銨(NH4OH)、在矽與隔離區域62與/或閘極密封間隔層72之材料之間具有良好蝕刻選擇性下能夠蝕刻矽的濕式蝕刻劑、類似者或上述之組合。蝕刻可為非等向性。在一些實施方式中,曝露冠結構58之頂表面作為凹部76至少部分之底表面。
第9圖繪示部分閘極密封間隔層材料72留在相鄰半導體鰭片64之間的隔離區域62上的實施方式。在本實施方式中,蝕刻製程可為直接轟擊蝕刻製程,此製程自暴露半導體鰭片64之頂表面移除閘極密封間隔層72(參看第7C圖),同時閘極密封間隔層材料72之某個部分留在隔離區域62上。一些閘極密封間隔層材料72留在隔離區域62上的原
因可至少部分在於隔離區域62上形成之閘極密封間隔層材料72與半導體鰭片64之頂表面相比更厚(參看第7C圖)。
第10圖與第11圖繪示源極/汲極區域80之形成。藉由在凹部76中磊晶成長材料來在凹部76中形成源極/汲極區域80,諸如藉由金屬有機物CVD(metal-organic CVD;MOCVD)、分子束磊晶(molecular beam epitaxy;MBE)、液相磊晶(liquid phase epitaxy;LPE)、氣相磊晶(vapor phase epitaxy;VPE)、選擇性磊晶生長(selective epitaxial growth;SEG)、類似者或上述之組合。如第10圖所圖示,由於相鄰半導體鰭片64之間的隔離區域62之阻擋,在凹部76中先垂直生長源極/汲極區域80,在此期間源極/汲極區域80不水平生長。在完全填滿凹部76後,在垂直與水平兩者方向上生長源極/汲極區域80以形成刻面(參看第11圖)。
如第11圖所示,相鄰半導體鰭片80之源極/汲極區域80合併以形成連續磊晶源極/汲極區域80。由於冠結構58上的隔離區域62之阻擋,在源極/汲極區域80之下部部分與冠結構58上的隔離區域62之頂表面之間形成空氣間隙82。
在源極/汲極區域80之形成後,在源極/汲極區域80上形成帽蓋層84。帽蓋層84與緩衝層可視為源極/汲極區域的一部分。在一些實施方式中,在源極/汲極區域80上磊晶生長帽蓋層84。帽蓋層幫助保護源極/汲極區域80在後續處理(例如,蝕刻製程、溫度處理等)期間避免摻雜劑損
失。可將源極/汲極區域80之構形控制為非平面(如第11圖所示)或平面(參看第14圖)。
半導體鰭片64在冠結構58之頂表面上方延伸高度H1。在一些實施方式中,高度H1小於約60nm。在一些實施方式中,高度H1小於約40nm。在一些實施方式中,高度H1小於約30nm。磊晶源極/汲極區域80可延伸至冠結構58中達高度H2。在一些實施方式中,高度H2之範圍為約5nm至約30nm範圍內。延伸至冠結構58中的源極/汲極區域80之部分可稱為緩衝層,因為這部分緩衝上方的較高摻雜劑濃度源極/汲極區域80與下方的冠結構58之間的應變差。緩衝層之摻雜劑濃度與源極/汲極區域80之剩餘部分可不同。舉例而言,緩衝層可具有小於約40%之Ge濃度,同時源極/汲極區域80之剩餘部分具有大於40%之Ge濃度。源極/汲極區域80之剩餘部分之較高濃度允許源極/汲極區域80施加較大應力至FinFET之通道區域。源極/汲極區域80之此高摻雜劑濃度部分可稱為應力層80。另外,帽蓋層84與應力層80之摻雜劑濃度可不同。舉例而言,帽蓋層84可具有小於約40%之Ge濃度,同時應力層80具有大於40%之Ge濃度。
在一些實施方式中,可在單個連續磊晶製程中形成緩衝層、應力層80與帽蓋層84。在其他實施方式中,可在獨立製程中形成這些結構。在具有單個連續製程的實施方式中,可改變磊晶製程之處理參數(例如,製程氣體流量、溫度、壓力等)以形成具有不同材料組成物的這些結構。舉
例而言,在磊晶期間,含鍺前驅物(諸如GeH4)之流動速率可在緩衝層之形成期間處於第一位準且可在過渡至應力層80之形成時增加至第二位準。進一步地,在過渡至帽蓋層84之形成時,可將含鍺前驅物之流動速率自第二位準減小至第三位準。
如第11圖所示,冠結構58上的隔離區域62之剩餘部分可具有厚度T1。在一些實施方式中,厚度T1的範圍為約2nm至約15nm範圍內。空氣間隙82可具有大於約4nm之高度H3。可將帽蓋層84形成至厚度T2,T2大於2nm。帽蓋層84之頂表面可具有最高點與最低點之間的高度H4。在一些實施方式中,高度H4大於約3nm。可藉由間隔S1分離FinFET裝置之相鄰鰭片。在一些實施方式中,間隔S1小於約40nm。
在所得FinFET為n型FinFET的一些示例性實施方式中,源極/汲極區域80包含碳化矽(SiC)、磷化矽(SiP)、摻磷的矽碳(SiCP)或類似者。在所得FinFET為p型FinFET的替代示例性實施方式中,源極/汲極區域80包含SiGe與諸如硼或銦之p型雜質。
可利用摻雜劑植入磊晶源極/汲極區域80以形成源極/汲極區域,隨後繼之以退火。植入製程可包含形成與圖案化遮罩(諸如光阻劑)以覆蓋欲保護避免受植入製程影響的FinFET之區域。源極/汲極區域80可具有自約1019cm-3至約1021cm-3範圍內之雜質濃度。在一些實施方式中,可在生長期間原位摻雜磊晶源極/汲極區域80。
可執行FinFET裝置之後續處理,諸如一或更多個層間介電質之形成與觸點之形成。下文將關於第12圖及第13圖描述這些製程。
在第12圖中,在第11圖中所示之結構上方沉積層間介電質(interlayer dielectric;ILD)90。層間介電質90係由諸如磷矽玻璃(phosphosilicate glass;PSG)、硼矽玻璃(borosilicate glass;BSG)、摻硼的磷矽玻璃(boron-doped phosphosilicate Glass;BPSG)、無摻雜矽酸玻璃(undoped silicate glass;USG)或類似者之介電材料形成,且可藉由任何適宜方法(諸如CVD、PECVD或FCVD)沉積。
在第13圖中,穿過層間介電質90形成觸點92。穿過層間介電質90形成觸點92的開口。可使用可接受之光微影與蝕刻技術形成開口。在一些實施方式中,在開口形成期間移除帽蓋層84的至少一部分。在開口中形成襯墊(諸如擴散阻障層、黏著層或類似者)與導電材料。襯墊可包含鈦、氮化鈦、鉭、氮化鉭或類似者。導電材料可為銅、銅合金、銀、金、鎢、鋁、鎳或類似者。可執行平坦化製程(諸如CMP)以自層間介電質90之表面移除過量材料。剩餘襯墊與導電材料在開口中形成觸點92。可執行退火製程以在源極/汲極區域80(若存在,帽蓋層84)與觸點92之間的界面處形成矽化物。將觸點92實體及電耦接至源極/汲極區域80(若存在,帽蓋層84)。
儘管未明確圖示,但本技術領域中的一般技術者將容易理解,可在第13圖中的結構上執行進一步處理步驟。舉例而言,可在層間介電質90上方形成各金屬間介電質(Inter-Metal Dielectrics;IMD)及相應金屬化物。進一步地,可穿過上覆介電層形成閘電極68的觸點。
進一步地,在一些實施方式中,可使用後閘極製程(有時稱為替換閘極製程)。在這些實施方式中,閘極68與閘極介電質66可視為虛設(dummy)結構並將在後續處理期間移除,再用主動(active)閘與主動閘介電質替換這些虛設結構。
第14圖繪示源極/汲極區域80具有實質平坦表面的實施方式。本實施方式類似於上文在第2圖至第13圖中所描述之實施方式,只不過本實施方式對於源極/汲極區域80具有平坦頂表面,而先前實施方式具有起伏頂表面(例如,波浪狀頂表面)。本文將不再重複關於本實施方式類似於先前描述實施方式之的細節。
可藉由改變用於形成源極/汲極區域80的磊晶製程之參數控制頂表面之形狀/配置。舉例而言,藉由執行磊晶製程經歷較長時間框,源極/汲極區域將自波浪狀頂表面配置變成平坦頂表面配置。
第15圖係根據示例性實施方式的FinFET製造中的中間階段之剖面圖。本實施方式類似於上文在第2圖至第14圖中所描述之實施方式,只不過本實施方式包含相鄰半導體鰭片64之間的閘極密封間隔層72之剩餘部分。本文
將不再重複關於本實施方式的細節,此等細節類似於先前描述實施方式之細節。
本實施方式類似於第9圖中所圖示之實施方式,其中在第9圖之結構上形成源極/汲極區域80與帽蓋層84。閘極密封間隔層72之剩餘部分在相鄰鰭片之間的隔離區域62之剩餘部分上的添加與在鰭片之間不具有閘極密封間隔層72之部分的實施方式相比可增加空氣間隙82之高度H4。
儘管第2圖至第15圖中的實施方式圖示每個FinFET的三個鰭片,但其他實施方式對於每個FinFET涵蓋更多或更少鰭片。
第16圖係根據示例性實施方式的FinFET製造中的中間階段之剖面圖。第16圖圖示第1圖之剖面線C-C之面。本實施方式類似於上文在第2圖至第15圖中所描述之實施方式,只不過本實施方式為FinFET具有單個鰭片的實施方式,而先前實施方式對於FinFET具有三個鰭片。本文將不再重複關於本實施方式的細節,此等細節類似於先前描述實施方式之細節。
在一些實施方式中,第16圖中的結構可用於SRAM裝置中的p型金氧半導體(p-type metal-oxide-semiconductor;PMOS)電晶體。舉例而言,第15圖中的裝置可用作SRAM裝置中的上拉電晶體。在一些實施方式中,源極/汲極區域80包含SiGe及諸如硼或銦之p型雜質。類似於先前實施方式,隔離區域62之某個部分留
在回蝕半導體鰭片64時所形成之凹部之開口附近。此剩餘隔離區域62幫助限制源極/汲極區域80之磊晶體積,從而可減小相鄰SRAM電晶體之源極/汲極區域80將合併在一起的可能性。此減小的合併可能性增加了裝置之良率,同時仍允許相鄰SRAM電晶體之間的所欲減小間隔。
第17圖係根據示例性實施方式的FinFET製造中的中間階段之剖面圖。第17圖圖示第1圖之剖面線C-C之面。本實施方式類似於上文在第16圖中所描述之實施方式,只不過本實施方式包含圍繞鰭片的閘極密封間隔層72之剩餘部分,這些部分包含相鄰鰭片之間的一部分。本文將不再重複關於本實施方式的細節,此等細節類似於先前描述實施方式之細節。
添加閘極密封間隔層72之剩餘部分在相鄰鰭片之間的隔離區域62之剩餘部分上的實施方式,與鰭片之間不具有部分閘極密封間隔層72的實施方式相比,可進一步限制源極/汲極區域80之磊晶體積與可進一步減小相鄰源極/汲極區域80合併在一起的可能性。圍繞鰭片且位於回蝕半導體鰭片64時所形成之凹部之開口附近的材料(例如,隔離區域62與閘極密封間隔層72)愈厚,源極/汲極區域80之磊晶體積受限愈多,因此進一步減小相鄰SRAM電晶體之源極/汲極區域80將合併在一起的可能性。
第18圖係根據示例性實施方式的FinFET製造中的中間階段之剖面圖。第18圖繪示第1圖之剖面線C-C之面。本實施方式類似於上文在第16圖及第17圖中所描述之
實施方式,只不過本實施方式在冠結構58上有兩個鰭片。本文將不再重複關於本實施方式的細節,此等細節類似於先前描述實施方式之細節。
在一些實施方式中,第18圖中的結構可用於SRAM裝置中的n型金氧半導體(n-type metal-oxide-semiconductor;NMOS)電晶體。舉例而言,第18圖中的裝置可用作SRAM裝置中的下拉電晶體。在本實施方式中,源極/汲極區域80可包含SiC、SiP、SiCP或類似者。類似於先前實施方式,某部分隔離區域62留在回蝕半導體鰭片64時所形成之凹部之開口附近。此剩餘隔離區域62幫助在相鄰半導體鰭片64之間形成空氣間隙82。在本實施方式中,將緩衝層標記為緩衝層96,而在先前實施方式中,將緩衝層包含在源極/汲極區域80中。類似於先前實施方式,緩衝層96包含與源極/汲極區域80類似的摻雜劑但具有較低摻雜劑濃度。
儘管未繪示,但本實施方式亦可包含相鄰鰭片之間的隔離區域62之剩餘部分上的閘極密封間隔層72之剩餘部分(參看第17圖)。
實施方式可實現多個優勢。舉例而言,本揭露係一種半導體裝置與形成此半導體裝置之方法,以提供簡單且具有成本效益的製程流程,從而在FinFET中的至少FinFET之通道區域附近實現具有較少缺陷(諸如錯位)的磊晶源極/汲極以便裝置增強。另外,此簡單且具有成本效益的製程流程可藉由減少相鄰鰭片之間的漏泄實現相鄰鰭片
之間的較佳隔離,亦可減小對源極/汲極區域的接觸電阻。具體而言,實施方式(諸如下文所揭露之實施方式)包含利用FinFET冠結構的製程流程,其中在相鄰鰭片之間的冠之頂表面上留下隔離區域(例如,淺溝槽隔離(STI)區域)之一些隔離材料。此剩餘隔離材料抑制錯位的產生,因為減小了相鄰鰭片之間的磊晶體積量。進一步地,隔離區域引發在冠結構之頂表面與磊晶源極/汲極區域之間形成空氣間隙,空氣間隙將減小介電常數(k值),進而可減小相鄰鰭片之間的寄生電容。此減小的寄生電容可允許裝置之較佳交流電(AC)效能。進一步地,磊晶源極/汲極結構之上表面可具有非平面(例如,起伏)頂表面,從而可增加重疊接觸的接觸表面積。此增加的接觸表面積可減小對源極/汲極區域的接觸電阻。
一實施方式係一種半導體結構,包含:基板上方的第一鰭片;基板上方的第二鰭片,第二鰭片與第一鰭片相鄰;圍繞第一鰭片與第二鰭片的隔離區域;沿第一鰭片與第二鰭片側壁且位於第一鰭片與第二鰭片之上表面上方的閘極結構,閘極結構定義第一鰭片與第二鰭片中的通道區域;於第一鰭片與第二鰭片上且與閘極結構相鄰的源極/汲極區域;以及使源極/汲極區域與基板之頂表面分離的空氣間隙。
另一實施方式係一種半導體結構的製造方法,包含:形成基板之凸起部分;在基板之凸起部分上形成鰭片;形成隔離區域以圍繞鰭片,隔離區域之第一部分位於相
鄰鰭片之間的基板之凸起部分之頂表面上;形成閘極結構在鰭片上方;以及在閘極結構之相對側上形成源極/汲極區域,源極/汲極區域中的至少一者具有使至少一個源極/汲極區域與隔離區域之第一部分分離的空氣間隙。
又一實施方式係一種半導體結構的製造方法,此方法包含:在基板上方形成第一鰭片;形成隔離區域以圍繞第一鰭片;形成第一閘極結構在第一鰭片上方;使第一閘極結構外部的第一鰭片形成凹陷以在隔離區域之頂表面下方具有頂表面;以及自第一閘極結構外部的凹陷第一鰭片磊晶生長第一源極/汲極區域,隔離區域限制第一源極/汲極區域之磊晶生長。
上文概述若干實施方式之特徵,使得熟習此項技術者可更好地理解本揭露之態樣。熟習此項技術者應瞭解,可輕易使用本揭露作為設計或修改其他製程及結構的基礎,以便實施本文所介紹之實施方式的相同目的與/或實現相同優勢。熟習此項技術者亦應認識到,此類等效結構並未脫離本揭露之精神及範疇,且可在不脫離本揭露之精神及範疇的情況下產生本文的各種變化、替代及更改。
50‧‧‧基板
58‧‧‧冠結構
62‧‧‧隔離區域
80‧‧‧源極/汲極區域
82‧‧‧空氣間隙
84‧‧‧帽蓋層
H1、H2、H3、H4‧‧‧高度
S1‧‧‧間隔
T1、T2‧‧‧厚度
Claims (10)
- 一種半導體結構,包含:一第一鰭片,置於一基板上;一第二鰭片,置於該基板上,該第二鰭片與該第一鰭片相鄰;一第一隔離區域,置於該第一鰭片與該第二鰭片之間;一第二隔離區域,其中該第一鰭片置於該第一隔離區域與該第二隔離區域之間,且該第二隔離區域的深度大於該第一隔離區域的深度;一閘極結構,沿該第一鰭片與該第二鰭片之上表面與側壁設置,該閘極結構定義該第一鰭片與該第二鰭片的通道區域;一源極/汲極區域,置於與該閘極結構相鄰的該第一鰭片與該第二鰭片上;以及一空氣間隙,使該源極/汲極區域分離該基板之一頂表面。
- 如請求項1所述之半導體結構,其中該第一鰭片與該第二鰭片自該基板之一凸起部分延伸,該空氣間隙位於該基板之該凸起部分之一頂表面與該源極/汲極區域之間,該第二隔離區域毗鄰該凸起部分,且該第一隔離區域置於該凸起部分上。
- 如請求項2所述之半導體結構,其中該第一隔離區域於該基板之該凸起部分之該頂表面與該空氣間隙之間。
- 如請求項3所述之半導體結構,更包含一閘極密封間隔層,置於該閘極結構之側壁上,部分之該閘極密封間隔層位於該第一隔離區域與該空氣間隙之間。
- 一種半導體結構的製造方法,包含:形成一基板之一凸起部分;在該基板之該凸起部分上形成鰭片;形成至少一第一隔離區域與複數個第二隔離區域以圍繞該些鰭片,該第一隔離區域位於相鄰之該些鰭片之間的該基板之該凸起部分之一頂表面上,該些第二隔離區域定義該凸起部分,且該些第二隔離區域的深度大於該第一隔離區域的深度;形成一閘極結構在該些鰭片上方;以及形成源極/汲極區域在該閘極結構之相對側上,該些源極/汲極區域中的至少一者具有使該至少一個源極/汲極區域與該第一隔離區域分離的一空氣間隙。
- 如請求項5所述之方法,更包含:形成一閘極密封間隔層在該閘極結構之側壁上,該閘極密封間隔層的一第一部分位於該第一隔離區域與該空氣間隙之間。
- 如請求項5所述之方法,其中該形成該源極/汲極區域更包含:使該閘極結構外部的該些鰭片形成凹陷以在該隔離區域之一頂表面下方具有頂表面;以及自該些閘極結構之相對側上的該些凹陷鰭片磊晶生長該些源極/汲極區域。
- 一種半導體結構的製造方法,包含:在一基板上方形成一第一鰭片;形成一第二鰭片在該基板上方,該第二鰭片與該第一鰭片相鄰;形成一第一隔離區域於該第一鰭片與該第二鰭片之間,且形成一第二隔離區域於該基板上,其中該第一鰭片位於該第一隔離區域與該第二隔離區域之間,且該第二隔離區域的深度大於該第一隔離區域的深度;形成一第一閘極結構在該第一鰭片上方;使該第一閘極結構外部的該第一鰭片形成凹陷以在該第一隔離區域之一頂表面下方具有一頂表面;以及自該第一閘極結構外部的該凹陷第一鰭片磊晶生長一第一源極/汲極區域,該第一隔離區域限制該第一源極/汲極區域之該磊晶生長。
- 如請求項8所述之方法,更包含: 形成一閘極密封間隔層在該第一閘極結構之側壁上,該閘極密封間隔層之一第一部分位於該第一隔離區域上,該閘極密封間隔層之該第一部分在該凹陷第一鰭片之一頂表面上方具有一頂表面。
- 如請求項8所述之方法,更包含:形成一第二閘極結構在該第二鰭片上方;使該第二閘極結構外部的該第二鰭片形成凹陷以在該第一隔離區域之一頂表面下方具有一頂表面;以及自該第二閘極結構外部的該凹陷第二鰭片磊晶生長一第二源極/汲極區域。
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- 2016-08-29 CN CN201610750016.3A patent/CN106531806B/zh active Active
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TWI773938B (zh) * | 2018-11-29 | 2022-08-11 | 台灣積體電路製造股份有限公司 | 積體電路裝置及其製造方法 |
US11948971B2 (en) | 2018-11-29 | 2024-04-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Confined source/drain epitaxy regions and method forming same |
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US20210265195A1 (en) | 2021-08-26 |
US20190252240A1 (en) | 2019-08-15 |
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CN106531806A (zh) | 2017-03-22 |
US20180082883A1 (en) | 2018-03-22 |
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CN106531806B (zh) | 2019-08-30 |
US11004724B2 (en) | 2021-05-11 |
TW201711187A (zh) | 2017-03-16 |
US10269618B2 (en) | 2019-04-23 |
US20170076973A1 (en) | 2017-03-16 |
KR101860199B1 (ko) | 2018-05-21 |
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