TW201417301A - 鰭式場效電晶體元件與其製造方法 - Google Patents

鰭式場效電晶體元件與其製造方法 Download PDF

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TW201417301A
TW201417301A TW102134452A TW102134452A TW201417301A TW 201417301 A TW201417301 A TW 201417301A TW 102134452 A TW102134452 A TW 102134452A TW 102134452 A TW102134452 A TW 102134452A TW 201417301 A TW201417301 A TW 201417301A
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sti
shallow trench
region
trench isolation
fin
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Chi-Wen Liu
Chao-Hsiung Wang
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Taiwan Semiconductor Mfg
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    • H01L29/6681—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET using dummy structures having essentially the same shape as the semiconductor body, e.g. to provide stability
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    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/66409—Unipolar field-effect transistors
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    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

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Abstract

本發明提供一種鰭式場效電晶體元件，包括：由一半導體基板所形成的鰭狀構造；一非凹陷化淺溝槽隔離(STI)區域設置於該些鰭狀構造之間；以及一虛設閘極設置於該非凹陷化淺溝槽隔離(STI)區域之上。

Description

鰭式場效電晶體元件與其製造方法
本發明係有關於一種半導體元件，且特別是有關於一種鰭式場效電晶體(FinFET)。
半導體元件應用於大量的電子元件中，例如電腦、行動電話以及其他電子元件。半導體元件包括形成於半導體晶圓上的積體電路，主要是藉由沉積許多種不同類型的材料薄膜於半導體晶圓上，並且圖案化這些材料薄膜，以形成這些積體電路。積體電路包括場效電晶體(field-effect transistors,FETs)，例如金屬氧化物半導體(metal oxide semiconductor,MOS)電晶體。
半導體工業的目標之一為持續縮減個別電晶體(FETs)的尺寸並且提升個別電晶體的速度。為實現此一目標，鰭式場效電晶體(finFETs)或多閘極電晶體(multiple gate transistors)應用於次32奈米電晶體技術節點(sub 32 nm transistor node)。鰭式場效電晶體不僅改善集積密度，同時亦改善通道的閘極控制。
本發明提供一種鰭式場效電晶體元件，包括：由 一半導體基板所形成的鰭狀構造；一非凹陷化淺溝槽隔離(STI)區域設置於該些鰭狀構造之間；以及一虛設閘極設置於該非凹陷化淺溝槽隔離(STI)區域之上。
本發明另提供一種鰭式場效電晶體元件，包括：由一半導體基板所形成的鰭狀構造；一非凹陷化淺溝槽隔離(STI)區域設置在介於該些鰭狀構造之間的位置，且至少一凹陷化淺溝槽隔離(STI)區域形成於與該些鰭狀構造相鄰的位置；一主動閘極形成於每一個該些鰭狀構造之上；以及一虛設閘極形成於該些主動閘極之間並且位於該非凹陷化淺溝槽隔離(STI)區域之上。
本發明又提供一種鰭式場效電晶體元件之製造方法，包括：利用一半導體基板形成鰭狀構造；形成一非凹陷化淺溝槽隔離(STI)區域於該些鰭狀構造之間；以及形成一虛設閘極於該非凹陷化淺溝槽隔離(STI)區域之上。
10‧‧‧鰭式場效電晶體
12‧‧‧鰭狀構造
14‧‧‧基板
16‧‧‧淺溝槽隔離(STI)區域
18‧‧‧鰭狀構造之頂部表面
20‧‧‧主動閘極
22‧‧‧虛設閘極
24‧‧‧缺口
26‧‧‧污染
28‧‧‧鰭式場效電晶體
30‧‧‧鰭狀構造
32‧‧‧半導體基板
34‧‧‧非凹陷化淺溝槽隔離(STI)區域
36‧‧‧凹陷化淺溝槽隔離(STI)區域
37‧‧‧凹陷化淺溝槽隔離(STI)區域之頂部表面
38‧‧‧虛設閘極
40‧‧‧主動閘極
42‧‧‧非凹陷化淺溝槽隔離(STI)區域之頂部表面
44‧‧‧鰭狀構造之頂部表面
46‧‧‧虛設閘極之側壁
48‧‧‧鰭狀構造之側壁
50‧‧‧虛設閘極之頂部表面
52‧‧‧主動閘極之頂部表面
54‧‧‧溝槽
56‧‧‧介電材料
58‧‧‧淺溝槽隔離(STI)區域
60‧‧‧圖案化光阻(PR)
62‧‧‧製造方法
64‧‧‧由半導體基板形成鰭狀構造
66‧‧‧形成非凹陷化淺溝槽隔離(non-recessed STI)區域於鰭狀構造之間
68‧‧‧形成虛設閘極於非凹陷化淺溝槽隔離(STI)區域之上
第1圖為一俯視圖，用以說明習知鰭式場效電晶體(FinFET)。
第2圖為一剖面圖，為沿著第1圖之線2-2所得之剖面圖。
第3圖為一剖面圖，用以說明本發明之鰭式場效電晶體(FinFET)。
第4a-4f圖為一系列剖面圖，用以說明形成第3圖之鰭式場效電晶體(FinFET)之流程圖。
第5圖為第3圖鰭式場效電晶體(FinFET)之製造方法。
本發明揭露之實施例係有關於鰭式場效電晶體金屬氧化物半導體(FinFET metal oxide semiconductor)。然而，本發明亦可應用於其他積體電路、電子結構以及類似之元件。
請參照第1圖到第2圖，其顯示一習知的鰭式場效電晶體10。如圖所顯示，習知的鰭式場效電晶體(FinFET)10包括由一矽基板或一含矽基板14所形成的鰭狀構造12。淺溝槽隔離(shallow trench isolation,STI)區域16形成於相鄰的鰭狀構造12之間。值得注意的是，相對於相鄰鰭狀構造12的頂部表面18，淺溝槽隔離(STI)區域16為凹陷化的區域。
仍請參照第1圖到第2圖，主動閘極(active gates)20形成於鰭狀構造12之上。此外，虛設閘極(dummy gate)22形成於一個凹陷化淺溝槽隔離(STI)區域16之上。如圖所顯示，凹陷化的淺溝槽隔離(STI)區域16形成一介於鰭狀構造12與虛設閘極(dummy gate)22之間的缺口(gap)24，如此一來，製程中不需要的碎片、粒子及污染物26將進入缺口24之中。污染物26將會降低習知鰭式場效電晶體10的效能及可靠度。
請參照第3圖，其顯示鰭式場效電晶體28的實施例。如圖所顯示，鰭式場效電晶體28包括由半導體基板32所形成的鰭狀構造30、一非凹陷化淺溝槽隔離(STI)區域34、凹陷化淺溝槽隔離(STI)區域36、虛設閘極38及主動閘極40。在一實施例中，半導體基板32由下列材料所形成：矽、含矽材料(例如，矽鍺(SiGe)等等)或絕緣層上覆矽(silicon-on-insulator,SOI)基板。
仍請參照第3圖，非凹陷化淺溝槽隔離(STI)區域34設置在介於鰭狀構造30之間的位置。換言之，非凹陷化淺溝槽隔離(STI)區域34嵌入在半導體基板32之中。如圖所顯示，非凹陷化淺溝槽隔離(STI)區域34的頂部表面42與鰭狀構造30的頂部表面44共平面。虛設閘極38的側壁46設置於鰭狀構造30的側壁48上方。在一實施例中，非凹陷化淺溝槽隔離(STI)區域34由下列材料所形成：例如，氧化矽(silicon oxide)、氮化矽(silicon nitride)或其他合適的絕緣材料。
除了非凹陷化淺溝槽隔離(STI)區域34之外，本實施例之鰭式場效電晶體28亦包括凹陷化淺溝槽隔離(STI)區域36。如圖所顯示，凹陷化淺溝槽隔離(STI)區域36形成於半導體基板32之上且相鄰於鰭狀構造30。凹陷化淺溝槽隔離(STI)區域36具有一頂部表面37，其中頂部表面37低於非凹陷化淺溝槽隔離(STI)區域34的頂部表面42與鰭狀構造30的頂部表面44。
如第3圖所示，非凹陷化淺溝槽隔離(STI)區域34支撐著虛設閘極38。相較之下，每一個凹陷化淺溝槽隔離(STI)區域36皆未與虛設閘極38接觸。每一個鰭狀構造30支撐著主動閘極40。如第3圖所描述，在一實施例中，虛設閘極38水平對準於主動閘極40。因此虛設閘極38的頂部表面50與主動閘極40的頂部表面52共平面。
每一個主動閘極40與每一個虛設閘極38可由下列材料所形成：多晶矽(polysilicon)或其他合適的閘極材料。此外，在一實施例中，主動閘極40及/或虛設閘極38可代表一閘極堆疊(gate stack)，其中閘極堆疊可包括其他閘極結構，(例 如介面氧化物層(interfacial oxide layer)、高介電常數值閘極介電層(high-k value gate dielectric layer)及金屬層等等)。第4a圖到第4f圖為一系列的流程圖，用以顯示如第3圖所示之鰭式場效電晶體28的製造方法。如第4a圖所示，溝槽(trenches)54形成於半導體基板32之上，用以定義出鰭狀構造30。溝槽54可藉由，例如，蝕刻製程而形成。接著，如第4b圖所示，介電材料56(例如，氧化矽等等)沉積於溝槽54之中且位於鰭狀構造30之上。介電材料56可藉由，例如，化學氣相沉積(chemical vapor deposition,CVD)製程或其他類似之製程而進行沉積。
接著請參照第4c圖，實施化學機械研磨(chemical-mechanical planarization,CMP)製程以移除介電材料56的頂部部分，並藉以定義出淺溝槽隔離(STI)區域58。接著，在第4d圖中，圖案化光阻(patterning photoresist,PR)60設置於淺溝槽隔離(STI)區域58(亦即，非凹陷化淺溝槽隔離(STI)區域34)之上，其中淺溝槽隔離(STI)區域58介於鰭狀構造30之間。藉由將圖案化光阻(PR)60覆蓋於非凹陷化淺溝槽隔離(STI)區域34之上，可保護非凹陷化淺溝槽隔離(STI)區域34不受到後續製程的影響。
接著請參照第4e圖，實施蝕刻製程或其他製程。實施蝕刻製程以移除介電材料56未受到圖案化光阻(PR)60覆蓋或保護的頂部部分。藉由移除這些介電材料56的頂部部分，可定義出第4e圖中所顯示的凹陷化淺溝槽隔離(STI)區域36。接著，如第4f圖所示，移除圖案化光阻(PR)60。接著，主動閘極40形成於鰭狀構造30之上，且虛設閘極38形成於非凹陷化淺溝 槽隔離(STI)區域34之上。在一實施例中，主動閘極40與虛設閘極38同時形成。如圖所顯示，第3圖中所顯示之鰭式場效電晶體並未包括第2圖中所顯示之鰭式場效電晶體10的缺口24。因此，第3圖中所顯示之鰭式場效電晶體28沒有第2圖中所描述之污染物26。
現在請參照第5圖，其顯示第3圖中所顯示之鰭式場效電晶體的製造方法62。在步驟64中，利用半導體基板32形成鰭狀構造30。在步驟66中，形成非凹陷化淺溝槽隔離(STI)區域34於鰭狀構造30之間。接著，在步驟68中，形成虛設閘極38於非凹陷化淺溝槽隔離(STI)區域34之上。應可理解的是，可實施其他或額外的製程步驟，以完成第3圖中所顯示之鰭式場效電晶體。
依據本發明所揭露之實施例，提供一鰭式場效電晶體元件，包括：由一半導體基板所形成的鰭狀構造、一非凹陷化淺溝槽隔離(STI)區域設置於該些鰭狀構造之間以及一虛設閘極設置於該非凹陷化淺溝槽隔離(STI)區域之上。
依據本發明所揭露之實施例，提供一鰭式場效電晶體元件，包括：由一半導體基板所形成的鰭狀構造、一淺溝槽隔離(STI)區域形成在與該些鰭狀構造相鄰的位置，其中該淺溝槽隔離(STI)區域包括至少一凹陷化部份以及一非凹陷化部份，一主動閘極形成於每一個該些鰭狀構造之上以及一虛設閘極形成於該些主動閘極之間並且位於該非凹陷化淺溝槽隔離(STI)區域之上。
依據本發明所揭露之實施例，提供一鰭式場效電 晶體元件的製造方法，包括：利用一半導體基板形成鰭狀構造、形成一非凹陷化淺溝槽隔離(STI)區域於該些鰭狀構造之間以及形成一虛設閘極於該非凹陷化淺溝槽隔離(STI)區域之上。
18‧‧‧鰭狀構造之頂部表面
20‧‧‧主動閘極
28‧‧‧鰭式場效電晶體
30‧‧‧鰭狀構造
32‧‧‧半導體基板
34‧‧‧非凹陷化淺溝槽隔離(STI)區域
36‧‧‧凹陷化淺溝槽隔離(STI)區域36
37‧‧‧凹陷化淺溝槽隔離(STI)區域之頂部表面
40‧‧‧主動閘極
42‧‧‧非凹陷化淺溝槽隔離(STI)區域之頂部表面
44‧‧‧鰭狀構造之頂部表面
46‧‧‧虛設閘極之側壁
48‧‧‧鰭狀構造之側壁
50‧‧‧虛設閘極之頂部表面
52‧‧‧主動閘極之頂部表面

Claims (10)

  1. 一種鰭式場效電晶體元件，包括：由一半導體基板所形成的鰭狀構造；一非凹陷化淺溝槽隔離(STI)區域設置於該些鰭狀構造之間；以及一虛設閘極設置於該非凹陷化淺溝槽隔離(STI)區域之上。
  2. 如申請專利範圍第1項所述之鰭式場效電晶體元件，其中該非凹陷化淺溝槽隔離(STI)區域的一頂部表面與該些鰭狀構造的一頂部表面共平面。
  3. 如申請專利範圍第1項所述之鰭式場效電晶體元件，尚包括：一主動閘極形成於該些鰭狀構造之上並且與該虛設閘極位於相對的兩側。
  4. 如申請專利範圍第1項所述之鰭式場效電晶體元件，其中一凹陷化淺溝槽隔離(STI)區域形成於該半導體基板之上且相鄰於其中一個該些鰭狀構造。
  5. 如申請專利範圍第1項所述之鰭式場效電晶體元件，其中該虛設閘極的側壁設置於該些鰭狀構造的側壁之上。
  6. 如申請專利範圍第3項所述之鰭式場效電晶體元件，其中該虛設閘極水平對準於位在該些鰭狀構造之上的該主動閘極。
  7. 一種鰭式場效電晶體元件之製造方法，包括：利用一半導體基板形成鰭狀構造；形成一非凹陷化淺溝槽隔離(STI)區域於該些鰭狀構造之 間；以及形成一虛設閘極於該非凹陷化淺溝槽隔離(STI)區域之上。
  8. 如申請專利範圍第7項所述之製造方法，尚包括當形成一凹陷化淺溝槽隔離(STI)區域時，保護該非凹陷化淺溝槽隔離(STI)區域。
  9. 如申請專利範圍第7項所述之製造方法，尚包括在形成一主動閘極於該些鰭狀構造之上的同時形成該虛設閘極於該非凹陷化淺溝槽隔離(STI)區域之上。
  10. 如申請專利範圍第7項所述之製造方法，尚包括於該些鰭狀構造之上相對的兩側形成一凹陷化淺溝槽隔離(STI)區域與非凹陷化淺溝槽隔離(STI)區域。
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