US20090321834A1 - Substrate fins with different heights - Google Patents

Substrate fins with different heights Download PDF

Info

Publication number
US20090321834A1
US20090321834A1 US12215778 US21577808A US20090321834A1 US 20090321834 A1 US20090321834 A1 US 20090321834A1 US 12215778 US12215778 US 12215778 US 21577808 A US21577808 A US 21577808A US 20090321834 A1 US20090321834 A1 US 20090321834A1
Authority
US
Grant status
Application
Patent type
Prior art keywords
height
isolation
layer
regions
mask
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US12215778
Inventor
Willy Rachmady
Justin S. Sandford
Michael K. Harper
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Images

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232Field-effect technology
    • H01L21/8234MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/785Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A device includes a number of fins. Some of the fins have greater heights than other fins. This allows the selection of different drive currents and/or transistor areas.

Description

    BACKGROUND Background of the Invention
  • [0001]
    Multi-gate devices such as transistors may be formed on fin structures. The gate channel “width” of such a multi-gate device may depend at least in part on the height of the fin.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • [0002]
    FIG. 1 is a cross sectional side view that illustrates a plurality of fins of different heights on the same substrate.
  • [0003]
    FIG. 2 is a cross sectional side view that illustrates the substrate.
  • [0004]
    FIG. 3 is a cross sectional side view that illustrates the substrate after isolation regions have been formed.
  • [0005]
    FIG. 4 is a cross sectional side view that illustrates a mask.
  • [0006]
    FIG. 5 is a cross-sectional side view that illustrates the patterned mask layer.
  • [0007]
    FIG. 6 is a cross-sectional side view that illustrates a time part way through an etching process that is used to form the fins.
  • [0008]
    FIG. 7 is a cross-sectional side view that illustrates another time part way through an etching process that is used to form the fins.
  • [0009]
    FIG. 8 is a cross-sectional side view that illustrates patterned mask layers that may be used to form fins having three different heights.
  • [0010]
    FIG. 9 is a cross-sectional side view that illustrates the fins resulting from the two different patterned mask layers illustrated in FIG. 8.
  • [0011]
    FIG. 10 is a cross-sectional side view that illustrates one application to which fins may be put: a multi-gate transistor.
  • [0012]
    FIG. 11 is an isometric view that illustrates the transistor.
  • [0013]
    FIGS. 12 and 13 are block diagrams that illustrate applications in which the above-mentioned NMOS and PMOS transistors may be used.
  • DETAILED DESCRIPTION
  • [0014]
    Various embodiments of a substrate having fins of different heights are discussed in the following description. One skilled in the relevant art will recognize that the various embodiments may be practiced without one or more of the specific details, or with other replacement and/or additional methods, materials, or components. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of various embodiments of the invention. Similarly, for purposes of explanation, specific numbers, materials, and configurations are set forth in order to provide a thorough understanding of the invention. Nevertheless, the invention may be practiced without specific details. Furthermore, it is understood that the various embodiments shown in the figures are illustrative example representations and are not necessarily drawn to scale.
  • [0015]
    Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure, material, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention, but do not denote that they are present in every embodiment. Thus, the appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily referring to the same embodiment of the invention. Furthermore, the particular features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments. Various additional layers and/or structures may be included and/or described features may be omitted in other embodiments.
  • [0016]
    Various operations will be described as multiple discrete operations in turn, in a manner that is most helpful in understanding the invention. However, the order of description should not be construed as to imply that these operations are necessarily order dependent. In particular, these operations need not be performed in the order of presentation. Operations described may be performed in a different order, in series or in parallel, than the described embodiment. Various additional operations may be performed and/or described operations may be omitted in additional embodiments.
  • [0017]
    FIG. 1 is a cross sectional side view that illustrates a plurality of fins 124 of different heights on the same substrate 102, according to one embodiment of the described invention. This substrate 102 may comprise any material that may serve as a foundation upon which a semiconductor device may be built. In one example, substrate 102 comprises silicon, although another material or other materials may be used in other examples. The substrate 102 may be a portion of a bulk substrate, such as a wafer of single crystal silicon, a silicon-on-insulator (SOI) substrate 102 such as a layer of silicon on a layer of insulating material on another layer of silicon, a germanium substrate 102, a group III-V material (such as GaAs, InSb, InAl, etc.) substrate 102, may be a substrate 102 comprising multiple layers, or another type of substrate 102 comprising other material or materials.
  • [0018]
    Fins 124 have been formed on the substrate 102. Rather than all fins 124 having the same height, the fins 124 have differing heights above isolation regions 104. Fins 124A through 124C have a smaller height 120 while fins 124D through 124G have a larger height 122. This difference between heights 120 and 122 is selectable by choosing materials and etchants. In an embodiment, the greater height 122 is selected to be between a height roughly equal to the lower height 120 and a height about twice as great as the lower height 120 (i.e. height 120 is between 99% and 50% of height 122). In another embodiment, the greater height 122 may be more than twice the lower height 120. In an embodiment, the lower height 120 may be between 15-20 nanometers, and the greater height 122 30-40 nanometers, although the invention is not limited to fins 124 within those height ranges.
  • [0019]
    Such an ability to have fins 124 of different height allows multi-gate transistors to be made on the fins 124 with different desired properties. As the drive current of a transistor is dependent on the gate channel “width” of a multi-gate transistor, and the “width” may be made greater by use of a taller fin 124 without increasing the area of the transistor, selectable multi-height fins 124 allow the transistors with the same area to have selected drive currents based on the fin heights. In other embodiments, different areas of transistors may be selected without changing drive currents by selecting the fin heights. Rather than having one selectable parameter, transistor area, with which to affect drive currents, designers may independently select transistor height and area to achieve desired device characteristics.
  • [0020]
    FIGS. 2 through 9 are cross sectional side views that illustrate how fins 124 of different heights on the same substrate 102 may be formed according to one embodiment.
  • [0021]
    FIG. 2 is a cross sectional side view that illustrates the substrate 102. As discussed above, the substrate 102 may comprise any material that may serve as a foundation upon which a semiconductor device may be built.
  • [0022]
    FIG. 3 is a cross sectional side view that illustrates the substrate 102 after isolation regions 104 have been formed. These isolation regions 104 may be, for example, shallow trench isolation regions. Any suitable method for forming isolation regions 104 may be used, and the isolation regions 104 may comprise any suitable material. A suitable isolation region 104 material is one that may be selectively etched while leaving the substrate 102 material substantially intact. In one embodiment, the isolation regions 104 comprise a silicon oxide material and the substrate 102 comprises silicon. Other suitable isolation region materials include, for example, silicon dioxide (which may be deposited in a variety of processes), and spin-on glass (SOG), among others.
  • [0023]
    The formation of the isolation regions 104 also results in pre-fin regions 106 of the substrate 102. These pre-fin regions 106 are between the isolation regions 104.
  • [0024]
    FIG. 4 is a cross sectional side view that illustrates a mask layer 108 formed on the substrate 102, isolation regions 104, and pre-fin regions 106. The mask layer 108 may be formed from a material that has an etch rate in a selected etchant within an order of magnitude of the etch rate of the isolation regions 104 in the selected etchant in one embodiment. In some embodiments, the mask layer 108 has an etch rate faster than the isolation regions 104 in the selected etchant. In some embodiments, the mask layer 108 has an etch rate that is twice the etch rate of the isolation regions 104 or less in the selected etchant. In some embodiments, the mask layer 108 has an etch rate that is one half the etch rate of the isolation regions 104 or more in the selected etchant. In one embodiment, the mask layer 108 comprises a silicon nitride material substantially free from oxygen and carbon. In other embodiments, the mask layer 108 may comprise a silicon nitride material with various amounts of oxygen and/or carbon present to modulate the etch rate, a SiC material, or other materials may also be used.
  • [0025]
    FIG. 5 is a cross-sectional side view that illustrates the patterned mask layer 110. Any suitable method may be used to pattern the mask layer 108 of FIG. 4 to result in the patterned mask layer 110. The patterned mask layer 110 remains over pre-fin regions 106A-106C, to protect them from part of the etching to come. Pre-fin regions 106D-106G are unprotected by the patterned mask layer 110. This will result in pre-fin regions 106A-106C becoming fins 124A-124C having a smaller height 120 than the height of fins 124D-124G that stem from pre-fin regions 106D-106G.
  • [0026]
    FIG. 6 is a cross-sectional side view that illustrates the patterned mask layer 110, the pre-fin regions 106, the isolation regions 104, and the substrate 102 part way through an etching process that is used to form the fins 124. In FIG. 6, part of the patterned mask layer 110 has been removed, leaving remaining partial mask layer 114. Thickness 116 of the patterned mask layer 110 has been removed. Also, a thickness 112 of the isolation regions 104 has been removed at this point in the etching process. The difference between thickness 112 and thickness 116 will depend upon the difference between the etch rates of mask layer 108 and isolation regions 104. In an embodiment where the mask layer 108 comprises a silicon nitride material, the isolation regions 104 comprise a silicon oxide material, and the substrate 102 and pre-fin regions 106 comprise silicon, the etchant chosen may be a hydrofluoric acid (HF). Different etchants and/or different materials may be used, selected based on the desired etchant rate difference between the mask layer 108 and the isolation regions 104, and the etch selectivity to etch the mask layer 108 and isolation regions 104 while leaving the substrate 102 and pre-fin regions 106 substantially intact. For example, spin-on dielectric films such as silicate or siloxane can be used as the mask layer 108 or the isolation regions 104, with HF or buffered HF as the etchant. Other combinations may also be used.
  • [0027]
    FIG. 7 is a cross-sectional side view that illustrates the pre-fin regions 106, the isolation regions 104, and the substrate 102 at another time part way through an etching process that is used to form the fins 124. At the point illustrated in FIG. 7, all of the patterned mask layer 110 has been removed, and the isolation regions 104A-104C formerly protected by the patterned mask layer 110 are about to be etched. At this point, a thickness 118 of isolation regions 104E-104G, plus the portion of isolation region 104D adjacent pre-fin region 106D, have been removed. This thickness 118 sets the height differential (height 122 minus height 120) between the taller fins 124D-124G of FIG. 1, and the shorter fins 124A-124C of FIG. 1 (subject to small variations of the etching process). Thus, the thickness and etch rate of the material of the patterned mask layer 110 is chosen to provide the desired thickness 118, and the desired height differential between the fins 124 of FIG. 1. The etching process will continue after the point illustrated in FIG. 7 to remove portions of isolation regions 104A-104C and more of isolation regions 104D-104G and result in the fins 124 of FIG. 1.
  • [0028]
    FIG. 1, as mentioned above, is a cross sectional side view that illustrates differently-heighted fins 124 resulting from the masking and etching has continued past the point illustrated in FIG. 7 to remove portions of isolation regions 104A-104C, plus the left side of isolation region 104D, to form fins 124A-124C with a desired height 120. This continued etching has also removed more of isolation regions 104E-104G, plus the right side of isolation region 104D, to form fins 124D-124G with desired height 122. The mask layer 108 thickness is chosen based on the desired height differential 118 and the etch rate difference between the material of the mask layer 108 and the material of the isolation regions 104. The etch time is selected to etch through the patterned mask layer 110 and remove portions of isolation regions 104A-104C, plus the left side of isolation region 104D, to result in desired height 120 of fins 124A-124C.
  • [0029]
    FIG. 8 is a cross-sectional side view that illustrates patterned mask layers 126, 128 that may be used to form fins 124 having three different heights. Isolation regions 104F, 104G, and the right side of isolation region 104E are not covered by a mask layer. Patterned mask layer 126 has been patterned to cover isolation regions 104A-104D, plus the left side of isolation region 104E. Patterned mask layer 128 has been patterned to cover isolation regions 104A-104C, plus the left side of isolation region 104D. When an etching process is performed, isolation regions 104F, 104G, and the right side of isolation region 104E will be etched from the start of the process. The right side of isolation region 104D and the left side of isolation region 104E will be etched after a delay caused by time it takes to remove patterned mask layer 126. Finally, the left side of isolation region 104D and isolation regions 104A-104C will be etched after a longer delay caused by the time it takes to remove both patterned mask layer 128 and patterned mask layer 126.
  • [0030]
    FIG. 9 is a cross-sectional side view that illustrates the fins 124 resulting from the two different patterned mask layers 126, 128 illustrated in FIG. 8. Because they were not covered by a mask layer, pre-fin regions 106E-106G became the fins 124E-124G with the greatest height 134. Because it was covered by only one patterned layer 126, pre-fin region 106D became fin 124D with a middle height 132. Because they were covered by two patterned mask layers 126, 128, pre-fin regions 106A-106C became fins 124A-124C with the shortest height 130.
  • [0031]
    The thickness of patterned mask layer 126 is selected based on the desired height differential between fin 124D and fins 124E-124G (i.e. height 134 minus height 132) and the etch rate difference between the material of the mask layer 126 and the material of the isolation regions 104. Similarly, the thickness of patterned mask layer 128 is selected based on the desired height differential between fins 124A-124C and fin 124D (i.e. height 132 minus height 130) and the etch rate difference between the material of the mask layer 128 and the material of the isolation regions 104.
  • [0032]
    Additional mask layers may be used to make yet other differences in the heights of fins 124 on a substrate. More than three different heights may be created. Rather than multiple stacked patterned mask layers 126, 128, there may be a first patterned mask layer with a first thickness covering some pre-fin regions 106, and a second patterned mask layer with a second thickness greater than the first thickness covering different pre-fin regions 106 than those covered by the first patterned mask layer. Alternatively, mask layers with different etch rates in an etchant may be used in place of, or in addition to, different thicknesses. No matter how many different heights are present in the final set of fins 124, the resulting fins 124 may be used in any application calling for such structures.
  • [0033]
    FIG. 10 is a cross-sectional side view that illustrates one application to which fins 124 may be put: a multi-gate transistor 135. The illustrated embodiment of the multi-gate transistor 135 is a tri-gate transistor 135 that includes the fin 124 adjacent the isolation regions 104. There is a gate dielectric layer 136 adjacent the fin 124, and a gate electrode 138 adjacent the gate dielectric layer 136. As the gate electrode 138 is adjacent three sides of the fin 124, the gate channel “width” of the transistor 135 includes the fin 124 width 140 plus twice the fin 124 height 142 (this is why the term channel “width” as used herein has quotations; the “width” is not merely the width of the channel, but also includes other dimensions). As the drive current of the transistor 124 is at least partially dependent on the gate channel “width” of the transistor 135, the drive current may be increased by increasing the height 142 while leaving the other dimensions of the transistor 135 the same.
  • [0034]
    FIG. 11 is an isometric view that illustrates the transistor 135. As mentioned above, because the gate channel “width” is dependent on the height 142 of the fin 124, the drive current of the transistor 135 may be increased without increasing the fin 124 width 140 or the gate depth 144. This means that by increasing the height 142 of the fin 124, the drive current may be increased without the transistor 135 taking up more area. “Area” referring to area within the X-Y plane; note that in FIGS. 1-10, the X-axis goes from left to right in the plane of the picture, the Z-axis is up and down in the plane of the picture, and the Y-axis is normal to the plane of the picture. Thus, using the embodiment illustrated in FIG. 1, fins 124A-124C may be used to make multi-gate transistors 135 with lower drive current and fins 124D-124G used to make multi-gate transistors 135 with higher drive current, with the areas of each of the multi-gate transistors (in the X-Y plane) being substantially the same.
  • [0035]
    One application is to make NMOS (n-type metal oxide semiconductor transistors) and PMOS (p-type metal oxide semiconductor transistors) having substantially the same drive current while being closer in area compared to NMOS and PMOS transistors made on fins having equal heights. A PMOS transistor having the same gate channel “width” as an NMOS transistor will typically have a lower drive current. By increasing the fin 124 height 142 of the PMOS transistor compared to the NMOS transistor on the same substrate 102, the PMOS gate “width” can be increased, and the drive current increased, without increasing the area taken up by the PMOS transistor. Thus, the PMOS and NMOS transistors 135 on a substrate 102 may have substantially the same area and substantially the same drive current.
  • [0036]
    In other embodiments, the PMOS transistor 135 may have substantially the same area as the NMOS transistor 135 and the drive current of the PMOS transistor may be more or less than that of the NMOS transistor by selecting the fin heights of the respective transistor types. Alternatively, both the area and fin height 142 of the PMOS transistor may be selected to each be greater or less than the NMOS transistor based on the desired drive current for some specific circuit requirement and acceptable use of area on the substrate 102.
  • [0037]
    In yet other embodiments, the drive current of multiple instances of a single transistor type (either N- or P-type) may be varied across a single substrate 102 without changing their area by having different fin 124 heights 142. This may be useful, for example, when transistors 135 of the same area are desired (e.g. when design rules that dictate spacing of transistors are based on transistor area) yet different drive currents are desired. The area and height of the fin 124 may each be separately chosen by the device designer to result in a device such as a transistor having the desired drive current and area.
  • [0038]
    FIGS. 12 and 13 are block diagrams that illustrate applications in which the above-mentioned NMOS and PMOS transistors 135 may be used. FIG. 12 includes a die 150 and a memory cell 148 that is part of the die 150. The memory cell 148, which may be, for example, a SRAM cell 148, includes a number of both NMOS and PMOS multi-gate transistors 135. The PMOS transistors 135 have a taller fin 124 than the NMOS transistors 135 so that transistors 135 of both types have substantially the same area and substantially the same drive current. FIG. 13 includes a die 150 and a ring oscillator 152 that is part of the die 150. The ring oscillator 152 includes a number of both NMOS and PMOS multi-gate transistors 135. The PMOS transistors 135 have a taller fin 124 than the NMOS transistors 135 so that transistors 135 of both types have substantially the same area and substantially the same drive current. Numerous other examples of devices and circuits that would benefit from transistors 135 with different height 142 fins 124 are also possible.
  • [0039]
    The foregoing description of the embodiments of the invention has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise forms disclosed. This description and the claims following include terms, such as left, right, top, bottom, over, under, upper, lower, first, second, etc. that are used for descriptive purposes only and are not to be construed as limiting. For example, terms designating relative vertical position refer to a situation where a device side (or active surface) of a substrate or integrated circuit is the “top” surface of that substrate; the substrate may actually be in any orientation so that a “top” side of a substrate may be lower than the “bottom” side in a standard terrestrial frame of reference and still fall within the meaning of the term “top.” The term “on” as used herein (including in the claims) does not indicate that a first layer “on” a second layer is directly on and in immediate contact with the second layer unless such is specifically stated; there may be a third layer or other structure between the first layer and the second layer on the first layer. The embodiments of a device or article described herein can be manufactured, used, or shipped in a number of positions and orientations. Persons skilled in the relevant art can appreciate that many modifications and variations are possible in light of the above teaching. Persons skilled in the art will recognize various equivalent combinations and substitutions for various components shown in the Figures. It is therefore intended that the scope of the invention be limited not by this detailed description, but rather by the claims appended hereto.

Claims (9)

  1. 1-12. (canceled)
  2. 13. A semiconductor device, comprising:
    a substrate;
    a first multi-gate transistor on a first portion of the substrate, the first multi-gate transistor comprising a first fin, the first fin having a first height above a first isolation region; and
    a second multi-gate transistor on a second portion of the substrate, the second multi-gate transistor comprising a second fin, the second fin having a second height above a second isolation region, the second height being greater than the first height.
  3. 14. The device of claim 13, wherein the first multi-gate transistor is an N-type transistor and the second multi-gate transistor is a P-type transistor.
  4. 15. The device of claim 14, further comprising a memory cell, wherein both the first and second multi-gate transistors are transistors of the memory cell.
  5. 16. The device of claim 14, further comprising a ring oscillator, wherein both the first and second multi-gate transistors are transistors of the ring oscillator.
  6. 17. The device of claim 14 wherein the second height is greater than the first height in an amount great enough that the drive current of the first transistor is within 10% of the drive current of the second transistor.
  7. 18. The device of claim 17 wherein first multi-gate transistor has a first area, the second multi-gate transistor has a second area, and the first area is within about 15% of the second area.
  8. 19. The device of claim 13 wherein the second height is at least 25% greater than the first height.
  9. 20. The device of claim 13, further comprising a third multi-gate transistor on a third portion of the substrate, the third multi-gate transistor comprising a third fin, the third fin having a third height above a third isolation region, the third height being greater than the second height.
US12215778 2008-06-30 2008-06-30 Substrate fins with different heights Abandoned US20090321834A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US12215778 US20090321834A1 (en) 2008-06-30 2008-06-30 Substrate fins with different heights

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US12215778 US20090321834A1 (en) 2008-06-30 2008-06-30 Substrate fins with different heights
PCT/US2009/048683 WO2010002702A3 (en) 2008-06-30 2009-06-25 Substrate fins with different heights
US12837321 US8441074B2 (en) 2008-06-30 2010-07-15 Substrate fins with different heights
US13875412 US8629039B2 (en) 2008-06-30 2013-05-02 Substrate fins with different heights

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12837321 Continuation US8441074B2 (en) 2008-06-30 2010-07-15 Substrate fins with different heights

Publications (1)

Publication Number Publication Date
US20090321834A1 true true US20090321834A1 (en) 2009-12-31

Family

ID=41446344

Family Applications (3)

Application Number Title Priority Date Filing Date
US12215778 Abandoned US20090321834A1 (en) 2008-06-30 2008-06-30 Substrate fins with different heights
US12837321 Active US8441074B2 (en) 2008-06-30 2010-07-15 Substrate fins with different heights
US13875412 Active US8629039B2 (en) 2008-06-30 2013-05-02 Substrate fins with different heights

Family Applications After (2)

Application Number Title Priority Date Filing Date
US12837321 Active US8441074B2 (en) 2008-06-30 2010-07-15 Substrate fins with different heights
US13875412 Active US8629039B2 (en) 2008-06-30 2013-05-02 Substrate fins with different heights

Country Status (2)

Country Link
US (3) US20090321834A1 (en)
WO (1) WO2010002702A3 (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2011161338A1 (en) * 2010-06-23 2011-12-29 Commissariat À L'energie Atomique Et Aux Energies Alternatives (Cea) Sram memory cell based on transistors of increased effective gate width and production process
US20130069112A1 (en) * 2011-09-21 2013-03-21 Huilong Zhu Sram cell and method for manufacturing the same
WO2013040833A1 (en) * 2011-09-21 2013-03-28 中国科学院微电子研究所 Sram unit and manufacturing method thereof
US20140239404A1 (en) * 2013-02-27 2014-08-28 Taiwan Semiconductor Manufacturing Company, Ltd. FInFET Structure and Method for Forming the Same
US20150145065A1 (en) * 2013-11-25 2015-05-28 International Business Machines Corporation finFET Isolation by Selective Cyclic Etch
US9196541B2 (en) 2011-09-21 2015-11-24 Institute of Microelectronics, Chinese Academy of Sciences SRAM cell and method for manufacturing the same
US20170069539A1 (en) * 2015-09-04 2017-03-09 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090321834A1 (en) 2008-06-30 2009-12-31 Willy Rachmady Substrate fins with different heights
KR20130096953A (en) * 2012-02-23 2013-09-02 삼성전자주식회사 Method for manufacturing semiconductor device
US9337318B2 (en) * 2012-10-26 2016-05-10 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET with dummy gate on non-recessed shallow trench isolation (STI)
KR20140075849A (en) 2012-11-30 2014-06-20 삼성전자주식회사 Semiconductor device and fabricated method thereof
US8999792B2 (en) 2013-03-15 2015-04-07 Qualcomm Incorporated Fin-type semiconductor device
DE112013006687T5 (en) * 2013-03-28 2015-10-29 Intel Corporation Resonance channel transistor having a plurality of gates
CN105097701B (en) * 2014-04-25 2017-11-03 中芯国际集成电路制造(上海)有限公司 The method of forming a static memory cell
US9324792B1 (en) 2015-03-31 2016-04-26 International Business Machines Corporation FinFET including varied fin height
US9406521B1 (en) * 2015-05-07 2016-08-02 United Microelectronics Corp. Semiconductor device and method for fabricating the same
KR20170000192A (en) 2015-06-23 2017-01-02 삼성전자주식회사 Integrated circuit device and method of manufacturing the same
CN105336766A (en) * 2015-10-22 2016-02-17 上海华虹宏力半导体制造有限公司 Method for locally thinning SOI top layer silicon thickness
US9570580B1 (en) * 2015-10-30 2017-02-14 Taiwan Semiconductor Manufacturing Company, Ltd. Replacement gate process for FinFET
CN105489637A (en) * 2015-11-27 2016-04-13 上海华虹宏力半导体制造有限公司 Forming method of semiconductor structure
US9466702B1 (en) * 2015-12-09 2016-10-11 International Business Machines Corporation Semiconductor device including multiple fin heights
US9716042B1 (en) 2015-12-30 2017-07-25 International Business Machines Corporation Fin field-effect transistor (FinFET) with reduced parasitic capacitance

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040222247A1 (en) * 2003-01-28 2004-11-11 Abel June A. Needlework accessory to protect non-working fabric ends of needlework fabric mounted on a scroll bar or like frame from soil or damage from repeated handling
US20050215014A1 (en) * 2004-03-23 2005-09-29 Young-Joon Ahn Complementary metal oxide semiconductor (CMOS) transistors having three-dimensional channel regions and methods of forming same
US20060081895A1 (en) * 2004-10-19 2006-04-20 Deok-Huyng Lee Semiconductor device having fin transistor and planar transistor and associated methods of manufacture
US7196372B1 (en) * 2003-07-08 2007-03-27 Spansion Llc Flash memory device
US7279997B2 (en) * 2005-10-14 2007-10-09 Freescale Semiconductor, Inc. Voltage controlled oscillator with a multiple gate transistor and method therefor
US20070259501A1 (en) * 2006-05-05 2007-11-08 Texas Instruments Incorporated Integrating high performance and low power multi-gate devices
US20080121998A1 (en) * 2006-09-15 2008-05-29 Kavalieros Jack T Apparatus and method for selectively recessing spacers on multi-gate devices
US20080128797A1 (en) * 2006-11-30 2008-06-05 International Business Machines Corporation Structure and method for multiple height finfet devices
US20080237751A1 (en) * 2007-03-30 2008-10-02 Uday Shah CMOS Structure and method of manufacturing same
US20080265338A1 (en) * 2007-04-27 2008-10-30 Chen-Hua Yu Semiconductor Device Having Multiple Fin Heights

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6909147B2 (en) * 2003-05-05 2005-06-21 International Business Machines Corporation Multi-height FinFETS
US20070257319A1 (en) 2006-05-05 2007-11-08 Texas Instruments Incorporated Integrating high performance and low power multi-gate devices
US7704835B2 (en) 2006-12-29 2010-04-27 Intel Corporation Method of forming a selective spacer in a semiconductor device
US7888750B2 (en) * 2008-02-19 2011-02-15 International Business Machines Corporation Multi-fin multi-gate field effect transistor with tailored drive current
US20090321834A1 (en) 2008-06-30 2009-12-31 Willy Rachmady Substrate fins with different heights

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040222247A1 (en) * 2003-01-28 2004-11-11 Abel June A. Needlework accessory to protect non-working fabric ends of needlework fabric mounted on a scroll bar or like frame from soil or damage from repeated handling
US7196372B1 (en) * 2003-07-08 2007-03-27 Spansion Llc Flash memory device
US20050215014A1 (en) * 2004-03-23 2005-09-29 Young-Joon Ahn Complementary metal oxide semiconductor (CMOS) transistors having three-dimensional channel regions and methods of forming same
US20060081895A1 (en) * 2004-10-19 2006-04-20 Deok-Huyng Lee Semiconductor device having fin transistor and planar transistor and associated methods of manufacture
US7279997B2 (en) * 2005-10-14 2007-10-09 Freescale Semiconductor, Inc. Voltage controlled oscillator with a multiple gate transistor and method therefor
US20070259501A1 (en) * 2006-05-05 2007-11-08 Texas Instruments Incorporated Integrating high performance and low power multi-gate devices
US20080121998A1 (en) * 2006-09-15 2008-05-29 Kavalieros Jack T Apparatus and method for selectively recessing spacers on multi-gate devices
US20080128797A1 (en) * 2006-11-30 2008-06-05 International Business Machines Corporation Structure and method for multiple height finfet devices
US20080237751A1 (en) * 2007-03-30 2008-10-02 Uday Shah CMOS Structure and method of manufacturing same
US20080265338A1 (en) * 2007-04-27 2008-10-30 Chen-Hua Yu Semiconductor Device Having Multiple Fin Heights

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2011161338A1 (en) * 2010-06-23 2011-12-29 Commissariat À L'energie Atomique Et Aux Energies Alternatives (Cea) Sram memory cell based on transistors of increased effective gate width and production process
US20130069112A1 (en) * 2011-09-21 2013-03-21 Huilong Zhu Sram cell and method for manufacturing the same
WO2013040833A1 (en) * 2011-09-21 2013-03-28 中国科学院微电子研究所 Sram unit and manufacturing method thereof
US9196541B2 (en) 2011-09-21 2015-11-24 Institute of Microelectronics, Chinese Academy of Sciences SRAM cell and method for manufacturing the same
US9397104B2 (en) * 2011-09-21 2016-07-19 Institute of Microelectronics, Chinese Academy of Sciences SRAM cell and method for manufacturing the same
US20140239404A1 (en) * 2013-02-27 2014-08-28 Taiwan Semiconductor Manufacturing Company, Ltd. FInFET Structure and Method for Forming the Same
US9318367B2 (en) * 2013-02-27 2016-04-19 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET structure with different fin heights and method for forming the same
US20150145065A1 (en) * 2013-11-25 2015-05-28 International Business Machines Corporation finFET Isolation by Selective Cyclic Etch
US9209178B2 (en) * 2013-11-25 2015-12-08 International Business Machines Corporation finFET isolation by selective cyclic etch
US20170069539A1 (en) * 2015-09-04 2017-03-09 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
US9905467B2 (en) * 2015-09-04 2018-02-27 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and manufacturing method thereof

Also Published As

Publication number Publication date Type
WO2010002702A2 (en) 2010-01-07 application
US20130273710A1 (en) 2013-10-17 application
WO2010002702A3 (en) 2010-04-01 application
US20100276756A1 (en) 2010-11-04 application
US8441074B2 (en) 2013-05-14 grant
US8629039B2 (en) 2014-01-14 grant

Similar Documents

Publication Publication Date Title
US7265059B2 (en) Multiple fin formation
US5804848A (en) Field effect transistor having multiple gate electrodes surrounding the channel region
US7413480B2 (en) Silicon pillars for vertical transistors
US7326634B2 (en) Bulk non-planar transistor having strained enhanced mobility and methods of fabrication
US7410844B2 (en) Device fabrication by anisotropic wet etch
US6709982B1 (en) Double spacer FinFET formation
US6787423B1 (en) Strained-silicon semiconductor device
US20080113483A1 (en) Methods of etching a pattern layer to form staggered heights therein and intermediate semiconductor device structures
US20060202276A1 (en) Semiconductor device and method of making semiconductor devices
US20040241981A1 (en) STRUCTURE AND METHOD TO FABRICATE ULTRA-THIN Si CHANNEL DEVICES
US6204532B1 (en) Pillar transistor incorporating a body contact
US20080230852A1 (en) Fabrication of FinFETs with multiple fin heights
US20120049294A1 (en) Forming Crown Active Regions for FinFETs
US20100164102A1 (en) Isolated germanium nanowire on silicon fin
US20070161171A1 (en) Process for forming an electronic device including a fin-type structure
US20100187503A1 (en) Semiconductor device and manufacturing method thereof
US20140217517A1 (en) Integrated circuits including finfet devices with lower contact resistance and reduced parasitic capacitance and methods for fabricating the same
US20050127362A1 (en) Sectional field effect devices and method of fabrication
US20080128797A1 (en) Structure and method for multiple height finfet devices
US20070072376A1 (en) Strained-induced mobility enhancement nano-device structure and integrated process architecture for CMOS technologies
US8796093B1 (en) Doping of FinFET structures
US7309626B2 (en) Quasi self-aligned source/drain FinFET process
US7208815B2 (en) CMOS logic gate fabricated on hybrid crystal orientations and method of forming thereof
US20080237575A1 (en) Silicon germanium and germanium multigate and nanowire structures for logic and multilevel memory applications
US7224029B2 (en) Method and structure to create multiple device widths in FinFET technology in both bulk and SOI

Legal Events

Date Code Title Description
AS Assignment

Owner name: INTEL CORPORATION,CALIFORNIA

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:RACHMADY, WILLY;SANDFORD, JUSTIN S.;HARPER, MICHAEL K.;SIGNING DATES FROM 20080625 TO 20080627;REEL/FRAME:024519/0374