TWI643258B - 半導體元件與其製造方法 - Google Patents

半導體元件與其製造方法 Download PDF

Info

Publication number
TWI643258B
TWI643258B TW105121610A TW105121610A TWI643258B TW I643258 B TWI643258 B TW I643258B TW 105121610 A TW105121610 A TW 105121610A TW 105121610 A TW105121610 A TW 105121610A TW I643258 B TWI643258 B TW I643258B
Authority
TW
Taiwan
Prior art keywords
fin
semiconductor fins
dummy semiconductor
fins
layer
Prior art date
Application number
TW105121610A
Other languages
English (en)
Other versions
TW201719747A (zh
Inventor
黃鉦謙
劉繼文
曾鴻輝
江宗育
Original Assignee
台灣積體電路製造股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 台灣積體電路製造股份有限公司 filed Critical 台灣積體電路製造股份有限公司
Publication of TW201719747A publication Critical patent/TW201719747A/zh
Application granted granted Critical
Publication of TWI643258B publication Critical patent/TWI643258B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/20—Resistors
    • H01L28/24—Resistors with an active material comprising a refractory, transition or noble metal, metal compound or metal alloy, e.g. silicides, oxides, nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/405—Resistive arrangements, e.g. resistive or semi-insulating field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/6681—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET using dummy structures having essentially the same shape as the semiconductor body, e.g. to provide stability
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66848—Unipolar field-effect transistors with a Schottky gate, i.e. MESFET
    • H01L29/66856—Unipolar field-effect transistors with a Schottky gate, i.e. MESFET with an active layer made of a group 13/15 material
    • H01L29/66863—Lateral single gate transistors
    • H01L29/66871—Processes wherein the final gate is made after the formation of the source and drain regions in the active layer, e.g. dummy-gate processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7855—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with at least two independent gates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823412—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Geometry (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)

Abstract

本案描述一種半導體元件，半導體元件包含鰭式場效電晶體(FinFET)組件、排列在鰭式場效電晶體組件之複數個鰭側面的複數個圖案化虛設半導體鰭、形成於圖案化虛設半導體鰭上之絕緣結構，及形成於圖案化虛設半導體鰭上及電連接至鰭式場效電晶體組件之調諧組件。圖案化虛設半導體鰭的高度小於鰭式場效電晶體組件的鰭之高度。

Description

半導體元件與其製造方法
本揭露是關於一種半導體元件與其製造方法。
半導體積體電路(integrated circuit；IC)工業已經歷指數性增長。IC材料及設計之技術進步已生產數代IC，其中每一代都具有比上一代更小及更複雜的電路。
更小的特徵尺寸是使用多閘極元件，如鰭式場效電晶體(fin field effect transistor；FinFET)元件。鰭式場效電晶體被如此稱呼是因為閘極形成於「鰭」上及周圍，此「鰭」從基板伸出。鰭式場效電晶體元件可容許縮小元件閘寬，同時在鰭之側面及/或頂部上提供閘極，包含通道區域。
本揭露之一實施方式提供了一種半導體元件，包含鰭式場效電晶體組件、複數個圖案化虛設半導體鰭、絕緣組件以及調諧組件。圖案化虛設半導體鰭排列在鰭式場效電晶體組件之複數個鰭的側面，其中圖案化虛設半導體鰭之高度比鰭式場效電晶體組件之鰭之高度短。絕緣結構形成於 圖案化虛設半導體鰭上。調諧組件形成於圖案化虛設半導體鰭上，且電連接至鰭式場效電晶體組件。
本揭露之另一實施方式提供了一種半導體元件，包含基板、形成於基板的複數個虛設半導體鰭上、充填虛設半導體鰭之間的溝槽的絕緣結構，以及組件。虛設半導體鰭形成一凹形頂表面，組件安置在虛設半導體鰭上的組件。
本揭露之又一實施方式提供了一種用於製造半導體元件的方法，該方法包含：在基板上形成複數個半導體鰭及複數個虛設半導體鰭；圖案化虛設半導體鰭，其中圖案化虛設半導體鰭比該些半導體鰭短；在圖案化虛設半導體鰭上形成絕緣結構；形成鰭式場效電晶體組件，鰭式場效電晶體組件包含位於基板上之半導體鰭；以及在絕緣結構上及圖案化虛設半導體鰭上方形成調諧組件。
100‧‧‧半導體元件
200‧‧‧鰭式場效電晶體組件
210‧‧‧基板
212‧‧‧n井區域
216‧‧‧p井區域
222‧‧‧半導體鰭
222c‧‧‧通道部分
222r‧‧‧凹槽部分
224‧‧‧半導體鰭
224c‧‧‧通道部分
224r‧‧‧凹槽部分
226‧‧‧虛設半導體鰭
226'‧‧‧圖案化虛設半導體鰭
230‧‧‧絕緣結構
240‧‧‧虛設閘極
242‧‧‧閘極堆疊
242a‧‧‧閘極絕緣體層
242b‧‧‧閘電極層
244‧‧‧封端層
250‧‧‧閘極隔離層
260‧‧‧介電鰭側壁結構
272‧‧‧磊晶結構
272a‧‧‧頂部部分
272b‧‧‧主體部分
276‧‧‧磊晶結構
276a‧‧‧頂部部分
276b‧‧‧主體部分
280‧‧‧介電層
282‧‧‧接觸蝕刻停止層
284‧‧‧介電層
286‧‧‧介電層
300‧‧‧調諧組件
310‧‧‧高電阻層
320‧‧‧硬質遮罩層
330‧‧‧觸點
閱讀以下詳細敘述並搭配對應之圖式，可了解本揭露之多個樣態。應注意，依據業界中之標凖作法，多個特徵並未按實際比例繪製。實際上，多個特徵之尺寸可任意增加或減少以利於討論的清晰性。
第1圖是依據本揭露案之部分實施例的半導體元件之俯視示意圖。
第2圖至第7圖為依據本揭露案之部分實施例的示意圖，用於以多個步驟製造半導體元件的鰭式場效電晶體組件之方法。
第8圖是本揭露案之部分實施例之鰭式場效電晶體組件之局部透視圖。
第9圖是依據本揭露案之部分實施例之半導體元件之鰭式場效電晶體組件之剖面示意圖。
第10圖至第15圖為依據本揭露案之部分實施例的示意圖，用於製造半導體元件之調諧組件的方法之不同階段。
第16圖是依據本揭露案之部分實施例之半導體元件的調諧組件之橫剖面視圖。
以下揭露內容提供眾多不同的實施例或範例，用於實施本案提供之主要內容的不同特徵。下文中描述一特定範例之組件及配置以簡化本揭露案。此等組件及配置當然僅為範例，且不擬定限制。例如，下文描述「第一特徵形成在第二特徵上方或之上」，於實施例中可包含第一特徵與第二特徵直接接觸，亦可包含第一特徵與第二特徵之間形成額外特徵使得第一特徵與第二特徵無直接接觸之實施例。此外，本揭露案在多個範例中可重複使用元件符號及/或字母。此重複之目的在於簡化與釐清，且其自身並不規定所討論的多個實施例及/或配置之間的關係。
此外，空間相對術語諸如「下方(beneath)」、「以下(below)」、「下部(lower)」、「上方(above)」、「上部(upper)」，在本文中使用以便於描述一個元件或特徵與另一元件或特徵之關係，如圖示中所示。空間相對術語除了描述元件繪製在圖中的方位外，也包含元件在使用中或操作下的不同方位。當裝置經另外配置(旋轉90度或其他方位)，而本案中使用之空間相對描述詞可相應地進行解釋。
第1圖是依據本揭露案之部份實施例之半導體元件之示意性俯視圖。本揭露案之半導體元件100包含鰭式場效電晶體組件200及調諧組件300。鰭式場效電晶體組件200包含複數個鰭及至少一個閘極。鰭具有較高深寬比，且通道及源極/汲極區域形成於鰭中。閘電極橫跨鰭而形成。鰭式場效電晶體組件200可用於記憶體單元中且包含複數個反相器，如交替排列的複數個N型反相器及複數個P型反相器。包含高電阻層之調諧組件300電連接至鰭式場效電晶體組件200以用於調諧鰭式場效電晶體組件200之閾值電壓。
第2圖至第7圖依據本揭露案之部份實施例，圖示用於以多個步驟製造半導體元件的鰭式場效電晶體組件之方法，其中第2圖至第7圖是第1圖中鰭式場效電晶體組件之區域A的局部透視圖。
請參看第2圖。此圖提供基板210。在部份實施例中的基板210，舉例來說，可為半導體材料且可包含已知結構，此等結構包含漸變層或埋入氧化物。在部份實施例中，基板210包含塊體矽，此矽可為未經摻雜或經摻雜(例 如P型、N型，或此兩者之組合)。亦可使用適合於半導體元件形成之其他材料。諸如鍺、石英、藍寶石及玻璃之其他材料可替代地用於基板210。或者，矽基板210可為絕緣體上半導體(semiconductor on insulator；SOI)基板之主動層或諸如形成於塊體矽層上的矽鍺層之多層結構。
複數個p井區域216及複數個n井區域212在基板210中形成。n井區域212中之一者形成於兩個P井區域216之間。p井區域216植入P型摻雜材料，如硼離子，及n井區域212植入N型摻雜材料，如砷離子。在p井區域216之植入期間，用遮罩(如光阻劑)覆蓋n井區域212，而在n井區域212之植入期間，用遮罩(如光阻劑)覆蓋p井區域216。
複數個半導體鰭222、224形成於基板210上。半導體鰭222形成於p井區域216上，及半導體鰭224形成於n井區域212上。在部份實施例中，半導體鰭222、224包含矽。需注意，第2圖中的半導體鰭222、224之數目僅以說明為目的，且將不會限制本揭露案所主張之範疇。此項技術之一般技術者可根據實際情況選擇適合數目之半導體鰭222、224。
半導體鰭222、224，舉例來說，可使用光微影技術而藉由圖案化及蝕刻基板210而形成。在部份實施例中，光阻劑材料層(未圖示)沉積在基板210上方。依據所需形狀(在此情況中為半導體鰭222、224)對光阻劑材料層進行照射(曝露)及顯影以移除光阻劑材料之一部分。殘 餘光阻劑材料保護下層材料以免其接觸諸如蝕刻之後續處理步驟。應注意，諸如氧化物或氮化矽遮罩之其他遮罩亦可用於蝕刻製程。
請參看第3圖。複數個絕緣結構230形成於基板210上。圍繞半導體鰭222、224而充當淺溝槽絕緣(shallow trench isolation；STI)之絕緣結構230可利用四乙氧基矽烷(TEOS)及氧作為前驅物，藉由化學氣相沉積(chemical vapor deposition；CVD)技術而形成。在又部分其他實施例中，絕緣結構230是絕緣體上半導體晶圓之絕緣體層。
請參看第4圖。至少一個虛設閘極240形成於部分半導體鰭222、224之上且曝露半導體鰭222、224之另一部分。虛設閘極240可橫跨多個半導體鰭222、224而形成。
如第4圖中所示，複數個閘極隔離層250形成於基板210上方及沿虛設閘極240側面形成。在部份實施例中，閘極隔離層250可包含氧化矽、氮化矽、氮氧化矽，或其他適合材料。閘極隔離層250可包含單層或多層結構。閘極隔離層250之包覆層可藉由化學氣相沈積、物理氣相沈積(physical vapor deposition；PVD)、原子層沉積(atomic layer deposition；ALD)，或其他適合之技術形成。然後，在包覆層上執行異向性蝕刻以在虛設閘極240兩側形成一對閘極隔離層250。在部份實施例中，閘極隔離層250用以偏移隨後形成之摻雜區域，如源極/汲極區域。隔離層250可進一步用於設計或修正源極/汲極區域(接面)輪廓。
複數個介電鰭側壁結構260形成於半導體鰭222、224之相對側上。介電鰭側壁結構260沿半導體鰭222、224形成。介電鰭側壁結構260可包含介電材料，如氧化矽。或者，介電鰭側壁結構260可包含氮化矽、碳化矽、氮氧化矽，或上述各者之組合。介電鰭側壁結構260之形成方法可包含在半導體鰭222、224上方沉積介電材料，然後異向性地回蝕介電材料。回蝕製程可包含多步驟蝕刻以獲得蝕刻選擇性、彈性及所需的過度蝕刻控制。
在部份實施例中，閘極隔離層250及介電鰭側壁結構260可以相同製程形成。例如，介電層之包覆層可藉由化學氣相沈積、物理氣相沈積、原子層沉積，或其他適合之技術形成以覆蓋虛設閘極240及半導體鰭222、224。然後，在包覆層上執行蝕刻製程以在虛設閘極240相對兩側上形成閘極隔離層250，及在半導體鰭222、224相對兩側上形成介電鰭側壁結構260。然而，在部份其他實施例中，閘極隔離層250及介電鰭側壁結構260可以不同製程形成。
請參看第5圖。曝露於虛設閘極240及閘極間隔層250外之半導體鰭222、224的部分被局部移除(或局部形成凹槽)以在半導體鰭222、224中形成凹槽R。在部份實施例中，形成凹槽R，以介電鰭側壁結構260作為凹槽的上部。在部份實施例中，凹槽R之側壁實質上為垂直且彼此平行。在部份其他實施例中，凹槽R形成不垂直的平行輪廓。
在第5圖中，半導體鰭222包含至少一個凹槽部分222r及至少一個通道部分222c。凹槽R形成於凹槽部分 222r上，而虛設閘極240覆蓋在通道部分222c上。半導體鰭224包含至少一個凹槽部分224r及至少一個通道部分224c。凹槽R形成於凹槽部分224r上，而虛設閘極240覆蓋在通道部分224c上。
介電鰭側壁結構260中至少有一者具有高度H1，而半導體鰭222、224中至少有一者具有從絕緣結構230(亦即通道部分222c、224c)中突出之高度H2。高度H1低於高度H2。在部份實施例中，高度H1及高度H2滿足以下條件：0.1≦(H1/H2)≦0.5，而本案主張範疇並非限定於此。介電鰭側壁結構260之高度H1可藉由例如蝕刻而調控，以調整形成於此等結構上之磊晶結構272及276(請參看第6圖)之輪廓。
凹槽製程可包含乾式蝕刻製程、濕式蝕刻製程，及/或上述各者之組合。凹槽製程亦可包含選擇性濕式蝕刻或選擇性乾式蝕刻。濕式蝕刻溶液包含氫氧化四甲銨(TMAH)、氫氟酸(HF)/硝酸(HNO3)/乙酸(CH3COOH)溶液，或其他適合溶液。乾式及濕式蝕刻製程具有可調節之蝕刻參數，如所使用之蝕刻劑、蝕刻溫度、蝕刻溶液濃度、蝕刻壓力、電源功率、射頻偏壓、射頻偏壓功率、蝕刻劑流速，及其他適合之參數。例如，濕式蝕刻溶液可包含氨水(NH4OH)、氫氧化鉀(KOH)、氫氟酸(HF)、氫氧化四甲銨(TMAH)，其他適合之濕式蝕刻溶液，或上述各者之組合。乾式蝕刻製程包含偏壓電漿蝕刻製程，此製程使用氯基化學品。其他乾式蝕刻劑氣體包含四氟化碳(CF4)、三 氟化氮(NF3)、六氟化硫(SF6)，及氦(He)。亦可藉由使用諸如深度反應離子蝕刻(deep reactive ion etching；DRIE)之機制來執行異向性乾式蝕刻。
請參看第6圖。複數個磊晶結構272分別形成於半導體鰭222的凹槽R中，而複數個磊晶結構276分別形成於半導體鰭224之凹槽R中。磊晶結構272與相鄰磊晶結構276是分離的。磊晶結構272及276自凹槽R突出。磊晶結構272可為N型磊晶結構，而磊晶結構276可為P型磊晶結構。磊晶結構272及276可藉由使用一或更多個磊晶或磊晶(epi)製程而形成，以使得矽特徵、矽鍺特徵，及/或其他適合特徵可以晶態形成於半導體鰭222、224上。在部份實施例中，磊晶結構272及276之晶格常數與半導體鰭222、224之晶格常數不同，且磊晶結構272及276經應變或應力以賦能靜態隨機存取記憶器(SRAM)元件之載子遷移率及增強元件效能。磊晶結構272及276可包含諸如鍺(Ge)或矽(Si)之半導體材料；或諸如砷化鎵(GaAs)、鋁砷化鎵(AlGaAs)、矽鍺(SiGe)、碳化矽(SiC)，或磷砷化鎵(GaAsP)之化合物半導體材料。
在部份實施例中，磊晶結構272及276可由不同磊晶製程而形成。磊晶結構272可包含磷化矽(SiP)、碳化矽(SiC)、碳磷化矽(SiPC)、矽(Si)、第III-V族化合物半導體材料或上述各者之組合，及磊晶結構276可包含矽鍺(SiGe)、矽鍺碳(SiGeC)、鍺(Ge)、矽(Si)、第III-V族化合物半導體材料或上述各者之組合。在磊晶結構272之形成期 間，可隨著磊晶之進行而摻雜諸如磷或砷之N型雜質。例如，當磊晶結構272包含碳化矽(SiC)或矽(Si)時，摻雜物為N型雜質。此外，在磊晶結構276之形成期間，可隨著磊晶之進行而摻雜諸如硼或二氟化硼(BF2)之P型雜質。例如，當磊晶結構276包含矽鍺(SiGe)時，摻雜物為P型雜質。磊晶製程包含化學氣相沉積技術(例如氣相磊晶(vapor-phase epitaxy；VPE)及/或超高真空化學氣相沉積(ultra-high vacuum CVD；UHV-CVD))、分子束磊晶，及/或其他適合製程。磊晶製程可使用氣體前驅物及/或液體前驅物，此等前驅物與半導體鰭222、224之成分(例如矽)反應。由此，受應變的通道可達到增大載子遷移率及增強元件效能。磊晶結構272及276可為臨場摻雜。如若不臨場摻雜磊晶結構272及276，則執行第二植入製程(亦即接面植入製程)以摻雜磊晶結構272及276。可執行一或更多個退火製程以活化磊晶結構272及276。退火過程包含快速熱退火(rapid thermal annealing；RTA)及/或雷射退火製程。
在部份實施例中，磊晶結構272具有頂部部分272a及安置在頂部部分272a與基板210之間的主體部分272b。頂部部分272a的寬度大於主體部分270b的寬度。介電鰭側壁結構260安置在磊晶結構272之主體部分272b的相對兩側，且磊晶結構272的頂部部分272a安置在介電鰭側壁結構260上。
此外，磊晶結構276具有頂部部分276a及安置在頂部部分276a與基板210之間的主體部分276b。頂部部 分276a的寬度大於主體部分276b的寬度。介電鰭側壁結構260安置在磊晶結構276之主體部分276b的相對兩側，且磊晶結構276的頂部部分276a安置在介電鰭側壁結構260上。磊晶結構272及276可用作反相器的源極/汲極區域。
在部份實施例中，磊晶結構272及276具有不同的形狀。磊晶結構272的頂部部分272a，存在於介電鰭側壁結構260上方之此部分可具有至少一個實質上為非刻面(或圓形)之表面，而磊晶結構276的頂部部分276a，存在於介電鰭側壁結構260上方之此部分可具有至少一個刻面之表面，而本案所主張之範疇並非限定於此。
請參看第7圖。在形成磊晶結構272及276之後，移除虛設閘極240並替換為閘極堆疊242。虛設閘極240可由任何適合之蝕刻製程而移除，由此在閘極隔離層250之間形成溝槽。形成閘極堆疊242並充填溝槽。在部份實施例中，閘極堆疊242包含閘極絕緣體層242a及閘電極層242b。閘極絕緣體層242a配置在閘電極層241b與基板210之間，且形成於半導體鰭222、224上。用於阻止電子耗盡之閘極絕緣體層242a可包含例如高介電常數(high-k)介電材料，如金屬氧化物、金屬氮化物、金屬矽酸鹽、過渡金屬氧化物、過渡金屬氮化物、過渡金屬矽酸鹽、金屬氮氧化物、金屬鋁酸鹽、矽酸鋯、鋁酸鋯，或上述各者之組合。部份實施例可包含二氧化鉿(HfO2)、氧化矽鉿(HfSiO)、氮氧化矽鉿(HfSiON)、氧化鉭鉿(HfTaO)、氧化鈦鉿(HfTiO)、氧化鋯鉿(HfZrO)、氧化鑭(LaO)、氧化鋯(ZrO)、氧化鈦 (TiO)、氧化鉭(Ta2O5)、氧化釔(Y2O3)、氧化鈦鍶(SrTiO3、STO)、氧化鈦鋇(BaTiO3、BTO)、氧化鋯鋇(BaZrO)、氧化鑭鉿(HfLaO)、氧化矽鑭(LaSiO)、氧化矽鋁(AlSiO)、氧化鋁(Al2O3)、氮化矽(Si3N4)、氮氧化物(SiON)，及上述各者之組合。閘極絕緣體層242a可具有多層結構，如其中一層為氧化矽(例如界面層)而另一層為高介電常數材料。
閘極絕緣體層242b可藉由使用化學氣相沉積、物理氣相沉積、原子層沉積、熱氧化、臭氧氧化、其他適合製程，或上述各者之組合而形成。閘電極層242b形成於基板210上方以覆蓋閘極絕緣體層242a及半導體鰭222、224之部分。閘電極層242b可以摻雜或未摻雜狀態沉積。例如，在部份實施例中，閘電極層242b包含藉由低壓化學氣相沉積(low pressure chemical vapor deposition；LPCVD)來沉積未摻雜之多晶矽。多晶矽之沉積亦可藉由如臨場摻雜多晶矽之爐管沉積。或者，閘電極層242b可包含金屬，如鎢(W)、鎳(Ni)、鋁(Al)、鉭(Ta)、鈦(Ti)，或上述各者之任何組合。封端層244進一步形成於閘極堆疊242上。
儘管如此，在部份其他實施例中，鰭式場效電晶體組件200可藉由其他適合之製程製造，如第8圖中所示。在第8圖中圖示之鰭式場效電晶體組件200的源極/汲極區域的製造係藉由摻雜半導體鰭222、224而非磊晶結構。
請參看第9圖，依據本揭露案之部份實施例，此圖是半導體元件100的鰭式場效電晶體組件200之剖面示意圖，如第一圖所示，第九圖係沿著9-9線截取。在形成鰭式場效電晶體組件200之後，封端層244形成於閘極堆疊242上以用於保護閘極堆疊242。封端層244可藉由適合之沉積製程而形成。封端層244可為氮化矽層。介電層280進一步形成於鰭式場效電晶體組件200上。介電層280可包含接觸蝕刻停止層282及複數個介電層284、286。包含導通孔及金屬栓塞之複數個觸點進一步形成於介電層280中以用於與鰭式場效電晶體組件200及其他組件互連。觸點中之至少一者電連接至調諧組件。
現請參看第10圖至第15圖。依據本揭露案之部份實施例，第10圖至第15圖圖示用於製造半導體元件100之調諧組件300之方法的不同階段，如第1圖所示，第10圖至第15圖是沿線10-10截取的橫剖面視圖。
請參看第10圖。虛設半導體鰭226形成於基板210上。虛設半導體鰭226可與半導體鰭222、224(如第2圖中所示)一起製造，藉由使用實質上上相同的製程製造而成。虛設半導體鰭226之高度與半導體鰭222、224之高度相同。
請參看第11圖。虛設半導體鰭226中之兩者經圖案化，並形成圖案化虛設半導體鰭226'。複數個虛設半導體鰭226位於圖案化虛設半導體鰭226'之間。
請參看第12圖，經圖案化的虛設半導體鰭226'之間的虛設半導體鰭226亦經圖案化，並形成為一連串經圖案化虛設半導體鰭226'。在虛設半導體鰭226經圖案化之後，圖案化虛設半導體鰭226'之高度減少，因此圖案化虛設半導體鰭226'之間的溝槽深度相應減少。圖案化虛設半導體鰭226'之間的溝槽深寬比減小。
在部份實施例中，圖案化虛設半導體鰭226'或至少部份圖案化虛設半導體鰭226'位於調諧組件下方。或者，圖案化虛設半導體鰭226'位於或至少位於調諧組件下方。虛設半導體鰭226可藉由執行蝕刻製程而圖案化。例如，虛設半導體鰭226可藉由乾式蝕刻製程而圖案化，因此圖案化虛設半導體鰭226'形成凹形頂表面。圖案化虛設半導體鰭226'在圖案化虛設半導體鰭226'中心部分處具有最小高度H3。亦即，圖案化虛設半導體鰭226'比虛設半導體鰭226短，且圖案化虛設半導體鰭226'之中心部分比邊緣部分短。每個圖案化虛設半導體鰭226'之頂表面向中心部分傾斜。在部份實施例中，圖案化虛設半導體鰭226'可為對稱排列。
請參看第13圖。絕緣結構230形成於基板210上且覆蓋圖案化虛設半導體鰭226'。圖案化虛設半導體鰭226'隱藏在絕緣結構230中。絕緣結構230充當淺溝槽絕緣(shallow trench isolation；STI)。絕緣結構230利用四乙氧基矽烷(TEOS)及氧作為前驅物，藉由化學氣相沉積技術而形成。因為圖案化虛設半導體鰭226'之頂部部分已經移除， 相鄰的圖案化虛設半導體鰭226'之間的深寬比小於虛設半導體鰭226之深寬比(請參看第10圖)。因此，絕緣結構230在圖案化虛設半導體鰭226'處之充填比充填虛設半導體鰭226更容易。由此，可防止由於失效充填而產生的問題，及充當淺溝槽絕緣體之絕緣結構230之品質可相應地改善。
請參看第14圖。至少一個介電層280形成於基板210上。介電層280形成於絕緣結構230上。介電層280包含至少一個接觸蝕刻停止層282及至少一個層間介電層284。接觸蝕刻停止層282形成於層間介電層284與絕緣結構230之間。接觸蝕刻停止層282及層間介電層284藉由執行複數個沉積製程而形成。接觸蝕刻停止層282是氮化矽層，及層間介電層284可為氧化層。
請參看第15圖。另一個層間介電層286形成於層間介電層284上。調諧組件300形成於層間介電層286中，及調諧組件300配置在圖案化虛設半導體鰭226'上方。調諧組件包含調諧層310，及形成於高電阻層310上之硬質遮罩層320。調諧層310是高電阻層，如金屬氮化物層。在部份實施例中，調諧層310是氮化鈦層。硬質遮罩層320是氮化物層，如氮化矽層。調諧層310及硬質遮罩層320藉由複數個適合的沉積及蝕刻製程而形成。在部份實施例中，硬質遮罩層320比調諧層310厚。調諧組件300進一步包含複數個觸點330。觸點330穿過層間介電層286及硬質遮罩層320而形成，並連接至調諧層310。觸點330可透過互連結構而電連接至鰭式場效電晶體組件200。調諧組件300至少 電連接至鰭式場效電晶體組件200以調諧半導體元件100之電流及閾值電壓。藉由適當地改變調諧層310之厚度、材料，及尺寸，可調諧半導體元件100的電流及閾值電壓至所需的值。
調諧組件300安置在圖案化虛設半導體鰭226'上方。調諧組件300及圖案化虛設半導體鰭226'為對稱排列，亦即調諧組件300及圖案化虛設半導體鰭226'為同軸。在部份其他實施例中，調諧組件300及圖案化虛設半導體鰭226'為不對稱排列，亦即調諧組件300之軸與圖案化虛設半導體鰭226'之軸之間存在偏移量d，如第16圖中所示。
調諧組件至少電連接至鰭式場效電晶體組件以用於調諧半導體元件之電流及閾值電壓。藉由圖案化調諧組件下方之虛設半導體鰭，鰭間溝槽的深度及深寬比減小。充填介電質而形成絕緣結構變得容易，且可防止失效充填產生的問題。
根據本揭露案之部份實施例，半導體元件包含鰭式場效電晶體組件、排列在鰭式場效電晶體組件之複數個鰭側面的複數個圖案化虛設半導體鰭、形成於圖案化虛設半導體鰭上之絕緣結構，及形成於圖案化虛設半導體鰭上且電連接至鰭式場效電晶體組件之調諧組件。圖案化虛設半導體鰭的高度小於鰭式場效電晶體組件的鰭之高度。
根據本揭露案之部份實施例，半導體元件包含基板、形成於基板上之複數個虛設半導體鰭，其中虛設半導體鰭形成凹形頂表面，充填在虛設半導體鰭之間複數個溝槽的絕緣結構，及配置在虛設半導體鰭上之組件。
根據本揭露案之部份實施例，提供製造半導體元件之一方法。此方法包含：在基板上形成複數個半導體鰭及複數個虛設半導體鰭；將虛設半導體鰭圖案化，使得圖案化虛設半導體鰭比半導體鰭短；在圖案化虛設半導體鰭上形成絕緣結構；形成鰭式場效電晶體組件，此組件包含含基板上之半導體鰭；及在絕緣結構上及圖案化虛設半導體鰭上方形成調諧組件。
前述內容概括數個實施例之特徵，以便彼等熟習此項技術者可更佳地理解本揭露案之樣態。彼等熟習此項技術者應瞭解，可容易的以本揭露案為基礎來設計或調整其他製程或結構，以實現與本案介紹之實施例相同的目的及/或達到與其相同的優勢。彼等熟習此項技術者亦應瞭解，此類等效的構造不脫離本揭露案之精神及範疇，且可在不脫離本揭露案之精神及範疇的情況下進行多種變更、取代及更動。

Claims (10)

  1. 一種半導體元件，包含：一鰭式場效電晶體(FinFET)組件；複數個圖案化虛設半導體鰭，排列在該鰭式場效電晶體組件之複數個鰭的側面，其中該些圖案化虛設半導體鰭之高度比該鰭式場效電晶體組件之該些鰭之高度短，且其中位於一中心部分處之該些圖案化虛設半導體鰭比位於一邊緣部分處之該些圖案化虛設半導體鰭短；一絕緣結構，形成於該些圖案化虛設半導體鰭上；以及一調諧組件，形成於該些圖案化虛設半導體鰭上，及電連接至該鰭式場效電晶體組件。
  2. 如請求項1所述之半導體元件，其中該些圖案化虛設半導體鰭形成一凹形頂表面。
  3. 如請求項1所述之半導體元件，其中該調諧組件包含：一調諧層，形成於該些圖案化虛設半導體鰭上；以及一硬質遮罩層，形成於該調諧層上。
  4. 如請求項3所述之半導體元件，更包含穿透該硬質遮罩層及連接至該調諧組件的複數個觸點。
  5. 如請求項1所述之半導體元件，其中該鰭式場效電晶體組件之每一鰭包含一半導體鰭及形成於該半導體鰭上之一磊晶結構。
  6. 如請求項1所述之半導體元件，其中該鰭式場效電晶體組件包含：一閘極堆疊，橫跨該些鰭；以及一封端層，安置在該閘極堆疊上。
  7. 一種半導體元件，包含：一基板；複數個虛設半導體鰭，形成於該基板上，其中該些虛設半導體鰭形成一凹形頂表面，該些虛設半導體鰭中每一者的一頂表面朝向該些虛設半導體鰭之一中心部分傾斜；一絕緣結構，充填該些虛設半導體鰭之間的複數個溝槽；以及一組件，安置在該些虛設半導體鰭上。
  8. 如請求項7所述之半導體元件，其中該組件包含：一氮化鈦層，形成於該絕緣結構上及該些虛設半導體鰭上方；以及一氮化矽層，形成於該氮化鈦層上。
  9. 一種用於製造一半導體元件的方法，該方法包含以下步驟：在該基板上形成複數個半導體鰭及複數個虛設半導體鰭；圖案化該些虛設半導體鰭，其中該些圖案化虛設半導體鰭比該些半導體鰭短，且其中位於一中心部分處之該些圖案化虛設半導體鰭比位於一邊緣部分處之該些圖案化虛設半導體鰭短；在該些圖案化虛設半導體鰭上形成一絕緣結構；形成一鰭式場效電晶體組件，該鰭式場效電晶體組件組件包含位於該基板上之該些半導體鰭；以及在該絕緣結構上及該些圖案化虛設半導體鰭上方形成一調諧組件。
  10. 如請求項9所述之方法，其中形成該調諧組件之步驟含：在該絕緣結構上及該些圖案化虛設半導體鰭上方形成一調諧層；及在該調諧層上形成一硬質遮罩層。
TW105121610A 2015-09-04 2016-07-07 半導體元件與其製造方法 TWI643258B (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201562214776P 2015-09-04 2015-09-04
US62/214,776 2015-09-04
US14/990,603 2016-01-07
US14/990,603 US10050030B2 (en) 2015-09-04 2016-01-07 Semiconductor device and fabricating method thereof

Publications (2)

Publication Number Publication Date
TW201719747A TW201719747A (zh) 2017-06-01
TWI643258B true TWI643258B (zh) 2018-12-01

Family

ID=58190215

Family Applications (1)

Application Number Title Priority Date Filing Date
TW105121610A TWI643258B (zh) 2015-09-04 2016-07-07 半導體元件與其製造方法

Country Status (4)

Country Link
US (3) US10050030B2 (zh)
KR (1) KR101808941B1 (zh)
CN (1) CN106505097B (zh)
TW (1) TWI643258B (zh)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9722050B2 (en) * 2015-09-04 2017-08-01 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and manufacturing method thereof
CN109216468B (zh) * 2017-06-29 2021-08-13 中芯国际集成电路制造(上海)有限公司 电阻器件及其制造方法
US10510875B2 (en) * 2017-07-31 2019-12-17 Taiwan Semiconductor Manufacturing Co., Ltd. Source and drain structure with reduced contact resistance and enhanced mobility
US10483378B2 (en) * 2017-08-31 2019-11-19 Taiwan Semiconductor Manufacturing Co., Ltd. Epitaxial features confined by dielectric fins and spacers
CN109728088A (zh) * 2017-10-30 2019-05-07 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
KR102535087B1 (ko) * 2018-04-20 2023-05-19 삼성전자주식회사 반도체 장치
US11069692B2 (en) 2018-07-31 2021-07-20 Taiwan Semiconductor Manufacturing Co., Ltd. FinFET SRAM cells with dielectric fins
CN112447708A (zh) * 2019-08-30 2021-03-05 台湾积体电路制造股份有限公司 用于改进的鳍临界尺寸控制的结构和方法
KR20220021159A (ko) 2020-08-13 2022-02-22 삼성전자주식회사 이미지 센서

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130330889A1 (en) * 2012-06-06 2013-12-12 Taiwan Semiconductor Manufacturing Company, Ltd. Method of making a finfet device
TW201417301A (zh) * 2012-10-26 2014-05-01 Taiwan Semiconductor Mfg 鰭式場效電晶體元件與其製造方法
TW201419545A (zh) * 2012-11-09 2014-05-16 Taiwan Semiconductor Mfg 元件與其形成方法
TW201428976A (zh) * 2013-01-14 2014-07-16 Taiwan Semiconductor Mfg 半導體元件與其製造方法

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100620446B1 (ko) * 2004-03-09 2006-09-12 삼성전자주식회사 핀 전계 효과 트랜지스터 및 이의 제조 방법
US7838429B2 (en) * 2007-07-18 2010-11-23 Texas Instruments Incorporated Method to manufacture a thin film resistor
JP2013058688A (ja) * 2011-09-09 2013-03-28 Toshiba Corp 半導体装置の製造方法
KR101908980B1 (ko) * 2012-04-23 2018-10-17 삼성전자주식회사 전계 효과 트랜지스터
US8603893B1 (en) * 2012-05-17 2013-12-10 GlobalFoundries, Inc. Methods for fabricating FinFET integrated circuits on bulk semiconductor substrates
US8796772B2 (en) * 2012-09-24 2014-08-05 Intel Corporation Precision resistor for non-planar semiconductor device architecture
US9515184B2 (en) 2013-09-12 2016-12-06 Taiwan Semiconductor Manufacturing Company Limited Semiconductor arrangement with multiple-height fins and substrate trenches
US9190496B2 (en) 2014-01-23 2015-11-17 Taiwan Semiconductor Manufacturing Company, Ltd. Method of making a FinFET device
US9330971B2 (en) * 2014-03-04 2016-05-03 GlobalFoundries, Inc. Method for fabricating integrated circuits including contacts for metal resistors
US9209172B2 (en) * 2014-05-08 2015-12-08 International Business Machines Corporation FinFET and fin-passive devices
US20150333057A1 (en) * 2014-05-13 2015-11-19 Globalfoundries Inc. Meander resistor
TWI615976B (zh) 2014-07-07 2018-02-21 聯華電子股份有限公司 鰭式場效電晶體及其製造方法
KR102282195B1 (ko) * 2014-07-16 2021-07-27 삼성전자 주식회사 저항 구조체를 갖는 반도체 장치의 제조 방법
CN105374871B (zh) * 2014-08-22 2020-05-19 联华电子股份有限公司 鳍状结构及其形成方法
CN105470293B (zh) * 2014-08-28 2020-06-02 联华电子股份有限公司 半导体元件及其制作方法
TWI612630B (zh) * 2015-01-08 2018-01-21 聯華電子股份有限公司 半導體元件結構
CN105826242B (zh) * 2015-01-08 2019-01-22 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
US9397099B1 (en) * 2015-01-29 2016-07-19 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device having a plurality of fins and method for fabricating the same
CN107026126B (zh) * 2016-02-02 2021-01-26 联华电子股份有限公司 半导体元件及其制作方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130330889A1 (en) * 2012-06-06 2013-12-12 Taiwan Semiconductor Manufacturing Company, Ltd. Method of making a finfet device
TW201417301A (zh) * 2012-10-26 2014-05-01 Taiwan Semiconductor Mfg 鰭式場效電晶體元件與其製造方法
TW201419545A (zh) * 2012-11-09 2014-05-16 Taiwan Semiconductor Mfg 元件與其形成方法
TW201428976A (zh) * 2013-01-14 2014-07-16 Taiwan Semiconductor Mfg 半導體元件與其製造方法

Also Published As

Publication number Publication date
US11018131B2 (en) 2021-05-25
CN106505097A (zh) 2017-03-15
US10050030B2 (en) 2018-08-14
US20170069621A1 (en) 2017-03-09
CN106505097B (zh) 2019-12-03
TW201719747A (zh) 2017-06-01
KR20170028821A (ko) 2017-03-14
KR101808941B1 (ko) 2017-12-13
US20210280575A1 (en) 2021-09-09
US20180342503A1 (en) 2018-11-29

Similar Documents

Publication Publication Date Title
TWI643258B (zh) 半導體元件與其製造方法
CN106505104B (zh) Finfet器件及其制造方法
US10886269B2 (en) Semiconductor device and manufacturing method thereof
US11594534B2 (en) Semiconductor device and manufacturing method thereof
US11043579B2 (en) Method for manufacturing semiconductor device
US11374108B2 (en) Fin semiconductor device having a stepped gate spacer sidewall
US11462534B2 (en) Semiconductor device and manufacturing method thereof
US20220320086A1 (en) Semiconductor device and manufacturing method thereof
US20220069135A1 (en) Epitaxial Features
US20210257361A1 (en) Semiconductor device and manufacturing method thereof
US20220102202A1 (en) Etch profile control of gate contact opening
US10777663B2 (en) Semiconductor device having boron-doped germanium tin epitaxy structure and method for forming the same
US11990524B2 (en) Semiconductor device and forming method thereof
US20230387261A1 (en) Semiconductor device and manufacturing method thereof