TW201419545A - 元件與其形成方法 - Google Patents

元件與其形成方法 Download PDF

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TW201419545A
TW201419545A TW102138609A TW102138609A TW201419545A TW 201419545 A TW201419545 A TW 201419545A TW 102138609 A TW102138609 A TW 102138609A TW 102138609 A TW102138609 A TW 102138609A TW 201419545 A TW201419545 A TW 201419545A
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gate
semiconductor
insulating regions
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TWI542007B (zh
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Kuo-Cheng Ching
Shi-Ning Ju
Guan-Lin Chen
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Taiwan Semiconductor Mfg
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Abstract

本發明提供之元件的形成方法，包括形成多個絕緣區，自半導體基板之上表面延伸至半導體基板中，與形成硬遮罩帶於絕緣區與半導體帶上，其中半導體帶位於兩個相鄰的絕緣區中。形成虛置閘極帶於硬遮罩帶上，其中虛置閘極帶之縱向垂直於半導體帶之縱向，且其中部份虛置閘極帶對準部份半導體帶。上述方法亦包括移除虛置閘極帶，移除硬遮罩帶，以及使絕緣區之第一部份凹陷，且絕緣區之第一部份與被移除的硬遮罩帶重疊。位於凹陷之絕緣區的第一部份之間並與其接觸之部份半導體帶形成半導體鰭狀物。

Description

元件與其形成方法
本發明係關於半導體元件，更特別關於鰭狀場效電晶體(FinFET)。
由於積體電路的尺寸持續縮小且速度持續增加，因此需要更小尺寸與更高驅動電流的電晶體，比如鰭狀場效電晶體(FinFET)。FinFET具有較大的通道寬度，即通道包含半導體鰭狀物之側壁上的部份與半導體鰭狀物之上表面上的部份。由於電晶體的驅動電流與通道寬度成正比，因此FinFET具有較大的驅動電流。
在現有的FinFET製程中，首先形成淺溝槽絕緣(STI)區於矽基板中。接著使STI區凹陷以形成矽鰭狀物，且矽鰭狀物包含凹陷之STI區上的部份矽基板。接著形成閘極介電層、閘極、以及源極與汲極區以完成FinFET。
本發明一實施例提供一種元件的形成方法，包括：形成多個絕緣區，且絕緣區自半導體基板之上表面延伸至半導體基板中；形成硬遮罩帶於絕緣區與半導體帶上，其中半導體帶位於兩個相鄰的絕緣區中；形成虛置閘極帶於硬遮罩帶上，其中虛置閘極帶之縱向垂直於半導體帶之縱向，且其中部份虛置閘極帶對準部份半導體帶；移除虛置閘極帶；移除硬遮 罩帶；以及使絕緣區之第一部份凹陷，且絕緣區之第一部份與被移除的硬遮罩帶重疊，其中位於凹陷之絕緣區的第一部份之間並與其接觸之部份半導體帶形成半導體鰭狀物。
本發明一實施例提供一種元件的形成方法，包括形成硬遮罩層於多個絕緣區與半導體帶上，其中絕緣區自半導體基板之上表面延伸至半導體基板中，且其中半導體帶位於絕緣區之間；形成硬遮罩帶於絕緣區與半導體帶上；形成虛置閘極帶於硬遮罩帶上；進行第一凹陷化製程，使絕緣區之第一部份凹陷，其中第一凹陷化製程的深度為第一凹陷深度，且其中絕緣區之第一部份位於虛置閘極帶之相反兩側上；在進行第一凹陷化製程後，移除虛置閘極帶；移除硬遮罩帶；以及進行第二凹陷化製程，使絕緣區之第二部份凹陷，其中絕緣區之第二部份與被移除的虛置閘極帶重疊，其中第二凹陷化製程的深度為第二凹陷深度，且位於絕緣區的第二部份之間並與其接觸之部份半導體帶形成半導體鰭狀物。
本發明一實施例提供一種元件，包括鰭狀場效電晶體，包括半導體鰭狀物；閘極介電層位於半導體鰭狀物之側壁上；閘極位於閘極介電層上，其中閘極介電層與閘極形成置換閘極；以及閘極間隔物位於閘極介電層與閘極之相反兩側上，其中部份閘極介電層位於閘極與閘極間隔物之間並與其接觸。
8B-8B、8C/8D/8E-8C/8D/8E‧‧‧切線
20‧‧‧基板
21‧‧‧半導體帶
21A‧‧‧鬆馳矽鍺區
21B‧‧‧實質純半導體區
22‧‧‧STI區
22’‧‧‧部份STI區
22A、22A’、22B、48A‧‧‧上表面
24、28‧‧‧硬遮罩層
26‧‧‧多晶矽層
28A‧‧‧氮化矽層
28B‧‧‧氧化矽層
30‧‧‧閘極間隔物
30A‧‧‧第一下表面
30B‧‧‧第二下表面
32、44‧‧‧凹陷
36‧‧‧磊晶區
38‧‧‧金屬矽化區
40‧‧‧ILD
48‧‧‧半導體鰭狀物
50‧‧‧閘極介電層
50A、52A‧‧‧頂部邊緣
52‧‧‧閘極
60‧‧‧FinFET
第1-7、8A-8E、9A-9D圖係本發明多個實施例中，FinFET 之製程透視圖或剖視圖。
下述內容將詳述本發明實施例之製作與應用。然而可以理解的是，這些實施例提供的可行創造概念可以多種特定方式實施。下述的特定實施例僅用以說明而非侷限本發明。
本發明多種實施例提供鰭狀場效電晶體(FinFET)與其形成方法，亦說明FinFET在製程中的臨時結構。下述內容亦包含多種實施例。在圖式與實施例中，將以相同標號標示類似單元。
第1至9D圖係本發明多個實施例中，FinFET之製程透視圖或剖視圖。第1圖為初始結構的透視圖。初始結構包含基板20，其可為半導體基板如矽基板、鍺基板、或由其他半導體材料組成的基板。基板20可掺雜p型或n型雜質。絕緣區如STI(淺溝槽絕緣)區22係形成於基板20中，由基板20之上表面延伸至基板20中。
如第1圖所示，半導體帶21係形成於相鄰的兩STI區22之間並與其接觸。半導體帶21之縱向為Y方向。為清楚說明，第1圖中只有單一半導體帶21，但可採用多個彼此平行的半導體帶21如第3圖所示。在某些實施例中，半導體帶21之材料與基板20之材料相同。舉例來說，半導體帶21與基板20可為矽。在另一實施例中，半導體帶21之材料不同於基板20之材料。在某些實施例中為形成p型FinFET，半導體帶21包含鬆馳矽鍺區21A與其上的實質純半導體(鍺)區21B。在另一實施例中為形成n型MOSFET，半導體帶21包含鬆馳矽鍺區21A與其上的 實質半導體(矽)區21B。在這些實施例中，半導體帶21之形成方法可為蝕刻STI區22之間的部份基板20，再磊晶成長半導體帶21於STI區22之間。
硬遮罩層24係形成於半導體帶21與STI區22上。硬遮罩層24可接觸STI區22與半導體帶21的上表面。在某些實施例中，硬遮罩層24可為氮化矽。在另一實施例中，硬遮罩層24可為氧化矽、碳化矽、金屬氮化物如氮化鈦與氮化鉭、或類似組成。
如第2圖所示，沉積多晶矽層26。在某些實施例中，進行平坦化步驟如研磨或化學機械研磨(CMP)以平坦化多晶矽層26的上表面。接著形成硬遮罩層28於多晶矽層26上。舉例來說，硬遮罩層28可為氮化矽，亦可為其他材料如氧化矽。如第2圖所示的某些實施例中，硬遮罩層28包含氮化矽層28A與其上的氧化矽層28B。
同樣如第2圖所示，圖案化硬遮罩層28。為圖案化硬遮罩層28，可形成光阻(未圖示)後圖案化光阻，再以圖案化光阻作為蝕刻遮罩以圖案化硬遮罩層28，接著移除圖案化光阻。保留的硬遮罩層28又稱為硬遮罩帶。接著以保留的硬遮罩層28作為蝕刻遮罩以蝕刻下方的多晶矽層26，此圖案化步驟可終止於硬遮罩層24上。保留的多晶矽層26又稱為多晶矽帶。保留的多晶矽層26覆蓋半導體帶21的中間部份，其縱向為X方向，且X方向與Y方向垂直。
如第3圖所示，保留的硬遮罩層28係作為選擇性圖案化硬遮罩層24之蝕刻遮罩。第3圖具有兩個半導體帶21。圖 案化硬遮罩層24後將露出某些STI區22與半導體帶21。在圖案化硬遮罩層24後，可進行第一STI凹陷化製程，使STI區22自原本的上表面22A’凹陷至上表面22A。在某些實施例中，未被保留的硬遮罩層28覆蓋的半導體帶21並未凹陷。在某些實施例中，在圖案化硬遮罩層24後，並在凹陷化STI區之前或之後，可移除保留的硬遮罩層28。在另一實施例中，可在進行某些後續步驟後再移除保留的硬遮罩層28。舉例來說，可在形成第6圖所示之ILD(層間介電層)40後，再移除保留的硬遮罩層28。
接著如第3圖所示，閘極間隔物30係形成於保留的硬遮罩層28之側壁上、保留的多晶矽層26上、與某些未凹陷化的STI區22之側壁上。閘極間隔物30之組成為介電材料。閘極間隔物30包含第一下表面30A與第二下表面30B，各自位於STI區22之上表面22A上與半導體帶21之上表面上。由於凹陷的STI區22之上表面22A低於半導體帶21之上表面，第一下表面30A低於第二下表面30B。
如第4圖所示，在形成閘極間隔物30後，以非等向蝕刻使半導體帶21露出的部份凹陷化。在某些實施例中，蝕刻STI區22露出的上表面22A上的部份半導體帶21。蝕刻半導體帶21的方法可持續到半導體帶21之上表面低於STI區22之上表面22A，以形成凹陷32於STI區22中。凹陷32可位於保留的多晶矽層26其相反兩側上。
接著如第5圖所示，自第4圖所示之凹陷32選擇性磊晶成長磊晶區36。在某些實施例中，磊晶區36包含矽鍺化合物或碳矽化合物。在另一實施例中，磊晶區36之組成為矽。在 磊晶區36填滿凹陷32後，後續磊晶成長的磊晶區36會水平延伸，並開始形成晶面。此外，水平成長的磊晶區36將覆蓋STI區22之某些上表面22A。在磊晶步驟後，可掺雜磊晶區36以形成源極區與汲極區。作為源極區與汲極區之磊晶區36分別位於保留的多晶矽層26之相反兩側上，並覆蓋STI區22的部份上表面22A。在形成源極區與汲極區後，可金屬矽化磊晶區36之上方部份以形成金屬矽化區38。在另一實施例中，金屬矽化區38之形成步驟晚於第9A至9D圖之閘極置換步驟。
如第6圖所示，形成ILD 40。在某些實施例中，ILD 40可為含碳氧化物、矽酸鹽玻璃、或其他介電材料。ILD 40的形成步驟可持續到其上表面高於保留的多晶矽層26之上表面，或高於保留的硬遮罩層28之上表面(未圖示於第6圖，請參考第3及4圖)。接著進行CMP以移除多餘的ILD 40。在某些實施例中，保留的多晶矽層26作為CMP停止層，因此ILD 40之上表面與保留的多晶矽層26之上表面等高。在另一實施例中，保留的硬遮罩層28(見第3圖)可作為CMP停止層。若保留的硬遮罩層28作為CMP停止層，在CMP結束後可進行蝕刻步驟以移除保留的硬遮罩層28。
接著如第7圖所示，以蝕刻步驟移除保留的多晶矽層26，以形成凹陷44於相反兩側的閘極間隔物30之間。上述步驟將露出硬遮罩層24。由於保留的多晶矽層26並不存在於最終結構，因此保留的多晶矽層26又稱作虛置多晶矽層。
在移除保留的多晶矽層26後，移除硬遮罩層24以形成第8A圖所示之結構。在移除硬遮罩層24後，進行第二凹陷 化步驟如選擇性蝕刻步驟，使原本被硬遮罩層24覆蓋的部份STI區22凹陷化，並讓凹陷44向下延伸。在此步驟後，STI區22自原本的上表面22A’(見第3圖)凹陷至上表面22B。如此一來，蝕刻步驟讓STI區22具有上表面22B。選擇性蝕刻並未蝕刻半導體帶21，且位於STI區22之上表面22B上的部份半導體帶21可作為半導體鰭狀物48。
第8B圖為8A圖中切線8B-8B之結構剖視圖，並顯示半導體鰭狀物48。
第8C、8D、及8E圖係8A圖中切線8C/8D/8E-8C/8D/8E之結構剖視圖。某些實施例如第8C及8A圖所示，部份STI區22之上表面22B與部份STI區22之上表面22A等高。某些實施例如第8D圖所示，部份STI區22之上表面22B低於部份STI區22之上表面22A。某些實施例如第8E圖所示，部份STI區22之上表面22B高於部份STI區22之上表面22A。在第8E圖中，部份STI區22’位於相反兩側之閘極間隔物30之間，且部份STI區22’之側壁接觸閘極間隔物30的側壁。在第8C、8D、與8E圖中，半導體鰭狀物48之上表面48A以虛線標示，因為半導體鰭狀物48不會出現在第8C、8D及8E圖之剖面中。
如第9A與9B圖所示，形成閘極介電層50與閘極52。第9A圖之剖面結構係沿著第8A圖中的切線8B-8B而來。首先，形成閘極介電層50於第8A圖之凹陷44中與半導體鰭狀物48之上表面與側壁上。在某些實施例中，閘極介電層50可為氧化矽、氮化矽、或上述之多層結構。在另一實施例中，閘極介電層50可為高介電常數之介電材料，其介電常數(k值)大於約 7.0，比如Hf、Al、Zr、La、Mg、Ba、Ti、Pb、或上述組合之氧化物或矽酸鹽。閘極介電層50之形成方法可為分子束沉積(MBD)、原子層沉積(ALD)、物理氣相沉積(PVD)、或類似方法。
接著形成導電材料於閘極介電層50上以填入剩下的凹陷44(請參考第8A圖)中。導電材料可為含金屬的材料如TiN、TaN、TaC、Co、Ru、Al、上述之組合、或上述之多層結構。導電材料可具有能帶邊緣的功函數，端視個別的FinFET為p型FinFET或n型FinFET而定。在形成導電材料後，可進行CMP移除超出ILD 40上表面的多餘閘極介電層50與導電材料。最後保留的導電材料即閘極52，可與閘極介電層50作為FinFET 60中置換後的閘極結構。
在本發明多種實施例中，第9B、9C、及9D圖之剖面結構係沿著第8A圖中的切線8C/8D/8E-8C/8D/8E而來。此外，第9B、9C、與9D圖中的FinFET 60，係由第8C、8D、與8E圖之結構進行後續製程而成。在第9B、9C、與9D圖中，置換閘極製程後的閘極介電層50其頂部邊緣50A與閘極52其頂部邊緣52A等高。在後續製程中，可形成額外ILD(未圖示)於ILD 40上，並形成接觸插塞(未圖示)垂直貫穿額外ILD與其下方之ILD 40，使接觸插塞電性耦接至閘極52與金屬矽化區38(見第6圖)。至此即完成FinFET 60。
在實施例中，FinFET 60具有置換閘極。先形成源極區與汲極區，再凹陷化STI區以形成半導體鰭狀物，則不需在形成輸入/輸出(I/O)元件時另外形成虛置氧化物覆蓋核心FinFET之鰭狀物。如此一來，半導體鰭狀物將不受形成或移除 虛置氧化物的製程損傷。
在最終的FinFET 60中，位於同一閘極52之相反兩側上的不同部份之STI區22，其上表面22A可高於、等於、或低於對準並位於閘極52下方的上表面22B。上述結構與習知的FinFET不同。在習知的FinFET中，位於同一閘極52之相反兩側上的STI區，其上表面與對準並位於閘極下方之STI區之上表面等高。
在實施例中，元件的形成方法包括：形成多個絕緣區，且絕緣區自半導體基板之上表面延伸至該半導體基板中，以及形成硬遮罩帶於絕緣區與半導體帶上，其中半導體帶位於兩個相鄰的絕緣區中。形成虛置閘極帶於硬遮罩帶上，其中虛置閘極帶之縱向垂直於半導體之縱向，且其中部份虛置閘極帶對準部份半導體帶。上述方法亦包括移除虛置閘極帶，移除硬遮罩帶；以及使絕緣區之第一部份凹陷，且絕緣區之第一部份與被移除的硬遮罩帶重疊。位於凹陷之絕緣區的第一部份之間並與其接觸之部份半導體帶形成半導體鰭狀物。
在其他實施例中，元件的形成方法包括形成硬遮罩層於多個絕緣區與半導體帶上，其中絕緣區自半導體基板之上表面延伸至半導體基板中，且其中半導體帶位於絕緣區之間。上述方法更包括形成硬遮罩帶於絕緣區與半導體帶上，形成虛置閘極帶於硬遮罩帶上，以及進行第一凹陷化製程，使絕緣區之第一部份凹陷，其中該第一凹陷化製程的深度為第一凹陷深度。絕緣區之第一部份位於虛置閘極帶之相反兩側上。在進行第一凹陷化製程後，移除虛置閘極帶。接著進行第二凹陷 化製程，使絕緣區之第二部份凹陷，其中絕緣區之第二部份與被移除的虛置閘極帶重疊。第二凹陷化製程的深度為第二凹陷深度，其中位於絕緣區的第二部份之間並與其接觸之部份半導體帶形成半導體鰭狀物。
在其他實施例中，鰭狀場效電晶體包括半導體鰭狀物，閘極介電層位於半導體鰭狀物之側壁上，一閘極位於閘極介電層上，其中閘極介電層與閘極形成置換閘極；以及閘極間隔物位於閘極介電層與閘極之相反兩側上。部份閘極介電層位於該閘極與該閘極間隔物之間並與其接觸。
雖然本發明已以數個較佳實施例揭露如上，然其並非用以限定本發明，任何熟習此技藝者，在不脫離本發明之精神和範圍內，當可作任意之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
20‧‧‧基板
22‧‧‧STI區
22A、22B‧‧‧上表面
30‧‧‧閘極間隔物
40‧‧‧ILD
50‧‧‧閘極介電層
50A、52A‧‧‧頂部邊緣
52‧‧‧閘極
60‧‧‧FinFET

Claims (11)

  1. 一種元件的形成方法，包括：形成多個絕緣區，且該些絕緣區自一半導體基板之上表面延伸至該半導體基板中；形成一硬遮罩帶於該些絕緣區與一半導體帶上，其中該半導體帶位於兩個相鄰的該些絕緣區中；形成一虛置閘極帶於該硬遮罩帶上，其中該虛置閘極帶之縱向垂直於該半導體帶之縱向，且其中部份該虛置閘極帶對準部份該半導體帶；移除該虛置閘極帶；移除該硬遮罩帶；以及使該些絕緣區之第一部份凹陷，且該些絕緣區之第一部份與被移除的該硬遮罩帶重疊，其中位於該些凹陷之絕緣區的第一部份之間並與其接觸之部份該半導體帶形成一半導體鰭狀物。
  2. 如申請專利範圍第1項所述之元件的形成方法，更包括：在移除該虛置閘極帶的步驟前，先使該些絕緣區之第二部份凹陷，且該虛置閘極帶未覆蓋該些絕緣區之第二部份；以及形成一閘極間隔物於該虛置閘極帶之側壁上。
  3. 如申請專利範圍第1項所述之元件的形成方法，更包括：在使該些絕緣區之第一部份凹陷的步驟前，先形成源極與汲極區於該虛置閘極帶的相反兩側上；以及形成層間介電層於該虛置閘極帶的相反兩側上與該源極與 汲極區上，其中形成該源極與汲極區之步驟包括：使部份該半導體帶凹陷；以及進行磊晶成長製程，以形成該源極與汲極區於凹陷的部份該半導體帶中。
  4. 一種元件的形成方法，包括：形成一硬遮罩層於多個絕緣區與一半導體帶上，其中該些絕緣區自一半導體基板之上表面延伸至該半導體基板中，且其中該半導體帶位於該些絕緣區之間；形成一硬遮罩帶於該些絕緣區與該半導體帶上；形成一虛置閘極帶於該硬遮罩帶上；進行一第一凹陷化製程，使該些絕緣區之第一部份凹陷，其中該第一凹陷化製程的深度為第一凹陷深度，且其中該些絕緣區之第一部份位於該虛置閘極帶之相反兩側上；在進行第一凹陷化製程後，移除該虛置閘極帶；移除該硬遮罩帶；以及進行一第二凹陷化製程，使該些絕緣區之第二部份凹陷，其中該些絕緣區之第二部份與被移除的該虛置閘極帶重疊，其中該第二凹陷化製程的深度為第二凹陷深度，且位於該些絕緣區的第二部份之間並與其接觸之部份該半導體帶形成一半導體鰭狀物。
  5. 如申請專利範圍第4項所述之元件的形成方法，更包括：在第一凹陷化製程後並在移除該虛置閘極帶的步驟前，形成一閘極間隔物於該虛置閘極帶之相反兩側的側壁上；以及 形成一源極與汲極區於該虛置閘極帶之相反兩側上，其中該閘極間隔物更位於該硬遮罩帶之側壁與該絕緣區之第二部份的側壁上。
  6. 如申請專利範圍第4項所述之元件的形成方法，其中該第一凹陷化製程之深度大於該第二凹陷化製程的深度。
  7. 如申請專利範圍第4項所述之元件的形成方法，其中該第一凹陷化製程的深度小於該第二凹陷化製程的深度。
  8. 如申請專利範圍第4項所述之元件的形成方法，其中該第一凹陷化製程的深度實質上等於該第二凹陷化製程的深度。
  9. 一種元件，包括：一鰭狀場效電晶體，包括：一半導體鰭狀物；一閘極介電層位於該半導體鰭狀物之側壁上；一閘極位於該閘極介電層上，其中該閘極介電層與該閘極形成一置換閘極；以及一閘極間隔物位於該閘極介電層與該閘極之相反兩側上，其中部份該閘極介電層位於該閘極與該閘極間隔物之間並與其接觸。
  10. 如申請專利範圍第9項所述之元件，更包括多個絕緣區，且該些絕緣區包括：第一部份對準並位於部份該閘極下，其中該半導體鰭狀物位於該些絕緣區之第一部份的第一上表面上；以及第二部份位於部份該閘極之相反兩側上，其中該些絕緣區 之第二部份的第二上表面與該些絕緣區之第一部份的第一上表面等高。
  11. 如申請專利範圍第9項所述之元件，更包括多個絕緣區，且該些絕緣區包括：第一部份對準並位於部份該閘極下，其中該半導體鰭狀物位於該些絕緣區之第一部份的第一上表面上；以及第二部份位於部份該閘極之相反兩側上，其中該些絕緣區之第二部份的第二上表面低於該些絕緣區之第一部份的第一上表面，其中該閘極間隔物包括一第一下表面接觸該些絕緣區之第二部份的上表面，且其中該閘極間隔物包括一第二下表面接觸該半導體鰭狀物的上表面。
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