TW201250838A - Methods for reducing the metal content in the device layer of SOI structures and SOI structures produced by such methods - Google Patents
Methods for reducing the metal content in the device layer of SOI structures and SOI structures produced by such methods Download PDFInfo
- Publication number
- TW201250838A TW201250838A TW101103124A TW101103124A TW201250838A TW 201250838 A TW201250838 A TW 201250838A TW 101103124 A TW101103124 A TW 101103124A TW 101103124 A TW101103124 A TW 101103124A TW 201250838 A TW201250838 A TW 201250838A
- Authority
- TW
- Taiwan
- Prior art keywords
- layer
- metal
- sacrificial oxide
- insulating layer
- interface
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/113—Isolations within a component, i.e. internal isolations
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P36/00—Gettering within semiconductor bodies
- H10P36/03—Gettering within semiconductor bodies within silicon bodies
- H10P36/07—Gettering within semiconductor bodies within silicon bodies of silicon-on-insulator structures
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P70/00—Cleaning of wafers, substrates or parts of devices
- H10P70/10—Cleaning before device manufacture, i.e. Begin-Of-Line process
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
- H10P90/19—Preparing inhomogeneous wafers
- H10P90/1904—Preparing vertically inhomogeneous wafers
- H10P90/1906—Preparing SOI wafers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
- H10P90/19—Preparing inhomogeneous wafers
- H10P90/1904—Preparing vertically inhomogeneous wafers
- H10P90/1906—Preparing SOI wafers
- H10P90/1914—Preparing SOI wafers using bonding
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
- H10W10/10—Isolation regions comprising dielectric materials
- H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P36/00—Gettering within semiconductor bodies
- H10P36/03—Gettering within semiconductor bodies within silicon bodies
Landscapes
- Element Separation (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Weting (AREA)
- Crystals, And After-Treatments Of Crystals (AREA)
- Formation Of Insulating Films (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201161437993P | 2011-01-31 | 2011-01-31 | |
| US13/354,788 US8796116B2 (en) | 2011-01-31 | 2012-01-20 | Methods for reducing the metal content in the device layer of SOI structures and SOI structures produced by such methods |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| TW201250838A true TW201250838A (en) | 2012-12-16 |
Family
ID=46576658
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW101103124A TW201250838A (en) | 2011-01-31 | 2012-01-31 | Methods for reducing the metal content in the device layer of SOI structures and SOI structures produced by such methods |
Country Status (9)
| Country | Link |
|---|---|
| US (3) | US8796116B2 (enExample) |
| EP (1) | EP2671247B1 (enExample) |
| JP (1) | JP5976013B2 (enExample) |
| KR (1) | KR101871534B1 (enExample) |
| CN (1) | CN103339713B (enExample) |
| MY (1) | MY166803A (enExample) |
| SG (1) | SG191966A1 (enExample) |
| TW (1) | TW201250838A (enExample) |
| WO (1) | WO2012106210A2 (enExample) |
Families Citing this family (36)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9064789B2 (en) * | 2013-08-12 | 2015-06-23 | International Business Machines Corporation | Bonded epitaxial oxide structures for compound semiconductor on silicon substrates |
| WO2015112308A1 (en) | 2014-01-23 | 2015-07-30 | Sunedison Semiconductor Limited | High resistivity soi wafers and a method of manufacturing thereof |
| US9853133B2 (en) * | 2014-09-04 | 2017-12-26 | Sunedison Semiconductor Limited (Uen201334164H) | Method of manufacturing high resistivity silicon-on-insulator substrate |
| US9899499B2 (en) | 2014-09-04 | 2018-02-20 | Sunedison Semiconductor Limited (Uen201334164H) | High resistivity silicon-on-insulator wafer manufacturing method for reducing substrate loss |
| US10381260B2 (en) | 2014-11-18 | 2019-08-13 | GlobalWafers Co., Inc. | Method of manufacturing high resistivity semiconductor-on-insulator wafers with charge trapping layers |
| EP3221885B1 (en) | 2014-11-18 | 2019-10-23 | GlobalWafers Co., Ltd. | High resistivity semiconductor-on-insulator wafer and a method of manufacturing |
| US10224233B2 (en) | 2014-11-18 | 2019-03-05 | Globalwafers Co., Ltd. | High resistivity silicon-on-insulator substrate comprising a charge trapping layer formed by He-N2 co-implantation |
| JP6517360B2 (ja) | 2015-03-03 | 2019-05-22 | サンエディソン・セミコンダクター・リミテッドＳｕｎＥｄｉｓｏｎ Ｓｅｍｉｃｏｎｄｕｃｔｏｒ Ｌｉｍｉｔｅｄ | 膜応力を制御可能なシリコン基板の上に電荷トラップ用多結晶シリコン膜を成長させる方法 |
| US9881832B2 (en) | 2015-03-17 | 2018-01-30 | Sunedison Semiconductor Limited (Uen201334164H) | Handle substrate for use in manufacture of semiconductor-on-insulator structure and method of manufacturing thereof |
| JP6637515B2 (ja) | 2015-03-17 | 2020-01-29 | グローバルウェーハズ カンパニー リミテッドＧｌｏｂａｌＷａｆｅｒｓ Ｃｏ．，Ｌｔｄ． | 半導体オン・インシュレータ構造の製造において使用するための熱的に安定した電荷トラップ層 |
| CN114496732B (zh) | 2015-06-01 | 2023-03-03 | 环球晶圆股份有限公司 | 制造绝缘体上硅锗的方法 |
| WO2016196060A1 (en) | 2015-06-01 | 2016-12-08 | Sunedison Semiconductor Limited | A method of manufacturing semiconductor-on-insulator |
| EP3378094B1 (en) | 2015-11-20 | 2021-09-15 | Globalwafers Co., Ltd. | Manufacturing method of smoothing a semiconductor surface |
| US9806025B2 (en) * | 2015-12-29 | 2017-10-31 | Globalfoundries Inc. | SOI wafers with buried dielectric layers to prevent Cu diffusion |
| US10622247B2 (en) | 2016-02-19 | 2020-04-14 | Globalwafers Co., Ltd. | Semiconductor on insulator structure comprising a buried high resistivity layer |
| US9831115B2 (en) | 2016-02-19 | 2017-11-28 | Sunedison Semiconductor Limited (Uen201334164H) | Process flow for manufacturing semiconductor on insulator structures in parallel |
| WO2017142704A1 (en) | 2016-02-19 | 2017-08-24 | Sunedison Semiconductor Limited | High resistivity silicon-on-insulator substrate comprising a charge trapping layer formed on a substrate with a rough surface |
| WO2017155808A1 (en) | 2016-03-07 | 2017-09-14 | Sunedison Semiconductor Limited | Semiconductor on insulator structure comprising a plasma nitride layer and method of manufacture thereof |
| WO2017155804A1 (en) | 2016-03-07 | 2017-09-14 | Sunedison Semiconductor Limited | Method of manufacturing a semiconductor on insulator structure by a pressurized bond treatment |
| EP3758050A1 (en) | 2016-03-07 | 2020-12-30 | GlobalWafers Co., Ltd. | Semiconductor on insulator structure comprising a low temperature flowable oxide layer and method of manufacture thereof |
| US10573550B2 (en) | 2016-03-07 | 2020-02-25 | Globalwafers Co., Ltd. | Semiconductor on insulator structure comprising a plasma oxide layer and method of manufacture thereof |
| EP3995608A1 (en) | 2016-06-08 | 2022-05-11 | GlobalWafers Co., Ltd. | High resistivity single crystal silicon ingot and wafer having improved mechanical strength |
| US10269617B2 (en) | 2016-06-22 | 2019-04-23 | Globalwafers Co., Ltd. | High resistivity silicon-on-insulator substrate comprising an isolation region |
| FR3057705B1 (fr) * | 2016-10-13 | 2019-04-12 | Soitec | Procede de dissolution d'un oxyde enterre dans une plaquette de silicium sur isolant |
| JP6831911B2 (ja) | 2016-10-26 | 2021-02-17 | グローバルウェーハズ カンパニー リミテッドＧｌｏｂａｌＷａｆｅｒｓ Ｃｏ．，Ｌｔｄ． | 向上した電荷捕獲効率を有する高抵抗率シリコンオンインシュレータ基板 |
| JP6801105B2 (ja) | 2016-12-05 | 2020-12-16 | グローバルウェーハズ カンパニー リミテッドＧｌｏｂａｌＷａｆｅｒｓ Ｃｏ．，Ｌｔｄ． | 高抵抗シリコンオンインシュレータ構造及びその製造方法 |
| EP3562978B1 (en) | 2016-12-28 | 2021-03-10 | Sunedison Semiconductor Limited | Method of treating silicon wafers to have intrinsic gettering and gate oxide integrity yield |
| WO2018125673A2 (en) * | 2016-12-28 | 2018-07-05 | Invensas Bonding Technologies, Inc | Processing stacked substrates |
| JP7034186B2 (ja) | 2017-07-14 | 2022-03-11 | サンエディソン・セミコンダクター・リミテッド | 絶縁体上半導体構造の製造方法 |
| CN107946231B (zh) * | 2017-11-22 | 2020-06-16 | 上海华力微电子有限公司 | 一种FDSOI器件SOI和bulk区域浅槽形貌优化方法 |
| US10964664B2 (en) | 2018-04-20 | 2021-03-30 | Invensas Bonding Technologies, Inc. | DBI to Si bonding for simplified handle wafer |
| JP7160943B2 (ja) | 2018-04-27 | 2022-10-25 | グローバルウェーハズ カンパニー リミテッド | 半導体ドナー基板からの層移転を容易にする光アシスト板状体形成 |
| CN112262467B (zh) | 2018-06-08 | 2024-08-09 | 环球晶圆股份有限公司 | 将硅薄层移转的方法 |
| US10943813B2 (en) * | 2018-07-13 | 2021-03-09 | Globalwafers Co., Ltd. | Radio frequency silicon on insulator wafer platform with superior performance, stability, and manufacturability |
| US12525572B2 (en) | 2021-03-31 | 2026-01-13 | Adeia Semiconductor Bonding Technologies Inc. | Direct bonding and debonding of carrier |
| US11798802B2 (en) * | 2022-02-11 | 2023-10-24 | Globalwafers Co., Ltd. | Methods for stripping and cleaning semiconductor structures |
Family Cites Families (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4824698A (en) * | 1987-12-23 | 1989-04-25 | General Electric Company | High temperature annealing to improve SIMOX characteristics |
| JP2617798B2 (ja) | 1989-09-22 | 1997-06-04 | 三菱電機株式会社 | 積層型半導体装置およびその製造方法 |
| JPH07106512A (ja) | 1993-10-04 | 1995-04-21 | Sharp Corp | 分子イオン注入を用いたｓｉｍｏｘ処理方法 |
| US5478758A (en) | 1994-06-03 | 1995-12-26 | At&T Corp. | Method of making a getterer for multi-layer wafers |
| JP3729955B2 (ja) | 1996-01-19 | 2005-12-21 | 株式会社半導体エネルギー研究所 | 半導体装置の作製方法 |
| JPH09260288A (ja) * | 1996-01-19 | 1997-10-03 | Semiconductor Energy Lab Co Ltd | 半導体装置及びその作製方法 |
| US5888858A (en) | 1996-01-20 | 1999-03-30 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and fabrication method thereof |
| US6033974A (en) | 1997-05-12 | 2000-03-07 | Silicon Genesis Corporation | Method for controlled cleaving process |
| US6548382B1 (en) * | 1997-07-18 | 2003-04-15 | Silicon Genesis Corporation | Gettering technique for wafers made using a controlled cleaving process |
| JPH1167778A (ja) * | 1997-08-19 | 1999-03-09 | Sumitomo Metal Ind Ltd | Ｓｏｉ半導体ウエーハの製造方法 |
| US7256104B2 (en) * | 2003-05-21 | 2007-08-14 | Canon Kabushiki Kaisha | Substrate manufacturing method and substrate processing apparatus |
| US7294561B2 (en) | 2003-08-14 | 2007-11-13 | Ibis Technology Corporation | Internal gettering in SIMOX SOI silicon substrates |
| US7084048B2 (en) * | 2004-05-07 | 2006-08-01 | Memc Electronic Materials, Inc. | Process for metallic contamination reduction in silicon wafers |
| EP2078307B1 (en) * | 2006-11-02 | 2015-03-25 | Imec | Removal of impurities from semiconductor device layers |
-
2012
- 2012-01-20 US US13/354,788 patent/US8796116B2/en active Active
- 2012-01-27 CN CN201280007174.XA patent/CN103339713B/zh active Active
- 2012-01-27 WO PCT/US2012/022970 patent/WO2012106210A2/en not_active Ceased
- 2012-01-27 MY MYPI2013002736A patent/MY166803A/en unknown
- 2012-01-27 KR KR1020137020296A patent/KR101871534B1/ko active Active
- 2012-01-27 EP EP12706356.8A patent/EP2671247B1/en active Active
- 2012-01-27 JP JP2013551383A patent/JP5976013B2/ja active Active
- 2012-01-27 SG SG2013053798A patent/SG191966A1/en unknown
- 2012-01-31 TW TW101103124A patent/TW201250838A/zh unknown
-
2013
- 2013-02-08 US US13/762,967 patent/US20130168836A1/en not_active Abandoned
- 2013-02-08 US US13/762,974 patent/US20130168802A1/en not_active Abandoned
Also Published As
| Publication number | Publication date |
|---|---|
| EP2671247A2 (en) | 2013-12-11 |
| JP5976013B2 (ja) | 2016-08-23 |
| US20130168836A1 (en) | 2013-07-04 |
| MY166803A (en) | 2018-07-23 |
| KR20140018872A (ko) | 2014-02-13 |
| KR101871534B1 (ko) | 2018-06-26 |
| CN103339713B (zh) | 2016-06-15 |
| WO2012106210A2 (en) | 2012-08-09 |
| EP2671247B1 (en) | 2015-07-22 |
| CN103339713A (zh) | 2013-10-02 |
| WO2012106210A3 (en) | 2012-11-01 |
| US20120193753A1 (en) | 2012-08-02 |
| JP2014508405A (ja) | 2014-04-03 |
| US8796116B2 (en) | 2014-08-05 |
| US20130168802A1 (en) | 2013-07-04 |
| SG191966A1 (en) | 2013-08-30 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TW201250838A (en) | Methods for reducing the metal content in the device layer of SOI structures and SOI structures produced by such methods | |
| JP6373354B2 (ja) | ライトポイント欠陥と表面粗さを低減するための半導体オンインシュレータウエハの製造方法 | |
| TWI528482B (zh) | 用於在晶圓處理期間監控傳遞至半導體晶圓的汙染物量之方法 | |
| JP2014508405A5 (enExample) | ||
| TWI394204B (zh) | 鍵合晶圓的製造方法 | |
| CN104488080B (zh) | 混合基板的制造方法和混合基板 | |
| JP2004533726A5 (enExample) | ||
| KR20070055955A (ko) | 층전이 웨이퍼의 재생 방법 및 이 방법에 의해 재생된층전이 웨이퍼 | |
| KR20100033414A (ko) | 접합 웨이퍼의 제조 방법 | |
| KR20140121392A (ko) | 접합 soi 웨이퍼의 제조방법 | |
| JP2009283582A (ja) | 貼り合わせウェーハの製造方法及び貼り合わせウェーハ | |
| KR100539465B1 (ko) | 실리콘 박막분리를 위한 표면기포 형성방법 | |
| Vast et al. | A novel method to prepare wafers with very low COPs for bonded SOI.(Materials). | |
| JP2004228139A (ja) | シリコン単結晶基板 |