JP5976013B2 - Ｓｏｉ構造体のデバイス層中の金属含有量の減少方法、およびこのような方法により製造されるｓｏｉ構造体 - Google Patents

Ｓｏｉ構造体のデバイス層中の金属含有量の減少方法、およびこのような方法により製造されるｓｏｉ構造体 Download PDF

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JP5976013B2
JP5976013B2 JP2013551383A JP2013551383A JP5976013B2 JP 5976013 B2 JP5976013 B2 JP 5976013B2 JP 2013551383 A JP2013551383 A JP 2013551383A JP 2013551383 A JP2013551383 A JP 2013551383A JP 5976013 B2 JP5976013 B2 JP 5976013B2
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silicon
device layer
layer
sacrificial oxide
oxide layer
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JP2014508405A5 (enExample
JP2014508405A (ja
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アレクシス・グラッベ
ローレンス・ピー・フラナリー
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SunEdison Inc
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SunEdison Inc
MEMC Electronic Materials Inc
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/113—Isolations within a component, i.e. internal isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P36/00—Gettering within semiconductor bodies
    • H10P36/03—Gettering within semiconductor bodies within silicon bodies
    • H10P36/07—Gettering within semiconductor bodies within silicon bodies of silicon-on-insulator structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P70/00—Cleaning of wafers, substrates or parts of devices
    • H10P70/10—Cleaning before device manufacture, i.e. Begin-Of-Line process
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P36/00—Gettering within semiconductor bodies
    • H10P36/03—Gettering within semiconductor bodies within silicon bodies

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  • Element Separation (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Weting (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Formation Of Insulating Films (AREA)
JP2013551383A 2011-01-31 2012-01-27 Ｓｏｉ構造体のデバイス層中の金属含有量の減少方法、およびこのような方法により製造されるｓｏｉ構造体 Active JP5976013B2 (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201161437993P 2011-01-31 2011-01-31
US61/437,993 2011-01-31
US13/354,788 US8796116B2 (en) 2011-01-31 2012-01-20 Methods for reducing the metal content in the device layer of SOI structures and SOI structures produced by such methods
US13/354,788 2012-01-20
PCT/US2012/022970 WO2012106210A2 (en) 2011-01-31 2012-01-27 Methods for reducing the metal content in the device layer of soi structures and soi structures produced by such methods

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JP2014508405A JP2014508405A (ja) 2014-04-03
JP2014508405A5 JP2014508405A5 (enExample) 2015-02-26
JP5976013B2 true JP5976013B2 (ja) 2016-08-23

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US (3) US8796116B2 (enExample)
EP (1) EP2671247B1 (enExample)
JP (1) JP5976013B2 (enExample)
KR (1) KR101871534B1 (enExample)
CN (1) CN103339713B (enExample)
MY (1) MY166803A (enExample)
SG (1) SG191966A1 (enExample)
TW (1) TW201250838A (enExample)
WO (1) WO2012106210A2 (enExample)

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US9881832B2 (en) 2015-03-17 2018-01-30 Sunedison Semiconductor Limited (Uen201334164H) Handle substrate for use in manufacture of semiconductor-on-insulator structure and method of manufacturing thereof
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US9806025B2 (en) * 2015-12-29 2017-10-31 Globalfoundries Inc. SOI wafers with buried dielectric layers to prevent Cu diffusion
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US9831115B2 (en) 2016-02-19 2017-11-28 Sunedison Semiconductor Limited (Uen201334164H) Process flow for manufacturing semiconductor on insulator structures in parallel
WO2017142704A1 (en) 2016-02-19 2017-08-24 Sunedison Semiconductor Limited High resistivity silicon-on-insulator substrate comprising a charge trapping layer formed on a substrate with a rough surface
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EP3995608A1 (en) 2016-06-08 2022-05-11 GlobalWafers Co., Ltd. High resistivity single crystal silicon ingot and wafer having improved mechanical strength
US10269617B2 (en) 2016-06-22 2019-04-23 Globalwafers Co., Ltd. High resistivity silicon-on-insulator substrate comprising an isolation region
FR3057705B1 (fr) * 2016-10-13 2019-04-12 Soitec Procede de dissolution d'un oxyde enterre dans une plaquette de silicium sur isolant
JP6831911B2 (ja) 2016-10-26 2021-02-17 グローバルウェーハズ カンパニー リミテッドＧｌｏｂａｌＷａｆｅｒｓ Ｃｏ．，Ｌｔｄ． 向上した電荷捕獲効率を有する高抵抗率シリコンオンインシュレータ基板
JP6801105B2 (ja) 2016-12-05 2020-12-16 グローバルウェーハズ カンパニー リミテッドＧｌｏｂａｌＷａｆｅｒｓ Ｃｏ．，Ｌｔｄ． 高抵抗シリコンオンインシュレータ構造及びその製造方法
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EP2671247A2 (en) 2013-12-11
US20130168836A1 (en) 2013-07-04
TW201250838A (en) 2012-12-16
MY166803A (en) 2018-07-23
KR20140018872A (ko) 2014-02-13
KR101871534B1 (ko) 2018-06-26
CN103339713B (zh) 2016-06-15
WO2012106210A2 (en) 2012-08-09
EP2671247B1 (en) 2015-07-22
CN103339713A (zh) 2013-10-02
WO2012106210A3 (en) 2012-11-01
US20120193753A1 (en) 2012-08-02
JP2014508405A (ja) 2014-04-03
US8796116B2 (en) 2014-08-05
US20130168802A1 (en) 2013-07-04
SG191966A1 (en) 2013-08-30

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