SG191966A1 - Methods for reducing the metal content in the device layer of soi structures and soi structures produced by such methods - Google Patents

Methods for reducing the metal content in the device layer of soi structures and soi structures produced by such methods Download PDF

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Publication number
SG191966A1
SG191966A1 SG2013053798A SG2013053798A SG191966A1 SG 191966 A1 SG191966 A1 SG 191966A1 SG 2013053798 A SG2013053798 A SG 2013053798A SG 2013053798 A SG2013053798 A SG 2013053798A SG 191966 A1 SG191966 A1 SG 191966A1
Authority
SG
Singapore
Prior art keywords
silicon
device layer
layer
metal
set forth
Prior art date
Application number
SG2013053798A
Other languages
English (en)
Inventor
Alexis Grabbe
Lawrence P Flannery
Original Assignee
Memc Electronic Materials
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Memc Electronic Materials filed Critical Memc Electronic Materials
Publication of SG191966A1 publication Critical patent/SG191966A1/en

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Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/113Isolations within a component, i.e. internal isolations
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P36/00Gettering within semiconductor bodies
    • H10P36/03Gettering within semiconductor bodies within silicon bodies
    • H10P36/07Gettering within semiconductor bodies within silicon bodies of silicon-on-insulator structures
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P70/00Cleaning of wafers, substrates or parts of devices
    • H10P70/10Cleaning before device manufacture, i.e. Begin-Of-Line process
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19Preparing inhomogeneous wafers
    • H10P90/1904Preparing vertically inhomogeneous wafers
    • H10P90/1906Preparing SOI wafers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19Preparing inhomogeneous wafers
    • H10P90/1904Preparing vertically inhomogeneous wafers
    • H10P90/1906Preparing SOI wafers
    • H10P90/1914Preparing SOI wafers using bonding
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10Isolation regions comprising dielectric materials
    • H10W10/181Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P36/00Gettering within semiconductor bodies
    • H10P36/03Gettering within semiconductor bodies within silicon bodies

Landscapes

  • Element Separation (AREA)
  • Weting (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
SG2013053798A 2011-01-31 2012-01-27 Methods for reducing the metal content in the device layer of soi structures and soi structures produced by such methods SG191966A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US201161437993P 2011-01-31 2011-01-31
US13/354,788 US8796116B2 (en) 2011-01-31 2012-01-20 Methods for reducing the metal content in the device layer of SOI structures and SOI structures produced by such methods
PCT/US2012/022970 WO2012106210A2 (en) 2011-01-31 2012-01-27 Methods for reducing the metal content in the device layer of soi structures and soi structures produced by such methods

Publications (1)

Publication Number Publication Date
SG191966A1 true SG191966A1 (en) 2013-08-30

Family

ID=46576658

Family Applications (1)

Application Number Title Priority Date Filing Date
SG2013053798A SG191966A1 (en) 2011-01-31 2012-01-27 Methods for reducing the metal content in the device layer of soi structures and soi structures produced by such methods

Country Status (9)

Country Link
US (3) US8796116B2 (enExample)
EP (1) EP2671247B1 (enExample)
JP (1) JP5976013B2 (enExample)
KR (1) KR101871534B1 (enExample)
CN (1) CN103339713B (enExample)
MY (1) MY166803A (enExample)
SG (1) SG191966A1 (enExample)
TW (1) TW201250838A (enExample)
WO (1) WO2012106210A2 (enExample)

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US9899499B2 (en) 2014-09-04 2018-02-20 Sunedison Semiconductor Limited (Uen201334164H) High resistivity silicon-on-insulator wafer manufacturing method for reducing substrate loss
US9853133B2 (en) * 2014-09-04 2017-12-26 Sunedison Semiconductor Limited (Uen201334164H) Method of manufacturing high resistivity silicon-on-insulator substrate
EP3221885B1 (en) 2014-11-18 2019-10-23 GlobalWafers Co., Ltd. High resistivity semiconductor-on-insulator wafer and a method of manufacturing
US10381260B2 (en) 2014-11-18 2019-08-13 GlobalWafers Co., Inc. Method of manufacturing high resistivity semiconductor-on-insulator wafers with charge trapping layers
US10224233B2 (en) 2014-11-18 2019-03-05 Globalwafers Co., Ltd. High resistivity silicon-on-insulator substrate comprising a charge trapping layer formed by He-N2 co-implantation
EP3266038B1 (en) 2015-03-03 2019-09-25 GlobalWafers Co., Ltd. Method of depositing charge trapping polycrystalline silicon films on silicon substrates with controllable film stress
WO2016149113A1 (en) 2015-03-17 2016-09-22 Sunedison Semiconductor Limited Thermally stable charge trapping layer for use in manufacture of semiconductor-on-insulator structures
US9881832B2 (en) 2015-03-17 2018-01-30 Sunedison Semiconductor Limited (Uen201334164H) Handle substrate for use in manufacture of semiconductor-on-insulator structure and method of manufacturing thereof
US10304722B2 (en) 2015-06-01 2019-05-28 Globalwafers Co., Ltd. Method of manufacturing semiconductor-on-insulator
CN114496732B (zh) 2015-06-01 2023-03-03 环球晶圆股份有限公司 制造绝缘体上硅锗的方法
JP6749394B2 (ja) * 2015-11-20 2020-09-02 グローバルウェーハズ カンパニー リミテッドGlobalWafers Co.,Ltd. 滑らかな半導体表面の製造方法
US9806025B2 (en) * 2015-12-29 2017-10-31 Globalfoundries Inc. SOI wafers with buried dielectric layers to prevent Cu diffusion
US9831115B2 (en) 2016-02-19 2017-11-28 Sunedison Semiconductor Limited (Uen201334164H) Process flow for manufacturing semiconductor on insulator structures in parallel
US10622247B2 (en) 2016-02-19 2020-04-14 Globalwafers Co., Ltd. Semiconductor on insulator structure comprising a buried high resistivity layer
US10468294B2 (en) 2016-02-19 2019-11-05 Globalwafers Co., Ltd. High resistivity silicon-on-insulator substrate comprising a charge trapping layer formed on a substrate with a rough surface
WO2017155806A1 (en) 2016-03-07 2017-09-14 Sunedison Semiconductor Limited Semiconductor on insulator structure comprising a plasma oxide layer and method of manufacture thereof
SG11201806851RA (en) 2016-03-07 2018-09-27 Globalwafers Co Ltd Semiconductor on insulator structure comprising a low temperature flowable oxide layer and method of manufacture thereof
US11114332B2 (en) 2016-03-07 2021-09-07 Globalwafers Co., Ltd. Semiconductor on insulator structure comprising a plasma nitride layer and method of manufacture thereof
US11848227B2 (en) 2016-03-07 2023-12-19 Globalwafers Co., Ltd. Method of manufacturing a semiconductor on insulator structure by a pressurized bond treatment
KR102439602B1 (ko) 2016-06-08 2022-09-01 글로벌웨이퍼스 씨오., 엘티디. 높은 비저항의 단결정 실리콘 잉곳 및 개선된 기계적 강도를 갖는 웨이퍼
US10269617B2 (en) 2016-06-22 2019-04-23 Globalwafers Co., Ltd. High resistivity silicon-on-insulator substrate comprising an isolation region
FR3057705B1 (fr) * 2016-10-13 2019-04-12 Soitec Procede de dissolution d'un oxyde enterre dans une plaquette de silicium sur isolant
EP4456146B1 (en) 2016-10-26 2026-03-25 GlobalWafers Co., Ltd. High resistivity silicon-on-insulator substrate having enhanced charge trapping efficiency
SG10201913059PA (en) 2016-12-05 2020-02-27 Globalwafers Co Ltd High resistivity silicon-on-insulator structure and method of manufacture thereof
CN117878055A (zh) 2016-12-28 2024-04-12 艾德亚半导体接合科技有限公司 堆栈基板的处理
KR102453743B1 (ko) 2016-12-28 2022-10-11 썬에디슨 세미컨덕터 리미티드 고유 게터링 및 게이트 산화물 무결성 수율을 갖도록 규소 웨이퍼들을 처리하는 방법
SG10201913850VA (en) 2017-07-14 2020-03-30 Sunedison Semiconductor Ltd Method of manufacture of a semiconductor on insulator structure
CN107946231B (zh) * 2017-11-22 2020-06-16 上海华力微电子有限公司 一种FDSOI器件SOI和bulk区域浅槽形貌优化方法
US10964664B2 (en) 2018-04-20 2021-03-30 Invensas Bonding Technologies, Inc. DBI to Si bonding for simplified handle wafer
EP3785293B1 (en) 2018-04-27 2023-06-07 GlobalWafers Co., Ltd. Light assisted platelet formation facilitating layer transfer from a semiconductor donor substrate
CN118943075A (zh) 2018-06-08 2024-11-12 环球晶圆股份有限公司 将硅薄层移转的方法
US10943813B2 (en) * 2018-07-13 2021-03-09 Globalwafers Co., Ltd. Radio frequency silicon on insulator wafer platform with superior performance, stability, and manufacturability
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Also Published As

Publication number Publication date
JP2014508405A (ja) 2014-04-03
US20130168836A1 (en) 2013-07-04
KR20140018872A (ko) 2014-02-13
US20130168802A1 (en) 2013-07-04
CN103339713B (zh) 2016-06-15
MY166803A (en) 2018-07-23
US20120193753A1 (en) 2012-08-02
EP2671247B1 (en) 2015-07-22
TW201250838A (en) 2012-12-16
EP2671247A2 (en) 2013-12-11
JP5976013B2 (ja) 2016-08-23
KR101871534B1 (ko) 2018-06-26
WO2012106210A2 (en) 2012-08-09
US8796116B2 (en) 2014-08-05
CN103339713A (zh) 2013-10-02
WO2012106210A3 (en) 2012-11-01

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