TW201209963A - Metal-contamination-free through-substrate via structure - Google Patents

Metal-contamination-free through-substrate via structure Download PDF

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Publication number
TW201209963A
TW201209963A TW100124663A TW100124663A TW201209963A TW 201209963 A TW201209963 A TW 201209963A TW 100124663 A TW100124663 A TW 100124663A TW 100124663 A TW100124663 A TW 100124663A TW 201209963 A TW201209963 A TW 201209963A
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Taiwan
Prior art keywords
diffusion barrier
metal
dielectric
semiconductor
layer
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TW100124663A
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English (en)
Inventor
Mukta G Farooq
Robert Hannon
Richard P Volant
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Ibm
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Application filed by Ibm filed Critical Ibm
Publication of TW201209963A publication Critical patent/TW201209963A/zh

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Description

201209963 六、發明說明： 【發明所屬之技術領域】 本揭示案係關於半導體結構之領域，且特定言之，本 揭示案係關於無金屬污染之貫穿基板的通孔結構及製造 該無金屬污染之貫穿基板的通孔結構之方法。 【先前技術】 近年來，建礅使用「三維矽」（three dimensi⑼al siHe⑽; 3DSi)結構以使多個矽晶片及/或晶圓能夠接合，該多個矽 曰曰片及/或晶圓安裝於封裝板或系統板上。3〇8丨結構採用 導電通孔結構，該等導電通孔結構稱為「貫穿基板之通 孔」結構或「TSV」結構，該等導電通孔結構提供貫穿半 導體晶片之基板之電氣連接。TSV結構增大整合於給定空 間中之有效電路之密度。此種3Dsi結構採用貫穿基板之 通孔（TSVs)’以在多個矽晶片及/或晶圓間提供電氣連接。 通常，習知TSV結構採用銅通孔結構，該銅通孔結構延 伸貫穿半導體晶片之基板。由氧化矽介電質襯裡將銅通 孔結構與基板橫向地電氣隔離。氧化矽介電質襯裡並無 法防止金屬材料擴散穿過。因此，在銅通孔結構嵌入端 之化學機械樾光期間產生之剩餘銅材料，可塗抹於氧化 矽介電質襯裡之終端面上，且隨後該剩餘銅材料擴散穿 過氧化矽介電質襯裡且進入基板内之半導體材料中。此 種剩餘銅材料擴散至半導體材料中可造成不良影響，諸 如造成基板中半導體元件内之電氣短路。 201209963 【發明内容】 兹提供-種利用背面平坦化製程生產的抗金屬污染貫 穿基板之通孔(TSV)結構。在形成貫穿基板之通孔(TSV) 溝槽後’在該TSV溝槽之侧壁上共形地沈積擴散阻障概 裡。藉由在該擴冑阻障襯裡之垂直部分上沈積介電材 料，來形成介電質襯裡。隨後，藉由填充該Tsv溝槽，來 形成金屬導電通孔結構。在沈積用於該金屬導電通孔結 構之導電材料之刖，可藉由各向異性蚀刻來移除該擴散 阻障襯裡之水平部分，或在移除該介電質襯裡之水平部 分後，可藉由平坦化移除該擴散阻障襯裡之該水平部 分。在該背側平坦化期間’藉由阻斷源自該金屬導電通 孔結構之剩餘金屬材料進入該基板之半導體材料，該擴 散阻障襯裡保護該基板之該半導體材料，進而保護該基 板内之半導體元件免受金屬污染。 根據本揭示案之一態樣，提供了半導體結構，該半導 體結構包括一半導體基板及—貫穿基板之通孔（Tsv)結 構，該貝穿基板之通孔結構嵌設於該半導體基板中。該 TSV結構包括：-擴散阻障襯裡，該擴散阻障襯裡接觸相 連側壁之整體，該側壁圍繞該半導體基板内之孔；一介 電質襯裡，該介電質襯裡接觸擴散阻障襯裡之内側壁； 以及一金屬導電通孔結構，該金屬導電通孔結構橫向地 接觸該介電質襯裡。 201209963 根據本揭示案之另一態樣，提供了一種形成半導體結 構之方法。該方法包括以下步驟：在半導體基板之第一 表面上形成至少—個半導體元件；在該半導體基板中形 成溝槽’其中該半導體基板之半導體材料暴露於該溝槽 之側壁處；在該側壁上直接形成擴散阻障襯裡；藉由用 導電填充材料填充該溝槽，形成金屬導電通孔結構；以 及使該半導體基板變薄，其中在該基板變薄之後，該金 屬導電通孔結構至少自該半導體基板之該第一表面延伸 至該半導體基板之第二表面，其中該第二表面位於該第 一表面之相對侧。 【實施方式】 如上所述，本揭示案係關於無金屬污染之貫穿基板的 通孔結構及製造無金屬污染之貫穿基板的通孔結構之方 法’現參照附圖進行詳細描述。貫穿諸圖式，相同的元 件符號或字母用以代表相似或均等元件。諸圖式未必按 比例繪製。 如本文所用’「導電貫穿基板之通孔(TSV)結構」為延 伸穿過基板之導電結構，亦即，至少自基板之頂面延伸 至基板之底面。 如本文所用’若表面意欲為平坦的，且表面之非平坦 性受用以形成表面的處理步驟中时缺陷所限制， 面為「大體上平坦的 201209963 如本文所用，文裝結構」為任一結構，而半導體晶片 可藉由電氣連接安裝至此結構。安裝結構可為封^基 板、插入結構或另一半導體晶片。 土 如本文所用，右在第一元件與第二元件之間存在電氣 導電路徑’則該第一元件「導電性地連接」至該第二元 件0 參見第1圖’根據本揭示案之第一實施例之第一示例性 半導體結構包括半導體基板1G。半導體基板ig包括半導 體材料，該半導體材料可選自（但不限於）：❾錯、石夕 錯合金、⑦碳合金、㈣碳合金、_化鎵、石t化姻填 化銦、III-V族化合物半導體材料、11¥1族化合物半導體 材料、有機半導體材料及其他化合物半導體材料。半導 體基板10可為塊狀基板、絕緣體上半導體 (SemiC〇ndUct〇r-on_insulat〇r; s〇I)基板或混合基板該混 合基板具有塊狀部分及S0I部分。半導體基板1〇中至少上 部包括半導體材料區，在該半導體材料區中至少具有一 個半導體元件12’諸如電晶體、二極體、電容器、感應 器及/或電阻器，採用本領域中之已知方法。 在半導體基板10之正面11上形成下互連層結構。正面 II為半導體基板之表面，至少—個半導體元件^位於該 半導體基板之表面上《正面U之至少一部分包括半導體 材料。下互連層結構包括下互連層介電層及下互連層導 電結構，該等下互連層導電結構嵌設於該等下互連層介 電層甲。作為一說明性實例，下互連層介電層可包括第 201209963 一下互連層介電層20、第二下互連層介電層30及第三下 互連層介電層40。下互連層導電結構可包括：第一下互 連層通孔結構22及第一下互連層線結構24，該第一下互 連層通孔結構22及第一下互連層線結構24嵌設於第一下 互連層介電層20中；第二下互連層通孔結構32及第二下 互連層線結構34’該第二下互連層通孔結構32及第二下 互連層線結構34嵌設於第二下互連層介電層3〇中；以及 第三下互連層通孔結構42及第三下互連層線結構44，該 第三下互連層通孔結構42及第三下互連層線結構44嵌設 於第三下互連層介電層40中。下互連層介電層（2〇、3〇、 4〇)可包括介電材料，諸如有機矽酸鹽玻璃（〇rgan〇siHcate glass; OSG)、未摻雜的矽酸鹽玻璃（und〇ped smcate “a叫 USG)、摻雜的矽酸鹽玻璃、氮化矽或用作後段製程介電 材料之任何其他已知的介電材料 (22 ' 24 ' 32 > 34 > 42 ' 44^»r>fe,rj^ 。下互連層導電結構 24 、 32 、 34 、 42 、
44)可例如為 Cu、Al、Ag、Ti、 Co WP及/或上述金屬的組合或 合金。將下互連層結構（20、3〇、4〇、22、24、32、Μ 42、44)之最頂層表面平坦化。 參見第2A圖及第2B圖 在下互連層結構（20、30、40 30、40、
(例如，第三下 9 201209963 互連層介電層4〇)之介電材料。若遮罩層ο為硬遮罩層， 則光阻層（未圖示）可塗覆於遮罩層47之頂面且光刻圖 案化該光阻層，且光阻層中之圖案可轉移至硬遮罩層中 以提供圖案化的遮罩層47。若遮罩層47為光阻層，則可 藉由光刻曝光及顯像圖案化光阻層。 隨後，遮罩層47中之圖案藉由各向異性银刻轉移至下 互連層結構（20、30、40、22、24、32、34、42、44)及半 導體基板ίο之上部中，以形成至少_個溝槽49。每—溝 槽49之橫截面形狀可具有（但並非必須具有）如第则 t所示之環形。半導體基板1G之半導體材料暴露於至少 一個溝槽49之側壁處。自半導體基板1〇之正面n量測的 至少一個溝槽49之深度J可為20微米至2〇〇微米且通常 為40微米至100微米，但亦可採用更小及更大的深度。至 少-個溝槽49之橫向尺寸，亦即，至少一個溝槽49中之 一個溝槽49之兩個不同側壁之間的最小橫向距離，可為2 微米至20微米，且通常為4微米至1〇微米，但亦可採用更 小及更大的橫向尺寸。例如，在溝槽49之水平橫截面區 為環狀之狀況中，彼溝槽49之橫向尺寸可為外侧壁半^ 與内側壁半徑之間的差，且溝槽49之橫向尺寸可為續: 至20微米，且通常為4微米至1〇微米。溝槽49之環形僅為 說明性實例，且溝槽49可具有任何水平橫截面形狀，前 提為在沈積本揭^案之龍後，可能在隨後處理步驟中 用導電材料來填充溝槽49。隨後，相對於下互連層結構 201209963 (20、30、40、22、24、32、34、42、44)之暴露介電材料’ 遮罩層47被選擇性地移除。 參見第3圖，在至少一個溝槽49之底面及側壁以及下互 連層結構（20、30、40、22、24、32、34、42、44)之最頂
層表面上沈積相連擴散阻障層48L。相連擴散阻障層48L 相連地覆蓋第一示例性半導體結構中之所有表面及至少 一個溝槽49之側壁表面。 在一個實施例中，相連擴散阻障層48L包括導電材料。 相連擴散阻障層48L可由單一同質導電材料組成，或相連 擴散阻障層48L可包括複數個導電材料層，該等導電材料 層具有不同組合物。具體而言’相連擴散阻障層48l之導 電材料可包括至少一種導電金屬氮化物。用於導電金屬 氮化物之非限制示例性材料包括TiN、TaN、WN、TiAIN 及TaCN。替代或另外地’相連擴散阻障層斗此之導電材 料可包括元素金屬’該元素金屬不會擴散至半導體材料 中。此種元素金屬包括Ta、Ti、W及Mo。然而，替代或 另外地’相連擴散阻障層48L之導電材料可包括可電鍍材 料’該可電鍍材料可選自CoW合金及CoWP合金。相連擴 散阻障層48L之導電材料作用如金屬材料之擴散阻障，亦 即’阻斷金屬材料擴散至半導體基板10之半導體材料中。 可藉由化學氣相沈積（chemical vapor deposition; CVD)、原子層沈積（at〇mic iayer deposition; ALD)、蒸 發、物理氣相沈積（physical vapor deposition; PVD » 亦 即’濺射）、電鍍、無電電鍍或上述方法之組合，將各種 11 201209963 導電材料沈積為相連層，該等導電㈣可作為相連擴散 阻障層48L的唯一成分導電層或作為相連擴散阻障層4儿 中多成分導電層中之一種成分。相連擴散阻障層4让中之 每一導電成分層之厚度可為1奈米至1〇〇奈米。相連擴散 阻障層48L之總厚度可為5奈米至1〇〇奈米，但亦可採用更 小及更大的厚度。 在另一實施例中，相連擴散阻障層48L包括介電材料。 相連擴散阻障層48L可由單一同質介電材料組成，或相連 擴散阻障層48L可包括複數個介電材料層，料介電材料 層具有不同組合物。具體而言，相連擴散阻障層48l之介 電材料可包括含金屬氧化物之介電材料。詩含金屬氧 化物介電材料之非限制示例性材料包括下述令之至少一 種材料：Hf〇2、Zr〇2、La2〇3、Al2〇3、Ti〇2、SrTi〇3、LaA1〇3、 Y2〇3、HfOxNy、Zr〇xNy、La2〇為、Ah〇為、加為、 hTi(DxNy、LaA1〇xNy、γ2〇χ、、上述化合物之矽酸鹽及 上述化合物之合金、以及上述化合物之非化學計量變 體’其中X中之每-數值獨立地為約〇 5至約3，且y中之每 一數值獨立地為0至約2。替代或另外地，相連擴散阻障 層48L之介電材料可包括選自碳化矽及札中之至 ;一種材料’其中x、y&z中之每-數值獨立地為。至約 1。然而，替代或另外地，相連擴散阻障層48L之介電材 料可包括氮切。相連擴散阻障層48L之介電材料作用如 金屬材料之擴散阻障，亦即，阻斷金屬材料擴散至半導 體基板10之半導體材料中。 12 201209963 可藉由化學氣相沈積（CVD)、原子層沈積（Ald)、噴射 塗佈或上述方法之組合’將各種介電材料沈積為相連 層’該等介電材料可作為相連擴散阻障層48L的唯一成分 介電層或相連擴散阻障層4 8L中許多成分介電層中之— 種成匀。沈積SiNxCyHz之方法為本領域所知，其中X、y 及z中之每一數值獨立地為〇至約1，且例如可在Angy ^等 人之美國專利第7,009,280號中發現沈積siNxCyHz之方 法。關於沈積SiNxCyHzi ’ 280專利案之内容以引用方式 併入本文。相連擴散阻障層48L中之每一介電成分層之厚 度可為5奈米至200奈米《相連擴散阻障層48L之總厚度可 為5奈米至1〇〇奈米，但亦可使用更小及更大的厚度。 在又一實施例中，相連擴散阻障層48L包括至少一個介 電材料層及至少一個導電材料層之組合。介電材料及導 電材料可獨立地用於相連擴散阻障層48L，介電材料及導 電材料亦可組合地用於相連擴散阻障層48L。相連擴散阻 障層48L之總厚度可為5奈米至1〇〇奈米，但亦可採用更小 及更大的厚度。 參見第4圖，藉由各向異性蝕刻移除相連擴散阻障層 48L之水平部分，該各向異性餘刻可為活性離子银刻，該 活性離子㈣相對於下互連層結構（2()、川、利、Μ、Μ、 32、34、42、44)之頂面上之材料，選擇性地移除相連擴 散阻障層48L之-或多種材料。相連擴散阻障層肌之剩 餘垂直部分組成擴散阻障襯裡48 ’該擴散阻障襯裡48僅 存在於至少一個溝槽49之側壁上。在各向異性蝕刻後， 13 201209963 暴露至少一個溝槽49之底面。在一說明性實例中，溝槽 49具有環形，在溝槽49之側壁上形成一對擴散阻障襯= 4 8，亦即’内擴散阻障層及外擴散阻障層。 在下互連層結構（20、30、40、22、24、32、34、42、 44)之最頂層表面、擴散阻障襯裡48之内側壁及至少一個 溝槽49之底面上連續地直接沈積介電質襯裡5〇ν。介電質 概裡50V包括介電材料’諸如未摻雜的矽酸鹽玻璃 (USG)、摻雜的矽酸鹽玻璃、有機矽酸鹽玻璃或上述材料 之組合。介電質襯裡50V促進了隨後形成於至少一個溝槽 49内之金屬導電通孔結構之黏附性。自擴散阻障襯裡心 之内側壁水平量測的介電質襯裡5〇v之厚度可為5〇奈米 至1微米，且通常為150奈米至500奈米，但亦可採用更小 及更大的厚度。介電質襯裡50V可藉由例如化學氣相沈積 (CVD)的方式來沈積。 參見第5圖，藉由用導電材料填充至少一個溝槽的，來 在至少一個溝槽49之每一溝槽49中形成金屬導電通孔結 構51。例如，可藉由電鍍、無電電鍍、物理氣相沈積、 化學氣相沈積或上述方法之組合，來沈積導電材料。藉 由平坦化製程移除沈積於介電質襯裡5〇v之最頂層表面 上之過量導電材料，本文中該介電質襯裡50V之最頂層表 面稱為遠端水平面50D。平坦化製程可採用化學機械平坦 化、凹槽蝕刻或上述方法之組合。可用於至少一個金屬 V電通孔結構51之材料包括Cu ' w、c〇w、c〇wp、Au、 A1及Ag。另外，可在介電質襯裡5〇v與至少一個金屬導 14 201209963 電通孔結構5 1之間任選地沈積至少一個金屬襯裡（未圖 示）。可用於金屬襯裡之材料包括TiN、TaN、WN、TiAIN 及 TaCN。 在形成至少一個金屬導電通孔結構5丨之前、與之同時 或之後，至少一個介電質襯裡層金屬互連結構52可穿過 介電質襯裡50V而形成，以向下互連層導電結構（22、24、 32、34、42、44)提供電氣導電路徑。介電質襯裡5〇v包 括一個水平部分’該水平部分具有遠端水平面5〇D及近端 水平面50P。遠端水平面50D為介電質襯裡50乂之最頂層 表面，且該遠端水平面5 0D與至少一個金屬導電通孔結構 51之終端面共面。擴散阻障襯裡48之最頂層表面與近端 水平面5 0P共面》运端水平面5 〇D較近端水平面5〇p更遠離 該至少一個半導體元件12。擴散阻障襯裡48不接觸介電 質襯裡50V之最頂層表面。 參見第6圖’在介電層50V及至少一個金屬導電通孔結 構51之平坦表面上形成上互連層結構。上互連層結構包 括上互連層介電層及上互連層導電結構，該等上互連層 導電結構嵌設於該等上互連層介電層中。作為說明性實 例，上互連層介電層可包括第一上互連層介電層5〇L、第 一上互連層介電層60及第二上互連層介電層上互連 層導電結構可包括：第一上互連層結構54，該第—上互 連層結構54嵌設於第一上互連層介電層5〇L中；第二上互 連層通孔結構62及第二上互連層線結構64，該第二上互 連層通孔結構62及第二上互連層線結構64嵌設於第二上 15 201209963 互連層介電層60中；以及第三上互連層通孔結構72及第 二上互連層線結構74，該第三上互連層通孔結構72及第 二上互連層線結構74嵌設於第三上互連層介電層7〇中。 上互連層介電層（50L、60、70)可包括介電材料，諸如有 機矽酸鹽玻璃（OSG)、未摻雜的矽酸鹽玻璃（USG)、摻雜 的矽酸鹽玻璃、氮化矽或用作後段製程介電材料之任何 其他已知的介電材料。上互連層導電結構（54、62、64、 72 74)可例如為 Cu、Al、Ag、Ti、Ta、W、TiN、TaN、 WN Co WP及/或上述金屬之組合或合金。將上互連層結 構（50L、60、70、54、62、64、72、74)之最頂層表面平 坦化。 上互連層結構可進一步包括鈍化層8〇，該鈍化層8〇阻 斷不純材料及水汽進入下方結構。因&，鈍化層8〇包括 介電材料，該介電材料阻斷不純材料及水汽之擴散。例 如，鈍化層80可包括氮化矽層。鈍化層8〇之厚度可為置⑽ 奈米至2微米，且通常為200奈米至5〇〇奈米，但亦可採用 更小及更大的厚度。在鈍化層8〇中可形成至少一個開 口’且在至少一個開口中之每一開口中可形成前側金屬 墊82 ,以提供穿過鈍化層80之電氣導電路徑。至少一個 前側金屬墊82中之每一前側金屬墊82導電性地連接至至 少一個半導體元件12中之一個半導體元件12。至少一個 前侧金屬墊82包括金屬，該金屬諸如銅、鎳、鋁或上述 金屬之合金或組合。至少一個前側金屬墊82中之每一前 側金屬墊82可為C4墊，隨後C4球可結合至該以墊上。 16 201209963 參見第7圖’處理基板90可附接至基板ι〇及嵌設於該基 板10中之部件、下互連層結構（20、3〇、4〇、22、24、32、 34、42、44)、介電質襯裡50V及嵌設於該介電質襯裡5〇v 中之部件、以及上互連層結構（50L、60、70、54、62、 64、72、74)之組件。例如，黏著層88可塗覆於鈍化層8〇 之暴露表面，且處理基板90可附接至黏著層88。 黏著層88可為基於聚合物的、基於溶劑的、基於樹脂 的、基於彈性物的或基於任何其他類型之結合機制的， 月，J提為在適宜條件下，處理基板9〇或鈍化層8〇及至少一 個前側金屬墊82之組件可舆黏著層88解離。處理基板9〇 足夠厚，以在半導體基板丨〇隨後薄化後，提供處理時之 機械支撐。例如，處理基板9〇可為玻璃基板，該玻璃基 板之厚度為500微米至2毫米，且通常自75〇微米至^50 微米。在一個實施例中’處理基板9〇之橫向尺寸匹配半 導體基板10之橫向尺寸。例如，若半導體基板1〇之直徑 為300 mm，則處理基板9〇之直徑可為約3〇〇爪爪。 參見第8圖，可翻轉顛倒半導體基板1〇，且可藉由移除 半導體基板丨0之背側部分來使半導體基板1〇薄化。具體 而言，例如，藉由研磨 分割、拋光、凹槽蝕刻或上述 方法之、，且口 ’來移除半導體基板1 〇之背側部分。在此薄 化步驟之後’並未暴露介電質襯裡5〇v及擴散阻障襯裡 48。半導體基板1〇之厚度，亦即，半導體基板之正面 1與月面19之間的距離，超過在第2A圖及第⑼圖之處理 步驟結束時至少—個溝槽49之深度心例如，半導體基板 17 201209963 10之厚度可為25微米至300微米，且通常為45微米至i5〇 微米，但亦可採用更小及更大的厚度。 參見第9圖，採用蝕刻繼續使半導體基板丨〇變薄。蝕刻 相對於介電質襯裡50V之材料及擴散阻障襯裡48之一或 多種材料，選擇性地移除半導體基板10之材料。蝕刻可 為各向異性蝕刻或各向同性蝕刻。此外，該蝕刻可為乾 式蝕刻或濕式蝕刻。在暴露介電質襯裡5〇v之水平面及擴 散阻障襯裡48之一或更多材料後，蝕刻持續直至使半導 體基板10之背面19相對於介電質襯裡5〇v之水平面凹陷 至凹槽深度W。凹槽深度Μ大於介電質襯裡50V之厚度， 且凹槽深度Μ可為丨微米至1〇微米，且通常為2微米至5微 米，但亦可採用更小及更大的凹槽深度。在該步驟處， 至少一個金屬導電通孔結構51至少自半導體基板之第一 表面（亦即，正面11)延伸至半導體基板1〇之第二表面 (才Ρ 者面19)’該背面19位於正面η之相對側。 參見第10圖，在半導體基板1〇之背側上沈積背側介電 層。例如，可在半導體基板10之背面19、擴散阻障襯裡 48之暴露側壁及介電質襯裡50V之暴露水平面上，相繼沈 積第一背侧介電層丨12、第二背側介電層i 14及第三背側 介電層116 〇 在一個實施例中，背側介電層（丨丨2、丨i 4、丨丨6)中之至 少一個背側介電層可包括介電材料，該介電材料阻斷金 屬材料之擴散。阻斷金屬材料之擴散之介電材料，可為 可用作相連擴散阻障層48L之介電材料之任何材料。例 201209963 如，背側介電層（Π2、U4、116)中之至少一個背侧介電 層可包括含金屬氧化物介電材料。含金屬氧化物介電材 料之非限制示例性材料包括下述中之至少一種材料： Hf02、Zr〇2、La203、Al2〇3 ' Ti〇2、SrTi〇3、LaA1〇3、 Y2O3、Hf〇xNy、ZrOxNy、La2〇xNy、Al2OxNy、TiOxNy、
SrTiOxNy、LaA10xNy、Y2〇xNy、上述化合物之石夕酸鹽及 合金、以及上述化合物之非化學計量變體，其中χ中之每 一數值獨立地為約〇·5至約3,且7中之每一數值獨立地為〇 至約2。替代或另外地’背側介電層（11 2、114、11 6)中之 至少一個背側介電層之介電材料可包括選自碳化矽及 SiNxCyHz中之至少一種材料，其中^、丫及2中之每一數值 獨立地為0至約1。然而，替代或另外地，背側介電層 (112、114、116)中之至少一個背側介電層之介電材料可 包括氮化矽。背側介電層（112、114、116)中之至少一個 月側；丨電層之介電材料作用如金屬材料之擴散阻障，亦 即’阻斷金屬材料穿過背面19擴散至半導體基板1〇之半 導體材料中。 在一個實施例中’第一背側介電層1 i 2可包括至少一種 介電材料，該介電材料作用如金屬材料之擴散阻障。在 另一實施例中，背側介電層（112、114、116)中之一個背 側介電層可包括促使黏附材料，諸如未摻雜的矽酸鹽玻 璃。在又一實施例中，背側介電層（丨丨2、丨i 4、丨丨6)可為 第一背側介電層112、第二背側介電層114及第三背側介 電層116之堆疊，該第一背側介電層n2包括氧化矽，該 19 201209963 第一背側介電層11 4包括氮化矽或作用如金屬材料之擴 散阻障之任何其他介電材料，該第三背側介電層ιΐ6包括 氧化矽。可在必要時最佳化背側介電層（丨丨2、i丨4、丨丨6) 中之每一背側介電層之厚度。通常，背側介電層（11 2、 114 ' 116)中之每一背側介電層之厚度可為5〇奈米至2微 米通㊉，月側介電層（112、114、116)之組合厚度可為1 微米至3微米，但亦可採用更小及更大的組合厚度。 參見第11圖，藉由平坦化移除至少一個金屬導電通孔 結構5 1上方之背側介電層（丨丨2、〗丨4、丨〗◦中之部分及至 少一個金屬導電通孔結構51之上部（亦即，最垂直遠離 半導體基板10之正面11之部分），該平坦化可以由化學機 械平坦化（CMP)達成。在平坦化製程中，源自至少一 個金屬導電通孔結構5丨之被移除部分之金屬粒子可塗抹 於背側介電層（112、114、116)之暴露背側表面，該等背 側"電層（11 2、11 4、11 6)之暴露背側表面位於與半導體 基板10之介面上方（如第丨丨圖中所示）或下方（在實際 CMP處理步驟期間）。擴散阻障襯裡48之存在確保了（塗 抹於介電質襯裡50V之暴露表面上之）金屬粒子會被阻擋 於擴散阻障襯裡48與介電質襯裡50V之剩餘部分之間的 介面處。此外，在背側介電層（112、114、116)中之至少 一個背側介電層中存在介電材料層可阻止金屬粒子穿過 背側表面19進入半導體基板1〇，該介電材料層作用如金 屬材料之擴散阻障，該等金屬粒子塗抹於背側介電層 (112、114、116)之暴露表面上。具體而言，若第一背側 20 201209963 介電材料層112作用如金屬材料之擴散阻障，則由材料相 連密封半導體基板1 〇之背面i 9及側壁表面，該等材料阻 斷金屬材料擴散至半導體基板10中。因此，第一示例性 半導體結構不受背側金屬污染之影響，或第一示例性半 導體結構顯著降低背側金屬污染之風險。在平坦化後， 背側介電層（112、114、116)之暴露表面、至少—個金屬 導電通孔結構5 1及擴散阻障襯裡48相對於彼此為大體上 平坦的。 參見第12圖，可在背側介電層（112、114、116)及至少 一個金屬導電通孔結構51之表面上沈積背側鈍化層 120。背側鈍化層120可包括介電材料，該介電材料阻斷 不純材料及水汽進入下方結構。例如，背側鈍化層12〇可 包括氮化矽層。背側鈍化層120之厚度可為1〇〇奈米至2微 米，且通常為200奈米至500奈米，但亦可採用更小及更 大的厚度。在背侧鈍化層120中可形成至少一個開口，且 在至少一個開口中之每一開口中可形成背側金屬墊 122，以提供穿過背側鈍化層12〇之電氣導電路徑。至少 一個背側金屬墊122中之每一背側金屬墊丨22可接觸金屬 接觸通孔結構51。至少一個背側金屬墊122包括金屬，該 金屬諸如銅、鎳、鋁或上述金屬之合金或組合。至少一 個背側金屬墊122中之每一個背側金屬墊122可為C4墊， 隨後C4球可結合至該C4墊上。 至少一個金屬接觸通孔結構51中之每一金屬接觸通孔 結構51為導電貫穿基板之通孔（TSV)結構，該導電貫穿基 21 201209963 板之通孔結構至少自半導體基板10之正面n垂直延伸至 半導體基板10之背面19。隨後，例如，可藉由將C4球124 結合至至少一個背侧金屬墊122及位於安裝基板上金屬 塾’來將安裝結構（未圖示）結合至半導體基板1〇之背 側。可在不將處理基板9〇及半導體基板1〇之組件切割為 晶圓級之情況下執行與安裝結構之結合，或可在沿切割 槽切割處理基板90及半導體基板1 〇之組件後執行與安裝 結構之結合’該等切割槽對應於個別半導體晶片之邊 界。一旦安裝結構藉由C4球124結合至半導體基板1〇’則 可例如藉由分割或藉由溶解黏著層88，將處理基板9〇與 半導體基板10、一系列（^球以々及安裝基板之組件分離開 來。若將處理基板90分割掉’則可採用為本領域已知之 方法移除黏著層88之剩餘材料。 參見第13圖’藉由沈積介電質襯裡5〇v而不移除相連擴 散阻P早層48L之水平部分，根據本揭示案之第二實施例之 第二示例性半導體結構可源自第3圖之第一示例性半導 體結構。換言之’在本揭示案之第二實施例中省略了各 向異性蝕刻，該各向異性蝕刻移除相連擴散阻障層48L之 水平部分。第二實施例之介電質襯裡5〇v可具有與第一實 施例中相同的厚度及組合物，且可採用與第一實施例相 同的方法形成該介電質襯裡50V。因此，在相連擴散阻障 層48L之内側壁上直接形成介電質襯裡5〇v。 參見第14圖，藉由用導電材料填充至少一個溝槽49， 來在至少一個溝槽49中之每一溝槽49中形成金屬導電通 22 201209963 孔結構5 1。導雷好組i θ ‘ 枓τ，、有與第一實施例中相同的組合 *可抓用與第—實施例相同的方法沈積該導電材 ;藉由平坦化製程移除過量導電材料，該導電材料沈 積於下互連層結構(20、30、40、22、24、32 34 42、 44)之最頂層表面上。平坦化製程可採用化學機械平坦 化、凹槽蝕刻或兩者之組合。可用於至少一個金屬導電 通孔結構51之材料包括Cu、w、⑽、c〇wp、Au、μ 及Ag。另外，可選擇性地在介電質襯裡與至少一個 金屬導電通孔結構5 i之間沈積至少一個金屬襯裡（未圖 示）。可用於金屬襯裡之材料包括TiN、TaN、WN' ^八⑺ 及 TaCN。 在平坦化製程期間，自下互連層結構（2〇、3〇、4〇、、 24、32、34、42、44)之最頂層表面上方移除介電質襯裡 50V之水平部分，該等下互連層結構定位於正面丨丨上方。 此外’自下互連層結構（20、30、40、22、24、32、34、 42、44)之最頂層表面上方移除相連擴散阻障層48L之水 平部分。由於相連擴散阻障層48L之水平部分僅存在於下 互連層結構（20、30、40、22、24、32、34、42、44)上方 及填充後溝槽之底部，故在平坦化步驟期間移除定位於 正面11上方之相連擴散阻障層48L之所有水平部分。因為 在平坦化步驟期間亦移除至少一個導電通孔結構5丨中之 部分’所以在最初形成金屬導電通孔結構5 1之後及在移 除至少一個金屬導電通孔結構51之一或更多上末端部分 之時，移除相連擴散阻障層48L之水平部分。 23 201209963 本文中’將平坦化步驟後之相連擴散阻障層48L之剩餘 部刀稱為擴散阻障槪裡48。本文中，將嵌設於半導體基 板 10及下互連層結構（2〇、30、4〇、22、24、32、34、42、 44)中之介電質襯裡5〇v之剩餘部分稱為嵌設介電質襯裡 50 W，亦即，經嵌設之介電質襯裡。下互連層結構（2〇、 3〇、40、22、24、32、34、42、44)之最頂層表面、擴散 阻障襯裡48、嵌設介電質襯裡5〇w及至少一個金屬導電 通孔結構5 1相對於彼此為大體上平坦的。 參見第15圖’可在下互連層結構（2〇、3〇、4〇、22、24、 2 34 42、44)、擴散阻障襯裡48、喪設介電質襯裡5〇w 及至少一個金屬導電通孔結構51上之平坦最頂層表面沈 積平坦互連層介電層5 0X。平坦互連層介電層5〇χ可包括 可用於第一實施例之任一上互連層介電層(5〇L、、7〇) 層之任何介電材料。採用為本領域已知之方法，可在平 坦互連層介電層5GX中形成至少—個介電f襯裡層金屬 互連結構52»平坦互連層介電層5〇χ為具有共面水平面之 互連層介電層’該共面水平面接觸至少_個金屬導電通 孔結構5 1及擴散阻障襯裡4 §。 參見第16圖，可在第二示例性半導體結構上執行第_ 至第12圖之處理步驟。在平坦化步驟中，擴散阻障襯裡 料之存在確保了，在第U圖之處理步驟期間（亦即，在 移除至少-個金屬導電通孔結構51上方之背側介電層 (112、U4、116)中之部分及至少一個金屬導電通孔結構 51之上部期間）’金屬粒子會被阻擋於擴散阻障襯裡48與 24 201209963 介電質襯裡50W之剩餘部分之間的介面處，該等金屬粒 子塗抹於介電質襯裡50W之暴露表面上。此外，在該平 坦化步驟期間，在背侧介電層（112、114、116)中之^少 一個背側介電層中，介電材料層之存在阻止金屬粒子^ 過背侧表面19進入半導體基板1〇，該介電材料層作用如 金屬材料之擴散阻障，該等金屬粒子塗抹於背側介電層 (112、II4、116)之暴露表面上。因此，第二示例性半導 體結構不受背侧金屬污染之影響，或第二示例性半導體 結構顯著降低背側金屬污染之風險。 儘管已結合本揭示案之較佳實施例詳細圖示且描述了 本揭不案’但熟習此項技術者應理解，在不脫離本揭示 案之精神及範嘴之情況下T在形式上及細節上進行上述 及其他改變。因此，本揭示案並非受限於所描述且說明 之精確形式及細節，而是在所附申請專利範圍之範疇内 即可。 【圖式簡單說明】 第1圖為根據本揭示案之第—實施例的、在於基板中形 成至少一個溝槽之前的、第一示例性半導體結構之垂直 橫截面圖。 第2A圖為根據本揭*案之第—實施例&、在於基板中 形成至少一個溝槽之後的、第—示例性半導體結構之垂 直橫截面圖。 25 201209963 第2B圖為根據本揭示案之第一實施例的、第2A圖的第 一示例性半導體結構之俯視圖。 第3圖為根據本揭示案之第一實施例的、在沈積相連擴 散阻障層後的、第一示例性半導體結構之垂直橫截面圖。 第4圖為根據本揭示案之第一實施例的、在移除相連擴 散阻障層之水平部分且沈積介電質襯裡之後的、第一示 例性半導體結構之垂直橫截面圖。 第5圖為根據本揭示案之第一實施例的、在沈積金屬導 電通孔結構之後的、第一示例性半導體結構之垂直橫截 面圖。 第6圖為根據本揭示案之第一實施例的、在形成上互連 層結構之後的、第一示例性半導體結構之垂直橫截面圖。 第7圖為根據本揭示案之第一實施例的、在附接處理基 板之後的、第一示例性半導體結構之垂直橫截面圖。 第8圖為根據本揭示案之第一實施例的、在移除基板之 背側部分之後的、第一示例性半導體結構之垂直橫截面 圖。 第9圖為根據本揭示案之第一實施例的、在使背側半導 體表面凹陷之後的、第一示例性半導體結構之垂直橫截 面圖。 第1 〇圖為根據本揭示案之第一實施例的、在沈積背側 介電層之後的、第一示例性半導體結構之垂直橫截面圖。 26 201209963 第11圖為根據本揭示案之第一實施例的、在平坦化背 侧介電層之後的、第一示例性半導體结構之垂直橫截面 圖。 第12圖為根據本揭示案之第一實施例的、在形成背側 金屬塾、將C4球附接於背側上且使處理基板與前側分離 之後的、第一示例性半導體結構之垂直橫截面圖。 第13圖為根據本揭示案之第二實施例的、在沈積介電 質襯裡之後的、第二示例性半導體結構之垂直橫截面圖。 第14圖為根據本揭示案之第二實施例的、在沈積金屬 導電通孔結構且移除介電質襯裡及擴散阻障襯裡之水平 部分之後的、第二示例性半導體結構之垂直橫截面圖。 第15圖為根據本揭示案之第二實施例的、在沈積第一 上後段製程（back-end-of-line; BEOL)介電層且在該第一 上後段製程介電層中形成通孔結構之後的、第二示例性 半導體結構之垂直橫截面圖。 第16圖為根據本揭示案之第二實施例的、在形成背側 金屬墊、將C4球附接於背側上且使處理基板與前側分離 之後的、第二示例性半導體結構之垂直橫截面圖。 【主要元件符號說明】 27 201209963 10 半導體基板 11 正面 12 半導體元件 19 背面 20 第一下互連層介電層 22 第一下互連層通孔結 構 24 第一下互連層線結構 30 第二下互連層介電層 32 第二下互連層通孔結構 34 第二下互連層線結構 40 第三下互連層介電層 42 第三下互連層通孔結 構 44 第三下互連層線結構 47 遮罩層 48 擴散阻障襯裡 48L 相連擴散阻障層 49 溝槽 50D 遠端水平面 50L 第一上互連層介電層 50P 近端水平面 50V 介電質襯裡/介電層 50W嵌設介電質襯裡 50X 平坦互連層介電層 51 金屬導電通孔結構/金 屬接觸通孔結構 52 介電質襯裡層金屬互連結54 第一上互連層結構 構 60 第二上互連層介電層_ 62 第二上互連層通孔結 構 64 第二上互連層線結構 70 第三上互連層介電層 72 第三上互連層通孔結構 74 第三上互連層線結構 80 鈍化層 82 前側金屬塾 88 黏著層 90 處理基板 112 第一背側介電層 114 第二背側介電層 28 201209963 ' 116第三背側介電層 120 122背側金屬墊 124 背側鈍化層 C4球 29

Claims (1)

  1. 201209963 七、申請專利範圍： K一種半導體結構，包含—半導體基板及-貫穿基板之通 孔（TSV)結構，該貫穿基板之通孔結構嵌η該半導體 基板中’其中該TSV結構包括： 一擴散阻障襯裡，該擴散阻障襯裡接觸一相連側壁之一整 體，該側壁圍繞該半導體基板内之一孔； 一介電質襯裡，該介電質襯裡接觸該擴散阻障襯裡之一内 側壁；以及 一金屬導電通孔結構，該金屬導電通孔結構橫向地接觸該 介電質襯裡。 2. 如請求項1所述之半導體結構，其中該擴散阻障襯裡包含 一導電材料。 3. 如請求項2所述之半導體結構，其十該擴散阻障襯裡包括 一導電金屬氮化物，且其中該導電金屬氮化物係選自 TiN、TaN、WN、TiAIN及 TaCN。 4. 如請求項2所述之半導體結構，其中該擴散阻障襯裡包括 一元素金屬，或其中該擴散阻障襯裡為一可電鍍材料， 該可電鍍材料選自一 Co W合金及一 Co WP合金。 30 201209963 5.:請求項1所述之半導體結構，其中該擴散阻障襯裡包含 -介電材料’該介電材料阻斷一金屬材料之擴散。 6·=求項5所述之半導體結構，其中該擴散阻障襯裡包括 金屬氧化物之介電材料；或該擴散阻障襯裡包含選 自碳化石夕及SiNxCyHA一材料，其中χ、πζ中之每—數 值獨立地為0至約1 ;或該擴散阻障襯裡包含氮化矽。 7·如請求項6所述之半導體結構，其中該含金屬氧化物之介 電材料包括下述中之至少一種材料：Hf〇2、Zr〇2、La2〇3、 Al2〇3、Ti〇2、SrTi03、LaA103、Y2〇3、Hf〇xNy、Zr〇xNy、 La2OxNy、Al2OxNy、TiQxNy、SrTiOxNy、LaA10xNy、 Y2〇xNy、上述化合物之矽酸鹽及合金、以及上述化合物 之非化學計量變體，其中χ中之每一數值獨立地為約〇5 至約3 ’且y中之每—數值獨立地為〇至約2。 8.如請求項1所述之半導體結構，進一步包含： 至少一個半導體元件’該等半導體元件位於該半導體基板 之一第一表面上；以及 —擴散阻障層’該擴散阻障層位於該半導體基板之一第二 表面上’其中該第二表面位於該第一表面之一相對側， 且 其中該擴散阻障層包含一介電材料，該介電材料阻斷一金 屬材料之擴散，或其中該擴散阻障層包‘含選自一含金屬 31 201209963 氧化物之介電材料、碳化矽、siNxCyHz及氮化矽之—材 料，其中X、丫及2中之每一數值獨立地為〇至約叉。 9. 如請求項1所述之半導體結構，其中該介電質襯裡包括— 水平部分，該水平部分具有一遠端水平面及一近端水平 面，其中該遠端水平面較該近端水平面更遠離該至少一 個半導體元件，且該遠端（distal )水平面與該金屬導電 通孔結構之一終端面（end surface)共面。 10. 如請求項1所述之半導體結構，進一步包含：一互連片 介電層，該介電層具有一共面水平面，該共面水平面接 觸該金屬導電通孔結構及該擴散阻障襯裡。 11. 如請求項1所述之半導體結構，進一步包含： 至少一個半導體元件，該等半導體元件位於該半導體基板 之一第一表面上；以及 一金屬塾’該金屬墊導電性地連接至該金屬導電通孔結 構，且相較於該第一表面’該金屬墊更接近於該半導體 基板之一第二表面，其中該第二表面位於該第一表面之 相對侧’且該第二表面進一步包含一 C4球，該C4球結 合至該金屬塾。 12. —種形成一半導體結構之方法’包含以下步驟： 32 201209963 在-半導體基板之-第—表面上形成至少一個半導體元件 在該半導體基板中形成-溝槽，纟中該半導體基板之一半 導體材料暴露於該溝槽之一側壁處； 在該側壁上直接形成一擴散阻障襯裡； 藉由用一導電填充材料填夯 、兄该溝槽，形成一金屬導電通孔 結構；以及 使該半導體基板變薄，其中在 开r隹該變薄步驟後，該金屬導電 通孔結構至少自該半導體其 等體基板之該第一表面延伸至該半 導體基板之一第二表面，苴φ封_ ^、中°亥第·—表面位於該第·—表 面之一相對側。 13.如請求項12所述之方法，其中藉由沈積一相連擴散阻障 層且隨後自該第-表面上方移除該相連擴散阻障層之水 平部分’來形成該擴散阻障襯裡，其中該擴散阻障概裡 包括該相連擴散阻障層之剩餘垂直部分。 各向異性钮刻移除 且在該各向異性蝕 14.如請求項π所述之方法，其中藉由一 該相連擴散阻障層之該等水平部分， 刻後，暴露該溝槽之—底面，或其中在形成該金屬導電 通孔結構且同時移除該金屬導電通孔結構之一末端部分 後，移除該相連擴散阻障層之該等水平部分，或 ，其中該介電 内側壁或該擴 進一步包含以下步驟：形成一介電質襯裡 質襯裡直接形成於該相連擴散阻障層之一 33 201209963 . 散阻障襯裡之一内側壁上，且該金屬導電通孔結構直接 形成於該介電質襯裡上。 15.如請求項12所述之方法，進一步包含以下步驟： 在該第二表面上形成-金屬墊’其中該金屬墊導電性地連 接至該金屬導電通孔結構；以及 將一C4球結合至該金屬墊，或 進一步包含以下步驟：在該半導體基板之該第二表面上直 接形成一擴散阻障層，其中該擴散阻障層包含一材料， 該材料阻斷一金屬材料之擴散。 34
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