CN103026483B - 无金属污染的贯穿衬底过孔结构 - Google Patents

无金属污染的贯穿衬底过孔结构 Download PDF

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Publication number
CN103026483B
CN103026483B CN201180036336.8A CN201180036336A CN103026483B CN 103026483 B CN103026483 B CN 103026483B CN 201180036336 A CN201180036336 A CN 201180036336A CN 103026483 B CN103026483 B CN 103026483B
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Prior art keywords
semiconductor
diffusion barrier
metal
semiconductor substrate
barrier pad
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CN201180036336.8A
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CN103026483A (zh
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M·G·法鲁奇
R·汉昂
R·P·沃兰特
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Core Usa Second LLC
GlobalFoundries Inc
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International Business Machines Corp
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Abstract

本发明提供一种不受由于后侧平坦化工艺所致的金属污染影响的贯穿衬底过孔(TSV)结构。在形成贯穿衬底过孔(TSV)沟槽之后，扩散阻挡衬垫保形地沉积于TSV沟槽的侧壁上。通过在扩散阻挡衬垫的竖直部分上沉积电介质材料来形成电介质衬垫。通过随后填充TSV沟槽来形成金属传导过孔结构。去除扩散阻挡衬垫的水平部分。扩散阻挡衬垫在后侧平坦化期间通过阻止源于金属传导过孔结构的残留金属材料进入衬底的半导体材料来保护衬底的半导体材料，由此保护衬底内的半导体器件免受金属污染。

Description

无金属污染的贯穿衬底过孔结构
技术领域
本公开内容涉及半导体结构领域，并且具体地涉及无金属污染的贯穿衬底过孔结构及其制造方法。
背景技术
近年来已经提出“三维硅(3DSi)”结构以实现在封装体或者系统板上装配的多个硅芯片和/或晶片的接合。3DSi结构运用称为“贯穿衬底的过孔”结构或者“TSV”结构的传导过孔结构，这些传导过孔结构提供贯穿半导体芯片衬底的电连接。TSV结构增加给定空间中集成的有源电路的密度。这样的3DSi结构运用贯穿衬底过孔(TSV)以在多个硅芯片和/或晶片之间提供电连接。
常规TSV结构通常运用经过半导体芯片的衬底延伸的铜过孔结构。铜过孔结构被氧化硅电介质衬垫从衬底横向电隔离。氧化硅电介质衬垫不防止金属材料扩散通过。因此，在铜过孔结构的嵌入末端的化学机械抛光期间生成的残留铜材料可能涂污到氧化硅电介质衬垫的端表面上，并且随后经过氧化硅电介质衬垫并且向衬底内的半导体材料中扩散。这样的残留铜材料向半导体材料中扩散可能在衬底中的半导体器件内产生有害影响，诸如电短接。
发明内容
提供一种不受由于后侧平坦化工艺所致的金属污染影响的贯穿衬底过孔(TSV)结构。在形成贯穿衬底过孔(TSV)沟槽之后，扩散阻挡衬垫保形地沉积于TSV沟槽的侧壁上。通过在扩散阻挡衬垫的竖直部分上沉积电介质材料来形成电介质衬垫。通过随后填充TSV沟槽来形成金属传导过孔结构。在沉积用于金属传导过孔结构的传导材料之前通过各向异性蚀刻来去除扩散阻挡衬垫的水平部分，或者可以在去除电介质衬垫的水平部分之后通过平坦化来去除扩散阻挡衬垫的水平部分。扩散阻挡衬垫在后侧平坦化期间通过阻止源于金属传导过孔结构的残留金属材料进入衬底的半导体材料来保护衬底的半导体材料，由此保护衬底内的半导体器件免受金属污染。
根据本公开内容的一个方面，提供一种半导体结构，该半导体结构包括半导体衬底和嵌入于其中的贯穿衬底过孔(TSV)结构。TSV结构包括：扩散阻挡衬垫，接触半导体衬底内的孔周围的邻接侧壁的全部；电介质衬垫，接触扩散阻挡衬垫的内侧壁；以及金属传导过孔结构，横向接触电介质衬垫。
根据本公开内容的另一方面，提供一种形成半导体结构的方法。该方法包括：在半导体衬底的第一表面上形成至少一个半导体器件；在半导体衬底中形成沟槽，其中半导体衬底的半导体材料暴露于沟槽的侧壁；在侧壁上直接形成扩散阻挡衬垫；通过用传导填充材料填充沟槽来形成金属传导过孔结构；并且减薄半导体衬底，其中金属传导过孔结构在减薄之后至少从第一表面向半导体衬底的第二表面延伸，其中第二表面位于第一表面的相对侧上。
附图说明
图1是根据本公开内容第一实施例的第一示例半导体结构在衬底中形成至少一个沟槽之前的竖直截面图。
图2A是根据本公开内容第一实施例的第一示例半导体结构在衬底中形成至少一个沟槽之后的竖直截面图。
图2B是根据本公开内容第一实施例的图2A的第一示例半导体结构的俯视图。
图3是根据本公开内容第一实施例的第一示例半导体结构在沉积邻接扩散阻挡层之后的竖直截面图。
图4是根据本公开内容第一实施例的第一示例半导体结构在去除邻接扩散阻挡层的水平部分并且沉积电介质衬垫之后的竖直截面图。
图5是根据本公开内容第一实施例的第一示例半导体结构在沉积金属传导过孔结构之后的竖直截面图。
图6是根据本公开内容第一实施例的第一示例半导体结构在沉积上互连级结构之后的竖直截面图。
图7是根据本公开内容第一实施例的第一示例半导体结构在附着操纵(handle)衬底之后的竖直截面图。
图8是根据本公开内容第一实施例的第一示例半导体结构在去除衬底的后侧部分之后的竖直截面图。
图9是根据本公开内容第一实施例的第一示例半导体结构在凹陷后侧半导体表面之后的竖直截面图。
图10是根据本公开内容第一实施例的第一示例半导体结构在沉积后侧电介质层之后的竖直截面图。
图11是根据本公开内容第一实施例的第一示例半导体结构在平坦化后侧电介质层之后的竖直截面图。
图12是根据本公开内容第一实施例的第一示例半导体结构在形成后侧金属焊盘、在后侧上附着C4球并且从前侧分离操纵衬底之后的竖直截面图。
图13是根据本公开内容第二实施例的第二示例半导体结构在沉积电介质衬垫之后的竖直截面图。
图14是根据本公开内容第二实施例的第二示例半导体结构在沉积金属传导过孔结构并且去除电介质衬垫和扩散阻挡衬垫的水平部分之后的竖直截面图。
图15是根据本公开内容第二实施例的第二示例半导体结构在沉积第一上后段工艺(back-end-of-line)(BEOL)电介质层并且在其中形成过孔结构之后的竖直截面图。
图16是根据本公开内容第二实施例的第二示例半导体结构在形成后侧金属焊盘、在后侧上附着C4球并且从前侧分离操纵衬底之后的竖直截面图。
具体实施方式
如上文所言，本公开内容涉及现在参照附图详细描述的无金属污染贯穿衬底过孔结构及其制造方法。在附图全篇中，相同标号或者字母用来标示相似或者等同单元。附图未必按比例绘制。
如这里所用，“传导贯穿衬底过孔(TSV)结构”是贯穿衬底(即至少从衬底的顶表面向衬底的底表面)延伸的传导结构。
如这里所用，如果表面旨在于平坦，则表面为“基本上平坦”，并且表面的非平坦度受用来形成表面的加工步骤中固有的缺陷限制。
如这里所用，“装配表面”是任何如下结构，可以通过产生与该结构的电连接来向该结构装配半导体芯片。装配结构可以是封装衬底、插入体结构或者另一半导体芯片。
如这里所用，如果在第一单元与第二单元之间存在电传导路径，则所述第一单元“传导地连接”到所述第二单元。
参照图1，根据本公开内容第一实施例的第一示例半导体结构包括半导体衬底10。半导体衬底10包括可以从硅、锗、硅锗合金、硅碳合金、硅锗碳合金、砷化镓、砷化铟、磷化铟、III-V族化合物半导体材料、II-VI化合物半导体材料、有机半导体材料和其它化合物半导体材料中选择但不限于此的半导体材料。半导体衬底10可以是体衬底、绝缘体上硅(SOI)衬底或者混合衬底，该混合衬底具有体部分和SOI部分。半导体衬底10的至少上部分包括半导体材料区域，在该半导体材料区域中，运用本领域已知方法来形成至少一个半导体器件12，诸如晶体管、二极管、电容器、电感器和/或电阻器。
下互连级结构形成于半导体衬底10的前表面11上。前表面11是半导体衬底的如下表面，至少一个半导体器件位于该表面上。前表面11的至少一部分包括半导体材料。下互连级结构包括下互连级电介质层和嵌入于其中的下互连级传导结构。作为示例例子，下互连级电介质层可以包括第一下互连级电介质层20、第二下互连级电介质层30和第三下互连级电介质层40。下互连级传导结构可以包括嵌入于第一下互连级电介质层20中的第一下互连级过孔结构22和第一下互连级线结构24、嵌入于第二下互连级电介质层30中的第二下互连级过孔结构32和第二下互连级线结构34、以及嵌入于第三下互连级电介质层40中的第三下互连级过孔结构42和第三下互连级线结构44。下互连级电介质层(20，30，40)可以包括电介质材料，诸如有机硅酸盐玻璃(OSG)、未掺杂的硅酸盐玻璃(USG)、掺杂的硅酸盐玻璃、氮化硅或者用作后段工艺电介质材料的任何其它已知电介质材料。下互连级传导结构(22，24，32，34，42，44)可以例如是Cu、Al、Ag、Ti、Ta、W、TiN、TaN、WN、CoWP和/或其组合或者合金。平坦化下互连级结构(20，30，40，22，24，32，34，42，44)的最上表面。
参照图2A和图2B，掩模层47形成于下互连级结构(20，30，40，22，24，32，34，42，44)的顶表面上并且随后被光刻地图案化。掩模层47可以是软掩模层(即光阻剂层)或者硬掩模层，该硬掩模层包括与下互连级结构(20，30，40，22，24，32，34，42，44)的最上层(例如第三下互连级电介质层40)的电介质材料不同的抗蚀刻电介质材料。如果掩模层47是硬掩模层，则可以向掩模层47的顶表面涂敷光阻剂层并且光刻地图案化该光阻剂层(未示出)，并且可以向硬掩模层中转移光阻剂层中的图案以提供经图案化的掩模层47。如果掩模层47是光阻剂层，则可以通过光刻曝光和显影来图案化光阻剂层。
随后通过各向异性蚀刻向下互连级结构(20，30，40，22，24，32，34，42，44)和半导体衬底10的上部分中转移硬掩模层47中的图案以形成至少一个沟槽49。每个沟槽49的截面形状可以具有、但是无需具有如图2B中所示环形形状。半导体衬底10的半导体材料暴露于至少一个沟槽49的侧壁。至少一个沟槽49的、如从半导体衬底10的前表面11测量的深度d可以是20微米至200微米，并且通常从40微米至100微米，但是也可以运用更少和更大深度。至少一个沟槽49的横向尺度(即在至少一个沟槽49之一的两个不同侧壁之间的最小横向距离)可以从2微米至20微米，并且通常从4微米至10微米，但是也可以运用更少和更大横向尺度。例如在沟槽49的水平截面区域是环带的情况下，该沟槽49的横向尺度可以是在外侧壁的半径与内侧壁的半径之差，并且可以从2微米至20微米，而且通常从4微米至10微米。用于沟槽49的环形形状仅为示例例子，并且沟槽49可以具有任何水平截面形状，只要在沉积本公开内容的衬垫之后有可能在后续加工步骤中用传导材料填充沟槽49。随后相对于下互连级结构(20，30，40，22，24，32，34，42，44)的暴露电介质材料选择性去除掩模层47。
参照图3，邻接扩散阻挡层48L沉积于至少一个沟槽49的底表面和侧壁以及下互连级结构(20，30，40，22，24，32，34，42，44)的最上表面上。邻接扩散阻挡层48L邻接地覆盖第一示例半导体结构的所有表面和至少一个沟槽49的侧壁表面。
在一个实施例中，邻接扩散阻挡层48L包括传导材料。邻接扩散阻挡层48L可以由单个同质传导材料构成，或者可以包括具有不同组成的多个传导材料层。具体而言，邻接扩散阻挡层48L的传导材料可以包括至少一个传导金属氮化物。用于传导金属氮化物的非限制示例材料包括TiN、TaN、WN、TiAlN和TaCN。取而代之或者除此之外，邻接扩散阻挡层48L的传导材料可以包括未向半导体材料中扩散的单质金属。这样的单质金属包括Ta、Ti、W和Mo。又取而代之或者除此之外，邻接扩散阻挡层48L的传导材料可以包括可以从CoW合金和CoWP合金选择的可电镀材料。邻接扩散阻挡层48L的传导材料作为用于金属材料的扩散阻挡来工作，即阻止金属材料向半导体衬底10的半导体材料中扩散。
可以通过化学气相沉积(CVD)、原子层沉积(ALD)、蒸发、物理气相沉积(PVD，即溅射)、电镀、无电镀覆或者其组合来沉积可以作为唯一成分或者作为多成分传导层之一而用于邻接扩散阻挡层48L的各种传导材料为邻接层。邻接扩散阻挡层48L的每个传导成分层的厚度可以从1nm至100nm。邻接扩散阻挡层48L的总厚度可以从5nm至100nm，但是也可以运用更少和更大厚度。
在另一实施例中，邻接扩散阻挡层48L包括电介质材料。邻接扩散阻挡层48L可以由单个同质电介质材料构成或者可以包括具有不同组成的多个电介质材料层。具体而言，邻接扩散阻挡层48L的电介质材料可以包括包含金属氧化物的电介质材料。用于包含金属氧化物的电介质材料的非限制示例材料包括HfO2、ZrO2、La2O3、A12O3、TiO2、SrTiO3、LaA1O3、Y2O3、HfOxNy、ZrOxNy、La2OxNy、Al2OxNy、TiOxNy、SrTiOxNy、LaA1OxNy、Y2OxNy、其硅酸盐及其合金及其非化学当量变体中的至少一种，其中x的每个值独立地从约0.5至约3，并且y的每个值独立地从0至约2。取而代之或者除此之外，邻接扩散阻挡层48L的电介质材料可以包括从碳化硅和SiNxCyHz中选择的至少一种材料，其中x、y和z的每个值独立地从0至约1。另外取而代之或者除此之外，邻接扩散阻挡层48L的电介质材料可以包括氮化硅。邻接扩散阻挡层48L的电介质材料作为用于金属材料的扩散阻挡来工作，即阻止金属材料向半导体衬底10的半导体材料中扩散。
可以通过化学气相沉积(CVD)、原子层沉积(ALD)、喷涂或者其组合来沉积可以作为唯一成分或者作为多成分传导层之一而用于邻接扩散阻挡层48L的各种传导材料为邻接层。可以例如在Angyal等人的第7,009,280号美国专利中发现如本领域已知的沉积SiNxCyHz的方法，其中x、y和z的每个值独立地从0至约1。通过引用将’280专利的、与沉积SiNxCyHz有关的内容结合于此。邻接扩散阻挡层48L的每个电介质成分层的厚度可以从5nm至200nm。邻接扩散阻挡层48L的总厚度可以从5nm至100nm，但是也可以运用更少和更大厚度。
在又一实施例中，邻接扩散阻挡层48L包括至少一个电介质材料层与至少一个传导材料层的组合。也可以组合运用可以独立用于邻接扩散阻挡层48L的电介质材料和传导材料。邻接扩散阻挡层48L的总厚度可以从5nm至100nm，但是也可以运用更少和更大厚度。
参照图4，通过各向异性蚀刻来去除邻接扩散阻挡层48L的水平部分，该各向异性蚀刻可以是相对于下互连级结构(20，30，40，22，24，32，34，42，44)的顶表面上的材料有选择地去除邻接扩散阻挡层48L的材料的反应离子蚀刻。邻接扩散阻挡层48L的剩余竖直部分构成仅存在于至少一个沟槽49的侧壁上的扩散阻挡衬垫48。在各向异性蚀刻之后暴露至少一个沟槽49的底表面。在示例例子中，沟槽49具有环形形状，成对扩散阻挡衬垫48(即内扩散阻挡层和外扩散阻挡层)形成于沟槽49的侧壁上。
电介质衬垫50V邻接地直接沉积于下互连级结构(20，30，40，22，24，32，34，42，44)的最上表面、扩散阻挡衬底48的内侧壁和至少一个沟槽49的底表面上。电介质衬垫50V包括电介质材料，诸如未掺杂的硅酸盐玻璃(USG)、掺杂的硅酸盐玻璃、有机硅酸盐玻璃或者其组合。电介质衬垫50V提升将随后形成于至少一个沟槽49内的金属传导过孔结构的粘合性。电介质衬垫50V的、如从扩散阻挡衬垫48的内侧壁水平测量的厚度可以从50nm至1微米并且通常从150nm至500nm，但是也可以运用更少和更大厚度。可以例如通过化学气相沉积(CVD)来沉积电介质衬垫50V。
参照图5，通过用传导材料填充至少一个沟槽49中的每个沟槽来在至少一个沟槽49的每个沟槽中形成金属传导过孔结构51。可以例如通过电镀、无电镀覆、物理气相沉积、化学气相沉积或者其组合来沉积传导材料。通过平坦化工艺去除在电介质衬垫50V的最上表面(这里称为远水平表面50D)之上沉积的过量传导材料。平坦化工艺可以运用化学机械平坦化、凹陷蚀刻或者其组合。可以用于至少一个金属传导过孔结构51的材料包括Cu、W、CoW、CoWP、Au、Al和Ag。此外，至少一个金属衬垫(未示出)可以可选地沉积于电介质衬垫50V与至少一个金属传导过孔结构51之间。可以用于金属衬垫的材料包括TiN、TaN、WN、TiAlN和TaCN。
可以在形成至少一个金属传导过孔结构51之前、并行或者之后经过电介质衬垫50V形成至少一个电介质衬垫级金属互连结构52以提供通向下互连级结构(22，24，32，34，42，44)的电传导路径。电介质衬垫50V包括具有远水平表面50D和近水平表面50P的水平部分。远水平表面50D是电介质衬垫50V的最上表面并且与至少一个金属传导过孔结构51的端表面共面。扩散阻挡衬垫48的最上表面与水平近表面50P共面。远水平表面50D比近水平表面50P更远离至少一个半导体器件12。扩散阻挡衬垫48未接触电介质衬垫50V的最上表面。
参照图6，上互连级结构形成于电介质层50V和至少一个金属传导过孔结构51的平坦表面之上。上互连级结构包括上互连级电介质层和嵌入于其中的上互连级传导结构。作为示例例子，上互连级电介质层可以包括第一上互连级电介质层50L、第二上互连级电介质层60和第三上互连级电介质层70。上互连级传导结构可以包括嵌入于第一上互连级电介质层50L中的第一上互连级结构54、嵌入于第二上互连级电介质层60中的第二上互连级过孔结构62和第二上互连级线结构64、以及嵌入于第三上互连级电介质层70中的第三上互连级过孔结构72和第三上互连级线结构74。上互连级电介质层(50L，60，70)可以包括电介质材料，诸如硅酸盐玻璃(OSG)、未掺杂的硅酸盐玻璃(USG)、掺杂的硅酸盐玻璃、氮化硅或者用作后段工艺电介质材料的任何其它已知电介质材料。上互连级传导结构(52，62，64，72，74)可以例如是Cu、Al、Ag、Ti、Ta、W、TiN、TaN、WN、CoWP和/或其组合或者合金。平坦化上互连级结构(50L，60，70，54，62，64，72，74)的最上表面。
上互连级结构还可以包括阻止杂质材料和潮湿进入下层结构的钝化层80。因此，钝化层80包括阻止杂质材料和潮湿扩散的电介质材料。例如钝化层80可以包括氮化硅层。钝化层80的厚度可以从100nm至2微米并且通常从200微米至500微米，但是也可以运用更少和更大厚度。至少一个开口可以形成于钝化层80中，并且前侧金属焊盘82可以形成于至少一个开口的每个开口中以经过钝化层80提供电传导路径。至少一个前侧金属焊盘82的每个前侧金属焊盘传导地连接到至少一个半导体器件12之一。至少一个前侧金属焊盘82包括金属，诸如铜、镍、铝或者其合金或者组合。至少一个前侧金属焊盘82的每个金属焊盘可以是C4焊盘，C4球可以随后键合于该C4焊盘上。
参照图7，操纵衬底90可以附着到衬底10和嵌入于中的部件、下互连级结构(20，30，40，22，24，32，34，42，44)、电介质衬垫50V和嵌入于其中的部件、以及上互连级结构(50L，60，70，54，62，64，72，74)的组件。例如可以向钝化层88的暴露表面涂敷粘合层88，并且可以向粘合层88附着操纵衬底90。
粘合层88可以基于聚合物、基于溶剂、基于树脂、基于弹性体或者基于任何其它类型的键合机制，只要操纵衬底90或者钝化层88和至少一个前侧金属焊盘82的组件可以在适当条件之下从粘合层88解离。操纵衬底90厚到足以在随后减薄半导体衬底10之后提供用于操纵的机械支撑。例如，操纵衬底90可以是具有从500微米至2mm并且通常从750微米至1250微米的厚度的玻璃衬底。在一个实施例中，操纵衬底90的横向尺度与半导体衬底10的横向尺度匹配。例如，如果半导体衬底10具有300mm的直径，则操纵衬底90可以具有约300mm的直径。
参照图8，可以通过去除半导体衬底10的后侧部分来倒置翻转并且减薄半导体衬底10。具体而言，例如通过研磨、分裂、抛光、凹陷蚀刻或者其组合来去除半导体衬底10的后侧部分。在这一减薄步骤之后未暴露电介质衬垫50V和扩散阻挡衬垫48。半导体衬底10的厚度(即在半导体衬底10的前表面11与后表面19之间的距离)在图2A和图2B的加工步骤结束时超过至少一个沟槽49的深度d。例如，半导体衬底10的厚度可以从约25微米至300微米并且通常从45微米至约150微米，但是也可以运用更少和更大厚度。
参照图9，运用蚀刻来继续减薄半导体衬底10。该蚀刻相对于电介质衬垫50V的材料和扩散阻挡衬垫48的材料选择性去除半导体衬底10的材料。蚀刻可以是各向异性蚀刻或者各向同性蚀刻。另外，这一蚀刻可以是干蚀刻或者湿蚀刻。该蚀刻在暴露电介质衬垫50V和扩散阻挡衬垫48的材料的水平表面之后继续直至半导体衬底10的后表面19相对于电介质衬垫50V的水平表面凹陷至凹陷深度rd。凹陷深度rd大于电介质衬垫50V的厚度，并且可以从1微米至10微米并且通常从2微米至5微米，但是也可以运用更少和更大凹陷深度。在这一步骤，至少一个金属传导过孔结构51至少从半导体衬底的第一表面(即前表面11)向半导体衬底10的第二表面(即位于前表面11的相对侧上的后表面19)延伸。
参照图10，后侧电介质层沉积于半导体衬底10的后侧上。例如，第一后侧电介质层112、第二后侧电介质层114和第三后侧电介质层116可以随后沉积于半导体衬底10的后表面19、扩散阻挡衬垫48的暴露侧壁和电介质衬垫50V的暴露水平表面上。
在一个实施例中，后侧电介质层(112，114，116)的至少一个后侧电介质层可以包括阻止金属材料扩散的电介质材料。阻止金属材料扩散的电介质材料可以是任何如下材料，该材料可以用作邻接扩散阻挡层48L的电介质材料。例如后侧电介质层(112，114，116)的至少一个后侧电介质层可以包含金属氧化物的电介质材料。用于包含金属氧化物的电介质材料的非限制示例材料包括HfO2、ZrO2、La2O3、A12O3、TiO2、SrTiO3、LaA1O3、Y2O3、HfOxNy、ZrOxNy、La2OxNy、Al2OxNy、TiOxNy、SrTiOxNy、LaA1OxNy、Y2OxNy、其硅酸盐及其合金及其非化学当量变体中的至少一种，其中x的每个值独立地从约0.5至约3，并且y的每个值独立地从0至约2。取而代之或者除此之外，后侧电介质层(112，114，116)中的至少一个后侧电介质层的电介质材料可以包括从碳化硅和SiNxCyHz中选择的至少一个材料，其中x、y和z的每个值独立地从0至约1。另外取而代之或者除此之外，后侧电介质层(112，114，116)的至少一个后侧电介质层的电介质材料可以包括氮化硅。后侧电介质层(112，114，116)的至少一个后侧电介质层的电介质材料作为用于金属材料的扩散阻挡来工作，即阻止金属材料经过背表面19向半导体衬底10的半导体材料中扩散。
在一个实施例中，第一后侧电介质层112可以包括作为用于金属材料的扩散阻挡来工作的至少一个电介质材料。在另一实施例中，后侧电介质层(112，114，116)之一可以包括粘合性提升材料，诸如未掺杂的硅酸盐玻璃。在又一实施例中，后侧电介质层(112，114，116)可以是包括氧化硅的第一后侧电介质层112、包括氮化硅或者作为用于金属材料的阻挡层来工作的任何其它电介质材料的第二后侧电介质层114、以及包括氧化硅的第三后侧电介质层116的堆叠物。可以根据需要优化后侧电介质层(112，114，116)的每个后侧电介质层的厚度。一般而言，后侧电介质层(112，114，116)的每个后侧电介质层可以具有从50nm至2微米的厚度。通常，后侧电介质层(112，114，116)的组合厚度可以从1微米至3微米，但是也可以运用更少和更大组合厚度。
参照图11，通过可以由化学机械抛光(CMP)实现的平坦化来去除后侧电介质层(112，114，116)的在至少一个金属传导过孔结构51的部分和至少一个金属传导过孔结构51的上部分(即从半导体衬底10的前表面11竖直地最远离的部分)。在平坦化工艺期间，源于至少一个金属传导过孔结构51的去除部分的金属粒子可能涂污到后侧电介质层(112，114，116)的位于与半导体衬底10的界面以上(如图11中所示)、以下(在实际CMP加工步骤期间)的暴露后侧表面。扩散阻挡衬垫48的存在保证向电介质衬垫50V的暴露表面上涂污的金属粒子停止于在扩散阻挡衬垫48与电介质衬垫50V的剩余部分之间的界面。另外，在后侧电介质层(112，114，116)的至少一个后侧电介质层之中存在作为用于金属材料的扩散阻挡来工作的电介质材料层防止向后侧电介质层(112，114，116)的暴露表面上涂污的金属粒子经过后侧表面19进入半导体衬底10。具体而言，如果第一后侧电介质材料层112作为用于金属材料的扩散阻挡来工作，则后表面19和半导体衬底10的侧壁表面由阻止金属材料向半导体衬底10中扩散的材料邻接地密封。因此，第一示例半导体结构不受后侧金属污染影响或者显著减少后侧金属污染风险。在平坦化之后，后侧电介质层(112，114，116)、至少一个金属传导过孔结构51和扩散阻挡衬垫48的暴露表面在相互之间基本上平坦。
参照图12，后侧钝化层120可以沉积于后侧电介质层(112，114，116)和至少一个金属传导过孔结构51的表面上。后侧钝化层120可以包括阻止杂质材料和潮湿进入下层结构的电介质材料。例如，后侧钝化层120可以包括氮化硅层。后侧钝化层120的厚度可以从100nm至2微米并且通常从200微米至500微米，但是也可以运用更少和更大厚度。至少一个开口可以形成于后侧钝化层120中，并且后侧金属焊盘122可以形成于至少一个开口的每个开口中以经过后侧钝化层120提供电传导路径。至少一个后侧金属焊盘122的每个后侧金属焊盘可以接触金属接触过孔结构51。至少一个后侧金属焊盘122包括金属，诸如铜、镍、铝或者其合金或者组合。至少一个后侧金属焊盘122中的每个后侧金属焊盘可以是C4焊盘，C4球可以随后键合于该C4焊盘上。
至少一个金属接触过孔结构51的每个金属接触过孔结构是至少从半导体衬底10的前表面11向后表面19竖直延伸的传导贯穿衬底过孔(TSV)结构。可以随后例如通过向至少一个后侧金属焊盘122和位于装配衬底上的金属焊盘键合C4球124来向半导体衬底10的后侧键合装配结构(未示出)。可以执行与装配结构的键合而未在晶片级切分操纵衬底10和半导体衬底10的组件，或者可以在沿着与个别半导体芯片的边界对应的切分通道切分操纵衬底10和半导体衬底10的组件之后执行与装配结构的键合。一旦经过C4球124向半导体衬底10键合装配结构，则可以例如通过分裂或者通过溶解粘合层88来从半导体衬底10、C4球124的阵列和装配衬底的组件分离操纵衬底90。如果分裂掉操纵衬底90，则可以运用本领域已知方法来去除粘合层88的残留材料。
参照图13，可以通过沉积电介质衬垫50V而未去除邻接扩散阻挡层48L的水平部分来从图3的第一示例半导体结构派生根据本公开内容第二实施例的第二示例半导体结构。换而言之，在本公开内容的第二实施例中省略将去除邻接扩散阻挡层48L的水平部分的各向异性蚀刻。第二实施例的电介质衬垫50V具有与在第一实施例中相同的厚度和组成，并且可以运用与在第一实施例中相同的方法来形成。因此，电介质衬垫50V直接形成于邻接扩散阻挡层48L的内侧壁上。
参照图14，通过用传导材料填充至少一个沟槽49的每个沟槽来在至少一个沟槽49中形成金属传导过孔结构51。传导材料可以具有与在第一实施例中相同的组成并且可以运用与在第一实施例中相同的方法来沉积。通过平坦化工艺去除在下互连级结构(20，30，40，22，24，32，34，42，44)的最上表面上沉积的过量传导材料。平坦化工艺可以运用化学机械平坦化、凹陷蚀刻或者其组合。可以用于至少一个金属传导过孔结构51的材料包括Cu、W、CoW、CoWP、Au、Al和Ag。此外，至少一个金属衬垫(未示出)可以可选地沉积于电介质衬垫50V与至少一个金属传导过孔结构51之间。可以用于金属衬垫的材料包括TiN、TaN、WN、TiAlN和TaCN。
在平坦化工艺期间，从下互连级结构(20，30，40，22，24，32，34，42，44)的位于前表面11以上的最上表面去除电介质衬垫50V的水平部分。另外，从下互连级结构(20，30，40，22，24，32，34，42，44)的最上表面以上去除邻接扩散阻挡层48L的水平部分。由于邻接扩散阻挡层48L的水平部分仅存在于下互连级结构(20，30，40，22，24，32，34，42，44)以上和填充的沟槽的底部，所以在平坦化步骤期间去除邻接扩散阻挡层48L的位于前表面11以上的所有水平部分。由于在平坦化步骤期间也去除至少一个传导过孔结构51的部分，所以在初始形成金属传导过孔结构51之后并且与去除至少一个金属传导过孔结构51的上端部分并行去除邻接扩散阻挡层48L的水平部分。
邻接扩散阻挡层48L在平坦化步骤之后的剩余部分在这里称为扩散阻挡衬垫48。电介质衬垫50V的嵌入于半导体衬底10和下互连级结构(20，30，40，22，24，32，34，42，44)中的剩余部分在这里称为嵌入式电介质衬垫50W，即嵌入的电介质衬垫。下互连级结构(20，30，40，22，24，32，34，42，44)、扩散阻挡衬垫48、嵌入式电介质衬垫50W和至少一个金属传导过孔结构51的最上表面在相互之间基本上平坦。
参照图15，平坦互连级电介质层50X可以沉积于下互连级结构(20，30，40，22，24，32，34，42，44)、扩散阻挡衬垫48、嵌入式电介质衬垫50W和至少一个金属传导过孔结构51的平坦最上表面上。平坦互连级电介质层50X可以包括用于第一实施例的任何上互连级电介质层(50L，60，70)的任何电介质材料。可以运用本领域已知方法在平坦互连级电介质层50X中形成至少一个电介质衬垫级金属互连结构52。平坦互连级电介质层50X是具有与至少一个金属传导过孔结构51和扩散阻挡衬垫48接触的共面水平表面的互连级电介质层。
参照图16，可以对第二示例半导体结构执行图6-图12的加工步骤。扩散阻挡衬垫48的存在保证在图11的工艺步骤期间(即在在平坦化步骤中去除后侧电介质层(112，114，116)的在至少一个金属传导过孔结构51以上的部分和至少一个金属传导过孔结构51的上部分期间)在向电介质衬垫50W的暴露表面上涂抹的金属粒子停止于在扩散阻挡衬垫48与电介质衬垫50W的剩余部分之间的界面。另外，在后侧电介质层(112，114，116)中的至少一个后侧电介质层之中存在作为用于金属材料的扩散阻挡来工作的电介质材料层防止向后侧电介质层(112，114，116)的暴露表面上涂污的金属粒子在这一平坦化步骤期间经过后侧表面19进入半导体衬底10。因此，第二示例实施例半导体结构不受后侧金属污染影响或者显著减少后侧金属污染风险。
尽管已经关于本公开内容的优选实施例具体示出并且描述本公开内容，但是本领域技术人员将理解可以进行在形式和细节上的前述和其它改变而未脱离本公开内容的精神实质和范围。因此旨在于本公开内容不限于描述和图示的确切形式和细节而是落入所附权利要求的范围内。

Claims (31)

1.一种半导体结构，包括半导体衬底和嵌入于其中的贯穿衬底过孔(TSV)结构，其中所述TSV结构包括：
扩散阻挡衬垫(48)，所述扩散阻挡衬垫包括传导材料并包括外侧壁，所述外侧壁接触所述半导体衬底内的孔周围的邻接侧壁的全部的半导体表面；
电介质衬垫(50V)，接触所述扩散阻挡衬垫的内侧壁；以及
金属传导过孔结构(51)，横向接触所述电介质衬垫。
2.根据权利要求1所述的半导体结构，其中所述扩散阻挡衬垫包括传导金属氮化物。
3.根据权利要求2所述的半导体结构，其中所述传导金属氮化物选自于TiN、TaN、WN、TiAlN和TaCN。
4.根据权利要求1所述的半导体结构，其中所述扩散阻挡衬垫包括单质金属。
5.根据权利要求1所述的半导体结构，其中所述扩散阻挡衬垫是从CoW合金和CoWP合金中选择的可电镀材料。
6.根据权利要求1所述的半导体结构，还包括：
至少一个半导体器件(12)，位于所述半导体衬底的第一表面(11)上；以及
扩散阻挡层，位于所述半导体衬底的第二表面(19)上，其中所述第二表面位于所述第一表面的相对侧上。
7.根据权利要求6所述的半导体结构，其中所述扩散阻挡层包括阻止金属材料扩散的电介质材料。
8.根据权利要求7所述的半导体结构，其中所述扩散阻挡层包括从包含金属氧化物的电介质材料、碳化硅、SiNxCyHz和氮化硅中选择的材料，其中x、y和z的每个值独立地从0至1。
9.根据权利要求6所述的半导体结构，其中所述电介质衬垫包括具有远水平表面(50D)和近水平表面(50P)的水平部分，其中所述远水平表面比所述近水平表面更远离所述至少一个半导体器件，并且所述远水平表面与所述金属传导过孔结构的端表面共面。
10.根据权利要求1所述的半导体结构，还包括具有与所述金属传导过孔结构和所述扩散阻挡衬垫接触的共面水平表面的互连级电介质层(50X)。
11.根据权利要求1所述的半导体结构，还包括：
至少一个半导体器件(12)，位于所述半导体衬底的第一表面(11)上；以及
金属焊盘(122)，传导地连接到所述金属传导过孔结构并且与所述半导体衬底的第二表面比与所述第一表面更邻近，其中所述第二表面位于所述第一表面的相对侧上。
12.根据权利要求11所述的半导体结构，还包括向所述金属焊盘键合的C4球(124)。
13.一种半导体结构，包括半导体衬底和嵌入于其中的贯穿衬底过孔(TSV)结构，其中所述TSV结构包括：
扩散阻挡衬垫(48)，接触所述半导体衬底内的孔周围的邻接侧壁的全部的半导体表面；
电介质衬垫(50V)，接触所述扩散阻挡衬垫的内侧壁；
至少一个半导体器件(12)，位于所述半导体衬底的第一表面(11)上；以及
金属传导过孔结构(51)，横向接触所述电介质衬垫，其中所述电介质衬垫包括具有远水平表面(50D)和近水平表面(50P)的水平部分，其中所述远水平表面比所述近水平表面更远离所述至少一个半导体器件，并且所述远水平表面与所述金属传导过孔结构的端表面共面。
14.根据权利要求13所述的半导体结构，其中所述扩散阻挡衬垫包括传导材料。
15.根据权利要求13所述的半导体结构，进一步包括：
扩散阻挡层，位于所述半导体衬底的第二表面(19)上，其中所述第二表面位于所述第一表面的相对侧上。
16.根据权利要求13所述的半导体结构，其中所述扩散阻挡衬垫包括阻止金属材料扩散的电介质材料。
17.根据权利要求16所述的半导体结构，其中所述扩散阻挡衬垫包括包含金属氧化物的电介质材料。
18.根据权利要求17所述的半导体结构，其中所述包含金属氧化物的电介质材料包括HfO2、ZrO2、La2O3、A12O3、TiO2、SrTiO3、LaA1O3、Y2O3、HfOxNy、ZrOxNy、La2OxNy、Al2OxNy、TiOxNy、SrTiOxNy、LaA1OxNy、Y2OxNy、其硅酸盐及其合金及其非化学当量变体中的至少一种，其中x的每个值独立地从0.5至3，并且y的每个值独立地从0至2。
19.根据权利要求16所述的半导体结构，其中所述扩散阻挡衬垫包括从碳化硅和SiNxCyHz中选择的材料，其中x、y和z的每个值独立地从0至1。
20.根据权利要求16所述的半导体结构，其中所述扩散阻挡衬垫包括氮化硅。
21.一种半导体结构，包括半导体衬底和嵌入于其中的贯穿衬底过孔(TSV)结构，其中所述TSV结构包括：
扩散阻挡衬垫(48)，接触所述半导体衬底内的孔周围的邻接侧壁的全部的半导体表面；
电介质衬垫(50V)，接触所述扩散阻挡衬垫的内侧壁；
金属传导过孔结构(51)，横向接触所述电介质衬垫；以及
互连级电介质层(50X)，具有与所述金属传导过孔结构和所述扩散阻挡衬垫接触的共面水平表面。
22.根据权利要求21所述的半导体结构，其中所述扩散阻挡衬垫包括传导材料。
23.根据权利要求21所述的半导体结构，其中所述扩散阻挡衬垫包括阻止金属材料扩散的电介质材料。
24.根据权利要求21所述的半导体结构，进一步包括：
至少一个半导体器件(12)，位于所述半导体衬底的第一表面(11)上；以及
扩散阻挡层，位于所述半导体衬底的第二表面(19)上，其中所述第二表面位于所述第一表面的相对侧上。
25.一种形成半导体结构的方法，包括：
在半导体衬底的第一表面(11)上形成至少一个半导体器件(12)；
在所述半导体衬底中形成沟槽(49)，其中所述半导体衬底的半导体材料暴露于所述沟槽的侧壁；
在所述侧壁上直接形成扩散阻挡衬垫(48)，所述扩散阻挡衬垫接触所述沟槽周围的邻接侧壁的全部的半导体表面；
通过用传导填充材料填充所述沟槽来形成金属传导过孔结构；以及
减薄所述半导体衬底，其中所述金属传导过孔结构在所述减薄之后至少从所述第一表面向所述半导体衬底的第二表面(19)延伸，其中所述第二表面位于所述第一表面的相对侧上。
26.根据权利要求25所述的方法，其中通过沉积邻接扩散阻挡层(48L)并且随后从所述第一表面以上去除所述邻接扩散阻挡层的水平部分来形成所述扩散阻挡衬垫，其中所述扩散阻挡衬垫包括所述邻接扩散阻挡层的剩余竖直部分。
27.根据权利要求26所述的方法，其中通过各向异性蚀刻来去除所述邻接扩散阻挡层的所述水平部分，并且在所述各向异性蚀刻之后暴露所述沟槽的底表面。
28.根据权利要求26所述的方法，其中在形成所述金属传导过孔结构之后与去除所述金属传导过孔结构的端部分并行地去除所述邻接扩散阻挡层的所述水平部分。
29.根据权利要求26所述的方法，还包括形成电介质衬垫(50V)，其中所述电介质衬垫直接形成于所述邻接扩散阻挡层的内侧壁或者所述扩散阻挡衬垫的内侧壁上，并且所述金属传导过孔结构直接形成于所述电介质衬垫上。
30.根据权利要求25所述的方法，还包括：
在所述第二表面上形成金属焊盘(122)，其中所述金属焊盘传导地连接到所述金属传导过孔结构；并且
向所述金属焊盘键合C4球(124)。
31.根据权利要求25所述的方法，还包括在所述半导体衬底的所述第二表面上直接形成扩散阻挡层(112)，其中所述扩散阻挡层包括阻挡金属材料扩散的材料。
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