TWI604590B - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

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Publication number
TWI604590B
TWI604590B TW105120948A TW105120948A TWI604590B TW I604590 B TWI604590 B TW I604590B TW 105120948 A TW105120948 A TW 105120948A TW 105120948 A TW105120948 A TW 105120948A TW I604590 B TWI604590 B TW I604590B
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Taiwan
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substrate
material layer
semiconductor device
trench
layer
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TW105120948A
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English (en)
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TW201737455A (zh
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林柏均
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南亞科技股份有限公司
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    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
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Description

半導體裝置及其製造方法
本揭露內容係有關於一種半導體裝置及其製造方法，且特別是指一種具有環繞矽穿孔電極之環狀結構的半導體裝置及其製造方法。
隨著半導體產業追求更高性能的需求增加，包裝技術已從二維(2D)發展至三維(3D)的晶片封裝，從而進一步提高積體電路裝置中，電路的密度及性能。
在3D晶片封裝中，兩個晶片藉由導電墊結合在一起，且隨後形成的矽穿孔(TSV)電極能連結第一晶片和第二晶片上的導電墊。矽穿孔電極通常由銅或其他導電材料所形成，以提供導電墊間電氣連結。然而，由於矽穿孔電極的銅或其他導電材料，與包圍矽穿孔電極之基板的材料間，熱膨脹係數差異甚大，故會產生熱應力，進而導致結構不穩定或產生缺陷。因此，需要進一步改善，以解決上述之問題，並提高半導體裝置的性能。
根據本發明之一些實施例，提供一種半導體裝置，其包含基板，此基板具有前側與後側，且後側具有導體於其上。此半導體裝置還包含孔洞及溝渠於基板之中，且孔洞穿透基板並暴露導體，而溝渠則延伸自後側至基板內部，並環繞孔洞。此半導體裝置更包含第一材料層於孔洞之中，並與導體電氣相連；以及第二材料層於溝渠之中。
根據本發明之一些實施例，半導體裝置更包含襯層於孔洞之側壁之上。
根據本發明之一些實施例，第二材料層與一部分襯層之側壁直接接觸。
根據本發明之一些實施例，第二材料層包含氧化矽、氮化矽、氮氧化矽、銅、鎢或其組合。
根據本發明之一些實施例，一部分的基板完全分離溝渠與孔洞。
根據本發明之一些實施例，半導體裝置更包含第二襯層於溝渠之側壁之上。
根據本發明之一些實施例，半導體裝置更包含凸塊於基板之後側之上。
根據本發明之一些實施例，凸塊、第一材料層及第二材料層係互相直接接觸，且係由一相同材料所組成。
根據本發明之一些實施例，半導體裝置更包含凸塊下金屬層於凸塊與基板後側之間。
根據本發明之一些實施例，凸塊下金屬層之底表面與第一材料層和第二材料層的頂表面係共平面。
根據本發明之一些實施例，凸塊及第二材料層係由相同之材料所製成，以形成插入溝渠的整合凸塊。
根據本發明之一些實施例，第一材料層及第二材料層的材料係由一材料所組成，其獨立選自一組合，包含：鈦、鋁、銅、鉻、銀、鎢、氧化矽及其組合。
根據本發明之一些實施例，導體係一結構，選自一組合，包含：內連線結構、金屬層、閘極電極、前側矽穿孔電極及其組合。
根據本發明之一些實施例，溝渠與凸塊由上而視具有一形狀，獨立選自一組合，包含：圓形、正方形及正多邊形。
根據本發明之一些實施例，提供一種製造半導體裝置之方法。此方法包含：接收基板，此基板包含後側與前側，且前側具有導體於其上；形成孔洞於基板之中，且暴露導體；形成溝渠，延伸自後側至基板內部，並環繞通孔；形成第一材料層於孔洞之中；以及形成第二材料層於溝渠之中。
根據本發明之一些實施例，此方法更包含形成凸塊於基板後側之上。
根據本發明之一些實施例，此方法更包含形成凸塊下金屬層於基板後側與凸塊之間。
根據本發明之一些實施例，形成凸塊與形成第二材料層係同時進行，且凸塊與第二材料層係由一相同的材料所製成。
根據本發明之一些實施例，形成第一材料層、形成第二材料層及形成凸塊係同時進行，且第一材料層、第二材料層和凸塊係由一相同的材料所製成。
根據本發明之一些實施例，形成溝渠係蝕刻一部分與空洞分離的基板。
10‧‧‧方法
12‧‧‧步驟
14‧‧‧步驟
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30‧‧‧方法
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50‧‧‧方法
52‧‧‧步驟
54‧‧‧步驟
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60‧‧‧方法
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66‧‧‧步驟
68‧‧‧步驟
70‧‧‧步驟
80‧‧‧方法
82‧‧‧步驟
100‧‧‧半導體裝置
110‧‧‧基板
112‧‧‧後側
114‧‧‧前側
120‧‧‧內連線結構
122‧‧‧層間介電層
130‧‧‧電晶體
132‧‧‧淺溝槽隔離
140‧‧‧導體
142‧‧‧晶種層
144‧‧‧襯層
144a‧‧‧側壁上部
150‧‧‧半導體裝置
152‧‧‧溝渠
160‧‧‧材料層
162‧‧‧環狀結構
162a‧‧‧下部
170‧‧‧凸塊下金屬層
180‧‧‧凸塊
190‧‧‧迴焊錫球凸塊
200‧‧‧半導體裝置
210‧‧‧基板
212‧‧‧後側
214‧‧‧前側
220‧‧‧內連線結構
222‧‧‧層間介電層
230‧‧‧電晶體
232‧‧‧淺溝槽隔離
240‧‧‧第一材料層
242‧‧‧晶種層
244‧‧‧襯層
250‧‧‧孔洞
252‧‧‧溝渠
260‧‧‧第二材料層
270‧‧‧凸塊下金屬層
280‧‧‧凸塊
290‧‧‧迴焊錫球凸塊
300‧‧‧半導體裝置
310‧‧‧光阻遮罩
340‧‧‧第一材料層
370‧‧‧凸塊下金屬層
380‧‧‧凸塊
380a‧‧‧第一部分
380b‧‧‧第二部分
390‧‧‧迴焊錫球凸塊
400‧‧‧半導體裝置
410‧‧‧光阻遮罩
452‧‧‧溝渠
460‧‧‧氧化物層
462‧‧‧第二氧化物層
470‧‧‧凸塊下金屬層
480‧‧‧凸塊
480a‧‧‧第一部分
480b‧‧‧第二部分
490‧‧‧迴焊錫球凸塊
500‧‧‧半導體裝置
510‧‧‧光阻遮罩
580‧‧‧凸塊
580a‧‧‧第一部分
580b‧‧‧第二部分
590‧‧‧迴焊錫球凸塊
L162‧‧‧長度
L170‧‧‧長度
L260‧‧‧長度
L270‧‧‧長度
當結合隨附圖式閱讀時，自以下詳細描述將很好地理解本發明之態樣。應注意，根據工業中的標準實務，圖式中各特徵並非按比例繪製。事實上，出於論述清晰之目的，可任意增加或減小圖示特徵之尺寸。
第1圖係繪示根據一些實施例，一種用於形成半導體裝置之方法的示意流程圖；第2A圖至第2E圖係繪示根據一些實施例，一種半導體裝置於製程中各階段的示意剖面圖；第3圖係繪示根據一些實施例，一種用於形成半導體裝置之方法的示意流程圖；第4A圖至第4E圖係繪示根據一些實施例，一種半導體裝置於製程中各階段的示意剖面圖；第5A圖係繪示根據一些實施例，一種用於形成半導體裝置之方法的示意流程圖；第5B圖係繪示根據一些實施例，一種用於形成半導體裝置之方法的示意流程圖； 第6A圖至第6C圖係繪示根據一些實施例，一種半導體裝置於製程中各階段的示意剖面圖；第7A圖至第7E圖係繪示根據一些實施例，一種半導體裝置於製程中各階段的示意剖面圖；第8圖係繪示根據一些實施例，一種用於形成半導體裝置之方法的示意流程圖；第9A圖至第9B圖係繪示根據一些實施例，一種半導體裝置於製程中各階段的示意剖面圖；第10A圖至第11B圖係繪示根據一些實施例，一種半導體元件由上而視的示意形狀。
以下揭示內容提供許多不同實施例或實例，以便實施本發明之不同特徵。下文描述組件及排列之特定實例以簡化本發明。當然，此等實例僅為示例且並不意欲為限制性。舉例而言，以下描述中在第二特徵上方或第二特徵上形成第一特徵可包括以直接接觸形成第一特徵及第二特徵的實施例，且亦可包括可在第一特徵與第二特徵之間形成額外特徵以使得第一特徵及第二特徵可不處於直接接觸的實施例。另外，本發明可在各實例中重複元件符號及/或字母。此重複係出於簡明性及清晰之目的，且本身並不指示所論述之各實施例及/或配置之間的關係。
進一步地，為了便於描述，本文可使用空間相對性術語(諸如「之下」、「下方」、「下部」、「上方」、 「上部」及類似者)來描述諸圖中所圖示一個元件或特徵與另一元件(或多個元件)或特徵(或多個特徵)之關係。除了諸圖所描繪之定向外，空間相對性術語意欲包含使用或操作中裝置之不同定向。設備可經其他方式定向(旋轉90度或處於其他定向)且因此可同樣解讀本文所使用之空間相對性描述詞。
在半導體結構的製程中，半導體結構的穩定運作是非常重要的。因此，應避免任何可能造成結構不穩定的因素。在半導體結構中，其中一個結構不穩定的現象可能發生在矽穿孔(through silicon via，TSV)電極與鄰近的半導體基板之間。通常，矽穿孔電極與半導體基板間的巨大熱膨脹係數不匹配可能造成矽穿孔電極的剝離，因而降低半導體裝置的結構穩定性。
更詳細地說，在傳統的半導體裝置中，銅或其他導電材料可能填充於矽穿孔中，以形成矽穿孔電極並提供電氣連結予位於晶圓兩側上之導電元件(例如：電路、電晶體和內連線結構)。值得注意的是，銅或其他導電金屬，具有遠高於矽的熱膨脹係數。舉例來說，銅的熱膨脹係數大約為16.5ppm/℃，而矽的熱膨脹係數卻只有2.6ppm/℃。在沉積銅之後或於後續的熱處理(例如：無鉛迴流焊接製程、測試或使用)中，如此大的熱膨脹係數差異可能造成顯著的熱應力於矽與銅之間。此外，若相鄰的矽穿孔電極更為接近，則此熱應力可能更加嚴重。上述之熱應力可能造成各種 問題，例如：薄膜剝離、半導體基板的裂痕和半導體裝置效能的下降。
為了解決由半導體基板(例如：矽基板)與矽穿孔電極(例如：銅矽穿孔電極)間的熱應力所造成之半導體裝置的結構不穩定，本發明提供一種降低半導體基板與矽穿孔電極間熱應力的方法。在此方法中，一環狀結構置於半導體基板的後側(back side)，並環繞矽穿孔電極。此處所稱之「後側」指的是位於具有電路於其上之前側(front side)的另一側。環狀結構可直接接觸矽穿孔電極或與其分離。此外，環狀結構可包含絕緣材料或導電材料。另外，環狀結構可與其他後側層(例如：凸塊下金屬層或凸塊)結合成一體或具有與後側層不同的材料。此環狀結構可降低或消除上述矽穿孔電極與半導體基板或兩相鄰矽穿孔電極間的熱應力，以解決上述裂痕或剝離的問題。
在本發明中，六個半導體裝置100、150、200、300、400、500及其製造方法10、30、50、60、80分別描述於六個實施例中。半導體裝置100、150、200、300、400、500間的差異可能為下列因素之一或其組合：環狀結構與矽穿孔電極間的關係(直接接觸或分離)；填充於環狀結構中的材料(導電材料或絕緣材料)；環狀結構與其他後側層的關係(結合或分開)。值得注意的是，本發明有關實施例之描述不可用於限縮權利請求項之精神與範圍。
在實施例一和實施例二中，半導體裝置100、150(第2D圖和第2E圖)係藉由方法10，形成自具有已存在 之導體(例如：前側矽穿孔電極)於其中的基板(第2A圖)。半導體裝置100、150包含與矽穿孔電極直接接觸的環狀結構於基板之中。以下先介紹實施例一。
實施例一：
請參照第1圖及第2A圖，方法10起始於步驟12，其係接收基板。如第2A圖所示，基板110包含前側114及後側112，前側114更包含電晶體130、淺溝槽隔離(STI)132、層間介電層(ILD)122及內連線結構120。此外，導體140置於基板110之中，且與內連線結構120電氣相連。
請再參照第2A圖，基板110可能包含主體矽基板(bulk silicon substrate)。或者，基板110可能包含基本半導體(例如：晶體結構之矽或鍺)或化合物半導體，例如：鍺化矽、碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦、銻化銦或其任意之組合。基板110亦可包含絕緣層覆矽(silicon-on-insulator，SOI)基板。一般來說，SOI基板包含一層具有半導體材料(例如：矽、鍺、鍺化矽、絕緣層覆鍺化矽或其任意之組合)的層。
此外，電晶體130可能包含閘極電極、源極/汲極區域、淺摻雜汲極(LDD)區域、N井(N-well)、P井(P-well)或其組合。舉例來說，N井可能包含N型摻雜質，例如：磷(P)、砷(As)、銻(Sb)、鉍(Bi)、硒(Se)、碲(Te)及其任意之組合。而P井可能包含P型摻雜質，例如：硼(B)、二氟化硼(BF2)或其任意之組合。為了簡潔之目的，本揭露內容未繪示或進一步描述上述電晶體130中的各種結構。
此外，內連線結構120及導體140可為任何適合的半導體導電元件。舉例來說，內連線結構120及導體140可能為但不侷限於：內連線結構、多晶矽閘極、金屬閘極、接點、前側矽穿孔電極或其組合。在本實施例中，導體140為前側矽穿孔電極，其於後述形成環狀結構之前便已存在。內連線結構120及導體140的材料隨著其用途而異。一般而言，內連線結構120及導體140的材料可各自含有一材料選自一組合，其包含但不局限於：銀(Ag)、銅(Cu)、鎢(W)、鈦(Ti)、鉭(Ta)、鋁(Al)、鎳(Ni)、釕(Ru)、鈀(Pd)、鉑(Pt)、錳(Mn)、氮化鎢(WN)、氮化鈦(TiN)、氮化鉭(TaN)、氮化鋁(AlN)、矽化鎢(WSi)、氮化鉬(MoN)、矽化鎳(Ni2Si)、矽化鈦(TiSi2)、鋁化鈦(TiAl)、砷(As)摻雜之多晶矽、氮化鋯(ZrN)、TaC、TaCN、TaSiN、TiAlN及其任意之組合。
在一些實施例中，半導體裝置100更包含晶種層142及襯層144。晶種層142位於導體140的上表面及側壁之上，而襯層144則於晶種層142的上表面及側壁之上。換言之，晶種層142及襯層144覆蓋導體140。在一些實施例中，晶種層142包含銅或其他導電材料。在一些實施例中，襯層144可能包含任何適合的材料，例如但不侷限於：四乙氧基矽烷(TEOS)、氮化矽、氮氧化矽、氧化矽及其組合。
請參照第1圖及第2B圖，方法10繼續進行至步驟14，其係從後側112削薄基板110以暴露襯層144。基板 110的削薄製程可為任何適合的製程，例如：化學機械研磨(CMP)、蝕刻或其組合。
在暴露襯層144之後，方法10繼續進行至步驟16，其係自基板110的後側112形成溝渠152。溝渠152位於基板110之中且環繞導體140。在一些實施例中，藉由微影蝕刻製程來形成具有孔洞(未標示)之光阻遮罩(未標示)。接著，藉由蝕刻製程(例如：濕蝕刻、乾蝕刻或電漿蝕刻)以形成溝渠152。微影蝕刻製程可能包含形成光阻層(未標示)於基板110的後側112上、暴露光阻層以形成圖案(未標示)、進行曝光後烘烤製程及圖案化光阻層以形成光阻遮罩。
如第2B圖所示，由俯視方向來看，溝渠152具有圓形形狀(第10A圖)。溝渠152暴露襯層144之側壁之上部。值得注意的是，溝渠152僅暴露襯層144之側壁之上部，而非整個襯層144之側壁。也就是說，溝渠152形成於基板110之緊鄰於後側112之上部，而非穿透基板110。在一些實施例中，溝渠152可能由多個分塊所組成(如第10B圖所示)。在一些實施例中，由上而視，溝渠152可能具有連續正方形形狀(如第10C圖所示)、不連續正方形形狀(如第10D圖所示)或正多邊形形狀。在其他實施例中，溝渠152可能暴露淺溝槽隔離132。
請參照第1圖及第2C圖，方法10繼續進行至步驟18，其係沉積材料層160於基板110之後側112之上，其中，一部分的材料層160填入溝渠152之中，以形成環狀結構162。在一些實施例中，材料層160的材料係選自一組合， 其包含氧化矽、氮化矽、氮氧化矽及其組合。在一些實施例中，由另一沉積製程形成環狀結構162，且其材料包含銅、鎢、其他導電材料或其組合。
在形成環狀結構162之後，進行一薄化製程，例如：化學機械研磨、研磨或蝕刻，以自後側112削薄基板110，以暴露導體140而保留環狀結構162於基板110之後側112。如第2C圖所示，沉積材料層160的方法可為任何適合的製程，例如但不侷限於：化學氣相沉積(CVD)、物理氣相沉積(PVD)、原子層沉積(ALD)、電漿化學氣相沉積(PECVD)或其組合。值得注意的是，環狀結構162係直接接觸於襯層144的側壁上部(即144a)。在一些實施例中，第2B圖所示之結構不包含襯層144，因此環狀結構162係直接接觸於晶種層142的側壁上部。在另一些實施例中，第2B圖所示之結構不包含襯層144及晶種層142，因此環狀結構162係直接接觸於導體140的側壁上部。因此，環狀結構162能於熱處理時，降低或消除前述之導體140與基板110間之熱應力。從而解決結構不穩定的問題，例如：導體140的剝離及自鄰近於後側112的導體140與基板110界面所形成之裂痕。
請參照第1圖及第2D圖，方法10繼續進行至步驟20，其係形成凸塊下金屬層(UBM)170及凸塊180於基板110之後側112上。其中，凸塊下金屬層170及凸塊180與導體140電氣相連。如第2D圖所示，凸塊下金屬層170係形成於基板110之後側112上。其中，凸塊下金屬層170覆蓋整 個環狀結構162及導體140。接著，形成凸塊180於凸塊下金屬層170之上。最後，形成迴焊錫球凸塊(reflowed solder bump)190於凸塊180之上。至此，具有環狀結構162的半導體裝置100便形成，而後續的製程(例如：黏結晶圓)可繼續進行。在一些實施例中，凸塊下金屬層170係濺鍍或電鍍至基板110之後側112之上。在一些實施例中，凸塊下金屬層170係由單層或多層所組成，其材料選自一組合，其包含：鉻、鈦、銅、銀及其組合。在一些實施例中，凸塊180及迴焊錫球凸塊190可藉由任何適合的製程(例如：蒸鍍、濺鍍、電鍍或印刷)形成於凸塊下金屬層170之上。
實施例二：
不同於實施例一中的半導體裝置100，可調整一些參數以符合設計需求，例如：環狀結構162的形狀、自襯層144之外側壁至環狀結構162之外側壁的長度(L162)及自襯層144之外側壁至凸塊下金屬層170之外側壁的長度(L170)。舉例來說，長度L170可能小於長度L162，使得凸塊下金屬層170覆蓋一部分或不覆蓋環狀結構162。在其他實施例中，在半導體裝置150(第2E圖)中，從剖面方向來看，環狀結構162具有弧形形狀於其下部(即162a)。此外，半導體裝置150的形成方法及元件的材料與前述之半導體裝置100相同。值得注意的是，長度L170及長度L162之間的關係與環狀結構162的形狀不該侷限於半導體裝置100(第2D圖)及150(第2E圖)。
值得注意的是，半導體裝置100、150中的環狀結構162可降低或消除前述之位於導體(或矽穿孔電極)與基板110之間的熱應力。更詳細地說，導體140與基板110之後側112的介面將會被推向基板110之內部，而此處的熱應力小於接近後側112的熱應力。或者，環狀結構162的溝渠152能消除導體140與基板110間的熱應力以降低上述熱應力之程度。在一些實施例中，上述環狀結構162的形成(即步驟18)係進行於較低的溫度，例如：300℃、200℃、100℃或室溫，如此一來，溝渠152及後續形成的環狀結構162能降低或消除原先於降溫過程中，產生於導體140與基板110之間的熱應力，而不再次產生熱應力。因此，導體140與基板110間的熱應力能被降低或消除。
在實施例三中，半導體裝置200(第4E圖)係藉由方法30(第3圖)，形成自不具有導體(例如：前側矽穿孔電極)於其中的基板(第4A圖)。半導體裝置200包含與矽穿孔電極分離的環狀結構於基板之中，其中，此環狀結構包含導電材料或絕緣材料。
實施例三：
請參照第3圖及第4A圖，方法30起始自步驟32，其係接收基板210。如第4A圖所示，基板210包含前側214及後側212。其中，此前側214更包含電晶體230、淺溝槽隔離(STI)232、層間介電層(ILD)222、內連線結構220。不同於基板110(第2A圖)，基板210不具有與內連線結構220電氣相連之導體於其中。也就是說，基板210不包含前 側矽穿孔電極於其中。由於有關於基板210的結構或元件與前述之有關於基板110的結構與元件(第2A圖)相似，為了簡潔之目的而不在此重複敘述。
請參照第3圖及第4B圖，方法30繼續進行至步驟34，其係自後側212形成孔洞250於基板210中。其中，此孔洞250穿透基板210並暴露內連線結構220。接著進行步驟36，其係自後側212形成溝渠252。其中，此溝渠252位於基板210之中並環繞孔洞250。在本實施例中，步驟34及步驟36係同步進行，藉由微影蝕刻製程與蝕刻製程，同時形成孔洞250及溝渠252。微影蝕刻製程及蝕刻製程類似於前述之形成溝渠152(第2B圖)之製程，故不在此贅述。
請參照第3圖及第4C圖，方法30繼續進行至步驟38，其係形成襯層244及晶種層242於基板210之後側212及孔洞250和溝渠252的側壁之上。如第4C圖所示，襯層244及晶種層242可藉由任何適合的製程(例如：CVD、PVD、PECVD、濺鍍及其組合)，沉積於後側212、孔洞250和溝渠252之下表面及側壁之上。值得注意的是，晶種層242係用於改善襯層244與隨後形成之第一導電層之間的附著結合度。襯層244及晶種層242的材料類似於前述之襯層144及晶種層142(第2A圖)，故不在此贅述。此外，一部分的孔洞250之底部未被襯層244及晶種層242覆蓋，使得後續填入孔洞250之第一導電層與內連線結構220形成電氣連接。
請參照第3圖及第4D圖，方法30繼續進行至步驟40，其係形成第一材料層240於孔洞250之中。接著，進 行步驟42以形成第二材料層260於溝渠252之中。在本實施例中，第一材料層240及第二材料層260係依次形成並由不同的材料所形成，其材料可選自一組合，其包含：鈦、鋁、銅、鉻、銀、鎢、氧化矽及其組合。在本實施例中，第一材料層240係由導電材料所製成，以形成矽穿孔電極。第一材料層240及第二材料層260可藉由沉積(例如：CVD、PVD、PECVD或濺鍍)或磊晶的方式形成。在一些實施例中，第一材料層240及第二材料層260係同時形成並由相同的材料所形成。在一些實施例中，由上而視，第二材料層260具有圓形或正方形形狀，分別如第10A圖及第10C圖所示。此外，此圓形或正方形形狀可為不連續的圖形，分別如第10B圖及第10D圖所示。在其他實施例中，由上而視，第二材料層260具有連續或不連續的正多邊形形狀。
請參照第3圖及第4E圖，方法30繼續進行至步驟44，其係形成凸塊下金屬層(UBM)270及凸塊280於基板210之後側212之上。如第4E圖所示，凸塊下金屬層270係形成於基板210之後側212之上，凸塊280係形成於凸塊下金屬層270之上，且迴焊錫球凸塊290係形成於凸塊280之上。凸塊下金屬層270、凸塊280及迴焊錫球凸塊290的材料及形成方式類似於凸塊下金屬層170、凸塊180及迴焊錫球凸塊190(第2D圖)。值得注意的是，在形成凸塊280之前，可能先蝕刻掉一部分未被凸塊280所覆蓋的凸塊下金屬層270和/或晶種層242，以避免相鄰矽穿孔電極的不同凸塊下金屬層間形成電氣相連而造成短路的現象。或者，在形成凸 塊下金屬層270及凸塊280後，可能蝕刻掉一部分未被凸塊280所覆蓋的晶種層242和/或凸塊下金屬層270，以避免前述之短路情形。在本實施例中，自第一材料層240側壁上之襯層244之外側壁至第二材料層260之外側壁的長度(L260)與自第一材料層240側壁上之襯層244之外側壁至凸塊下金屬層270之外側壁的長度(L270)相同。在其他實施例中，距離L260可能大於或小於距離L270。至此，半導體裝置200已完成。在一些實施例中，由上而視，凸塊下金屬層270具有圓形或正方形形狀，分別如第11A圖及第11B圖所示。
在實施例四和實施例五中，半導體裝置300、400(第6C圖和第7E圖)係分別藉由方法50(第5A圖)、60(第5B圖)，形成自不具有或具有導體(例如：前側矽穿孔電極)於其中的基板。半導體裝置300、400包含與矽穿孔電極分離的環狀結構於基板之中，其中，此環狀結構與之後形成於其上之凸塊整合成一體，並具有凸塊下金屬層於凸塊與基板之間。以下將先介紹實施例四。
實施例四：
請參照第5A圖及第6A圖，方法50自方法30的步驟38(標誌為”B”)繼續進行至步驟52，其係形成第一材料層340於第4C圖的半導體裝置裡的孔洞250之中。如第6A圖所示，在形成第一材料層340於孔洞250之前，藉由前述之微影蝕刻製程，先形成光阻遮罩310於基板210的後側212之上。光阻遮罩310覆蓋溝渠252且未填入孔洞250之 中，因而使得後續的製程(例如：沉積或磊晶)能只形成與內連線結構220電氣相連的第一材料層340於孔洞250之中。在形成第一材料層340之後，移除光阻遮罩310以暴露溝渠252。
請參照第5A圖及第6B圖，方法50繼續進行至步驟54，其係沉積凸塊下金屬層(UBM)370於基板210之後側212上。其中，凸塊下金屬層370也覆蓋溝渠252的側壁。
請參照第5A圖及第6C圖，方法50繼續進行至步驟56，其係形成凸塊380於凸塊下金屬層370之上。其中，凸塊380插入溝渠252，因此，環狀結構(即填入一部分之凸塊380的溝渠252)與凸塊(即凸塊380)整合成一體。接著，進行後續的製程以形成迴焊錫球凸塊390於凸塊380之上，至此，半導體裝置300已形成。值得注意的是，在形成凸塊380之前，可蝕刻掉一部分未被凸塊380覆蓋的凸塊下金屬層370和/或晶種層242，以避免相鄰矽穿孔電極的不同凸塊下金屬層間形成電氣相連而造成短路的現象。或者，在形成凸塊下金屬層370及凸塊380之後，可能蝕刻掉一部分未被凸塊380所覆蓋之晶種層242和凸塊下金屬層370，以避免前述之短路現象。此外，凸塊380包含第一部分380a於溝渠252之中及第二部分380b於後側212之上。在一些實施例中，由上而視，第一部分380a具有圓形或正方形形狀，分別如第10A圖及第10C圖所示。此外，此圓形或正方形形狀可為不連續的圖形，分別如第10B圖及第10D圖所示。在其他實施例中，由上而視，第一部分380a具有連續或非連續 的正多邊形形狀。在一些實施例中，由上而視，第二部分380b具有圓形或正方形形狀，分別如第11A圖及第11B圖所示。
實施例五：
另一方面，在實施例五中，半導體裝置400大致上具有與實施例四中的半導體裝置300相同的結構。半導體裝置400係藉由方法60(第5B圖)，形成自一具有導體(例如：前側矽穿孔電極)於其中的基板。
請參照第5B圖及第7A圖，方法60自方法10的步驟14(標誌為”A”)繼續進行至步驟62，其係沉積氧化物層460於基板110之後側112之上，並進行薄化製成，以暴露導體140。在本實施例中，先形成氧化物層460於後側112之上，且覆蓋著襯層144。接著，進行薄化製程以去除一部分的氧化物層460、一部分的襯層144及一部分的晶種層142，已暴露導體140。在其他實施例中，先進行薄化製程以去除一部分的襯層144及一部分的晶種層142，以暴露導體140。接著，再沉積氧化物層460於後側112之上，且覆蓋著導體140。然後，再次進行薄化製程以暴露導體140。上述之薄化製程可能為化學機械研磨、蝕刻或其組合。
請參照第5B圖及第7B圖，方法60繼續進行至步驟64，其係形成環繞導體140的溝渠452於基板110之中。如第7B圖所示，光阻遮罩410係形成於後側112之上並覆蓋氧化物層460及導體140。其中，光阻遮罩410具有開孔(未標示)於溝渠452的正上方。光阻遮罩410可藉由前述 之微影蝕刻製程的方式來形成。接著，進行蝕刻製程(例如：濕蝕刻、乾蝕刻、電漿蝕刻及其組合)以去除一部分的氧化物層460及基板110，進而形成溝渠452。
請參照第5B圖及第7C圖，方法60繼續進行至步驟66，其係形成第二氧化物層462於溝渠452的側壁之上。如第7C圖所示，第二氧化物層462與氧化物層460直接接觸，以形成連續的氧化物層，進而提供基板110保護作用。在本實施例中，第二氧化物層462係由與氧化物層460相同的材料所形成，因此，氧化物層460及第二氧化物層462形成一整合層。在其他實施例中，第二氧化物層462可能包含雙層結構，其具有與前述之晶種層142及襯層144(第2A圖)相似的材料。
請參照第5B圖及第7D圖，方法60繼續進行至步驟68，其係沉積凸塊下金屬層(UBM)470於基板110之後側112上。其中凸塊下金屬層470也覆蓋第二氧化物層462的側壁。
請參照第5B圖及第7E圖，方法60繼續進行至步驟70，其係形成凸塊480於凸塊下金屬層470之上。其中，凸塊480插入溝渠452，因此，環狀結構(即填入一部分之凸塊480的溝渠452)與凸塊(即凸塊480)整合成一體。接著，進行後續的製程以形成迴焊錫球凸塊490於凸塊480之上，至此，半導體裝置400已形成。值得注意的是，在形成凸塊480之前，可蝕刻掉一部分未被凸塊480所覆蓋的凸塊下金屬層470，以避免相鄰矽穿孔電極的不同凸塊下金屬層間形 成電氣相連而造成短路的現象。或者，在形成凸塊480之後，可能蝕刻掉一部分未被凸塊480所覆蓋的凸塊下金屬層470，以避免前述之短路現象。此外，凸塊480包含第一部分480a於溝渠452之中及第二部分480b於後側112之上。在一些實施例中，由上而視，第一部分480a具有圓形或正方形形狀，分別如第10A圖及第10C圖所示。此外，此圓形或正方形形狀可為不連續的圖形，分別如第10B圖及第10D圖所示。在其他實施例中，由上而視，第一部分480a具有連續或非連續的正多邊形形狀。在一些實施例中，從俯視方向來看，第二部分480b具有圓形或正方形形狀，分別如第11A圖及第11B圖所示。
實施例六：
在實施例六中，半導體裝置500(第9B圖)係藉由方法80(第8圖)，形成自不具有導體(例如：前側矽穿孔電極)於其中的基板。半導體裝置500包含與矽穿孔電極分離的環狀結構於基板之中，其中，此環狀結構與之後形成於其上之凸塊整合以形成一體，且不具有凸塊下金屬層於凸塊與基板之間。
請參照第8圖及第9A圖，方法80自方法30的步驟38(第3圖的標誌”B”)繼續進行至步驟82，其係形成凸塊580於第4C圖的半導體裝置中的基板210之後側212之上，且凸塊580插入孔洞250與溝渠252之中。如第9A圖所示，藉由前述之微影蝕刻製程，先形成光阻遮罩510。接著，藉由沉積或磊晶的方法，形成與內連線結構220電氣相連的凸 塊580於晶種層242之上。接著，可接著進行後續製程以形成迴焊錫球凸塊590於凸塊580之上，至此，半導體裝置500(第9B圖)已形成。值得注意的是，在形成凸塊580之前，可蝕刻掉一部分未被凸塊580所覆蓋的晶種層242，以避免相鄰矽穿孔電極的不同晶種層間形成電氣相連而造成短路的現象。或者，在形成凸塊580之後，可能蝕刻掉一部分未被凸塊580所覆蓋的晶種層242，以避免前述之短路現象。此外，凸塊580包含第一部分580a於溝渠252之中及第二部分580b於後側212之上。在一些實施例中，由上而視，第一部分580a具有圓形或正方形形狀，分別如第10A圖及第10C圖所示。此外，此圓形或正方形形狀可為不連續的圖形，分別如第10B圖及第10D圖所示。在其他實施例中，由上而視，第一部分580a具有連續或非連續的正多邊形形狀。在一些實施例中，由上而視，第二部分580b具有圓形或正方形形狀，分別如第11A圖及第11B圖所示。
值得注意的是，位於半導體裝置200、300、400、500之後側的第二材料層260和第一部分380a、480a、580a(或稱作環狀結構)能弱化前述位於矽穿孔電極(例如：第4D圖中的第一材料層240)與基板(例如：第4D圖中的基板210)間的熱應力。更詳細地說，溝渠(例如：第4C圖中的溝渠252)能釋放由矽穿孔電極與基板間大量熱膨脹係數差異所造成的拉伸應力。接著，再填入各態樣的材料於溝渠之中以形成環狀結構。
以上所討論的本揭露之各實施例具有現有半導體裝置與製程所沒有的優點，其優點總結如下。本揭露之半導體裝置係新穎的結構，其應用環狀結構於基板之中。此環狀結構位於基板的後側，且環繞矽穿孔電極，以降低矽穿孔電極與基板間或兩相鄰矽穿孔電極間的熱應力，此熱應力可能造成結構不穩定、效能低落或甚至使得矽穿孔電極剝離自基板。更詳細地說，在形成矽穿孔之後，未填入材料的環狀結構(即溝渠)能釋放熱應力(通常為拉伸應力)。或者，在填入材料於溝渠之中以形成環狀材料之後，鄰近基板後側(即相對於具有電路於其上的前側)的矽穿孔電極與基板間的介面將被往基板內部推進，使得矽穿孔電極與基板間的熱應力下降。此外，環狀結構可直接接觸或分離自矽穿孔電極；環狀結構的材料可為絕緣或導電材料；且環狀結構可與其他後側層(例如：凸塊下金屬層或凸塊)結合成一體或具有與其他後側層不同的材料。
上文概述若干實施例之特徵，使得熟習此項技術者可更好地理解本發明之態樣。熟習此項技術者應瞭解，可輕易使用本發明作為設計或修改其他製程及結構的基礎，以便實施本文所介紹之實施例的相同目的及/或實現相同優勢。熟習此項技術者亦應認識到，此類等效結構並未脫離本發明之精神及範疇，且可在不脫離本發明之精神及範疇的情況下產生本文的各種變化、替代及更改。
100‧‧‧半導體裝置
110‧‧‧基板
112‧‧‧後側
140‧‧‧導體
160‧‧‧材料層
162‧‧‧環狀結構
170‧‧‧凸塊下金屬層
180‧‧‧凸塊
190‧‧‧迴焊錫球凸塊

Claims (16)

  1. 一種半導體裝置，包含：一基板，包含一後側與一前側，且該前側具有一導體於其上；一孔洞，穿透該基板並暴露該導體；一溝渠，延伸自該後側至該基板之中並環繞該孔洞，其中，一第一材料層位於該孔洞之中並電性連接至該導體，一第二材料層位於該溝渠之中，且該第二材料層與該第一材料層之頂表面共平面；以及一凸塊下金屬層(UBM)，位於該第二材料層之上且直接接觸於該第二材料層，其中該UBM與該第二材料層係由不同材料製成。
  2. 如請求項1所述之半導體裝置，更包含一襯層位於該孔洞之側壁上。
  3. 如請求項2所述之半導體裝置，其中該第二材料層直接接觸一部分該襯層之側壁。
  4. 如請求項3所述之半導體裝置，其中該第二材料層包含氧化矽、氮化矽、氮氧化矽、銅、鎢或其組合。
  5. 如請求項1所述之半導體裝置，其中一部分該基板完全分離該溝渠與該孔洞。
  6. 如請求項5所述之半導體裝置，更包含一第二襯層於該溝渠之側壁之上。
  7. 如請求項1所述之半導體裝置，更包含一凸塊位於該基板之後側之上。
  8. 如請求項7所述之半導體裝置，其中該凸塊下金屬層(UBM)於該凸塊及該基板之該後側之間。
  9. 如請求項8所述之半導體裝置，其中該UBM之一底表面與該第一材料層及該第二材料層之頂表面係共平面。
  10. 如請求項1所述之半導體裝置，其中該第一材料層及該第二材料層包含一材料，其獨立選自一群組，包含：鈦、鋁、銅、鉻、銀、鎢、氧化矽及其組合。
  11. 如請求項1所述之半導體裝置，其中該導體係一結構，其選自一群組，包含：內連線結構、金屬層、閘極、前側矽穿孔電極及其組合。
  12. 如請求項7所述之半導體裝置，其中該溝渠及該凸塊由上而視具有一形狀，其獨立選自一群組，包含：圓形、正方形及多邊形。
  13. 一種製造半導體裝置之方法，包含：接收一基板，其包含一後側與一前側，且該前側具有一導體於其上；形成一孔洞於該基板之中，且該孔洞暴露該導體；形成一溝渠，其延伸自該後側至該基板之中且環繞該孔洞；形成一第一材料層於該孔洞之中；形成一第二材料層於該溝渠之中，其中該第二材料層與該第一材料層之頂表面共平面；以及形成一凸塊下金屬層(UBM)於該第二材料層之上且直接接觸於該第二材料層，其中該UBM與該第二材料層係由不同材料製成。
  14. 如請求項13所述之方法，更包含形成一凸塊於該基板之該後側之上。
  15. 如請求項14所述之方法，其中該凸塊下金屬層(UBM)形成於該凸塊與該基板之該後側之間。
  16. 如請求項13所述之方法，其中形成該溝渠係蝕刻一部分與該孔洞分離之基板。
TW105120948A 2016-04-11 2016-07-01 半導體裝置及其製造方法 TWI604590B (zh)

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