CN107293522B - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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CN107293522B
CN107293522B CN201610886753.6A CN201610886753A CN107293522B CN 107293522 B CN107293522 B CN 107293522B CN 201610886753 A CN201610886753 A CN 201610886753A CN 107293522 B CN107293522 B CN 107293522B
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substrate
material layer
semiconductor device
conductor
bump
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CN107293522A (zh
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林柏均
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Nanya Technology Corp
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Nanya Technology Corp
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Abstract

本发明公开了一种半导体装置及其制造方法，此半导体装置具有环绕硅穿孔电极的环状结构。其制造方法包含接收基板，此基板包含后侧与具有导体的前侧；形成孔洞在该基板中，此孔洞暴露导体；形成沟渠，从后侧延伸至基板中并环绕孔洞；形成第一材料层于孔洞中；以及形成第二材料层于沟渠中。填满第二材料层的沟渠将形成环状结构，而填满第一材料层的孔洞则形成硅穿孔电极。环状结构可降低或消除硅穿孔电极与基板或两相邻硅穿孔电极间的热应力，而达到避免发生裂痕或剥离的效果。

Description

半导体装置及其制造方法
技术领域
本发明涉及一种半导体装置及其制造方法，且特别涉及一种具有环绕硅穿孔电极的环状结构的半导体装置及其制造方法。
背景技术
随着半导体产业追求更高性能的需求增加，包装技术已从二维(2D)发展至三维(3D)的晶片封装，从而进一步提高集成电路装置中，电路的密度及性能。
在3D晶片封装中，两个晶片通过导电垫结合在一起，且随后形成的硅穿孔(TSV)电极能连结第一晶片和第二晶片上的导电垫。硅穿孔电极通常由铜或其它导电材料所形成，以提供导电垫间电气连结。然而，由于硅穿孔电极的铜或其它导电材料，与包围硅穿孔电极的基板的材料间，热膨胀系数差异甚大，故会产生热应力，进而导致结构不稳定或产生缺陷。因此，需要进一步改善，以解决上述的问题，并提高半导体装置的性能。
发明内容
根据本发明的一些实施例，提供一种半导体装置，其包含基板，此基板具有前侧与后侧，且后侧具有导体。此半导体装置还包含孔洞及沟渠于基板中，且孔洞穿透基板并暴露导体，而沟渠则从后侧延伸至基板内部，并环绕孔洞。此半导体装置还包含第一材料层于孔洞中，并与导体电性连接；以及第二材料层于沟渠中。
根据本发明的一些实施例，半导体装置还包含衬层于孔洞的侧壁上。
根据本发明的一些实施例，第二材料层与部分衬层的侧壁直接接触。
根据本发明的一些实施例，第二材料层包含氧化硅、氮化硅、氮氧化硅、铜、钨或其组合。
根据本发明的一些实施例，部分的基板完全分离沟渠与孔洞。
根据本发明的一些实施例，半导体装置还包含第二衬层于沟渠的侧壁上。
根据本发明的一些实施例，半导体装置还包含凸块于基板的后侧上。
根据本发明的一些实施例，凸块、第一材料层及第二材料层为互相直接接触，且由相同材料所组成。
根据本发明的一些实施例，半导体装置的凸块与基板后侧之间还包含凸块下金属层。
根据本发明的一些实施例，凸块下金属层的底表面与第一材料层和第二材料层的顶表面为共平面。
根据本发明的一些实施例，凸块及第二材料层由相同的材料所制成，以形成插入沟渠的整合凸块。
根据本发明的一些实施例，第一材料层及第二材料层的材料由一种材料所组成，其独立选自组合，该组合包含：钛、铝、铜、铬、银、钨、氧化硅及其组合。
根据本发明的一些实施例，导体为一种结构，选自组合，该组合包含：内连线结构、金属层、闸极电极、前侧硅穿孔电极及其组合。
根据本发明的一些实施例，沟渠与凸块由上而视具有一定形状，独立选自组合，该组合包含：圆形、正方形及正多边形。
根据本发明的一些实施例，提供一种半导体装置的制造方法。此方法包含：接收基板，此基板包含后侧与前侧，且前侧具有导体；形成孔洞于基板中，且暴露导体；形成沟渠，从后侧延伸至基板内部，并环绕通孔；形成第一材料层于孔洞中；以及形成第二材料层于沟渠中。
根据本发明的一些实施例，此方法还包含形成凸块于基板后侧上。
根据本发明的一些实施例，此方法还包含在基板后侧与凸块之间形成凸块下金属层。
根据本发明的一些实施例，形成凸块与形成第二材料层为同时进行，且凸块与第二材料层由相同的材料所制成。
根据本发明的一些实施例，形成第一材料层、形成第二材料层及形成凸块为同时进行，且第一材料层、第二材料层和凸块由相同的材料所制成。
根据本发明的一些实施例，形成沟渠为蚀刻部分与空洞分离的基板。
本发明提供的半导体装置及其制造方法制造的半导体环状结构，可降低或消除硅穿孔电极与基板或两相邻硅穿孔电极间的热应力，可达到避免发生裂痕或剥离的效果。
附图说明
在结合随附图阅读时，自以下详细描述将很好地理解本发明的技术方面。应注意，根据工业中的标准实务，附图中各特征并非按比例绘制。事实上，出于论述清晰的目的，可任意增加或减小图示特征的尺寸。
图1为绘示根据一些实施例，一种用于形成半导体装置的方法的示意流程图；
图2A至图2E为绘示根据一些实施例，一种半导体装置在工艺中各阶段的示意剖面图；
图3为绘示根据一些实施例，一种用于形成半导体装置的方法的示意流程图；
图4A至图4E为绘示根据一些实施例，一种半导体装置在工艺中各阶段的示意剖面图；
图5A为绘示根据一些实施例，一种用于形成半导体装置的方法的示意流程图；
图5B为绘示根据一些实施例，一种用于形成半导体装置的方法的示意流程图；
图6A至图6C为绘示根据一些实施例，一种半导体装置在工艺中各阶段的示意剖面图；
图7A至图7E为绘示根据一些实施例，一种半导体装置在工艺中各阶段的示意剖面图；
图8为绘示根据一些实施例，一种用于形成半导体装置的方法的示意流程图；
图9A至图9B为绘示根据一些实施例，一种半导体装置在工艺中各阶段的示意剖面图；
图10A至图11B为绘示根据一些实施例，一种半导体元件由上而视的示意形状。
具体实施方式
以下揭示内容提供许多不同实施例或实例，以便实施本发明的不同特征。下文描述组件及排列的特定实例以简化本发明。当然，此等实例仅为示例且并不意欲为限制性。举例而言，以下描述中在第二特征上方或第二特征上形成第一特征可包括以直接接触形成第一特征及第二特征的实施例，且亦可包括可在第一特征与第二特征之间形成额外特征以使得第一特征及第二特征可不处于直接接触的实施例。另外，本发明可在各实例中重复元件符号及/或字母。此重复是出于简明性及清晰的目的，且本身并不指示所论述的各实施例及/或配置之间的关系。
进一步地，为了便于描述，本文可使用空间相对性术语(诸如“之下”、“下方”、“下部”、“上方”、“上部”及类似者)来描述诸图中所图示一个元件或特征与另一元件(或多个元件)或特征(或多个特征)的关系。除了诸图所描绘的定向外，空间相对性术语意欲包含使用或操作中装置的不同定向。设备可经其它方式定向(旋转90度或处于其它定向)且因此可同样解读本文所使用的空间相对性描述词。
在半导体结构的工艺中，半导体结构的稳定运作是非常重要的。因此，应避免任何可能造成结构不稳定的因素。在半导体结构中，其中一个结构不稳定的现象可能发生在硅穿孔(through silicon via，TSV)电极与邻近的半导体基板之间。通常，硅穿孔电极与半导体基板间的巨大热膨胀系数不匹配可能造成硅穿孔电极的剥离，因而降低半导体装置的结构稳定性。
更详细地说，在传统的半导体装置中，铜或其它导电材料可能填充于硅穿孔中，以形成硅穿孔电极并提供电气连结与位于晶圆两侧上的导电元件(例如：电路、晶体管和内连线结构)。值得注意的是，铜或其它导电金属，具有远高于硅的热膨胀系数。举例来说，铜的热膨胀系数大约为16.5ppm/℃，而硅的热膨胀系数却只有2.6ppm/℃。在沉积铜之后或于后续的热处理(例如：无铅回流焊接工艺、测试或使用)中，如此大的热膨胀系数差异可能造成显著的热应力于硅与铜之间。此外，若相邻的硅穿孔电极更为接近，则此热应力可能更加严重。上述的热应力可能造成各种问题，例如：薄膜剥离、半导体基板的裂痕和半导体装置效能的下降。
为了解决由半导体基板(例如：硅基板)与硅穿孔电极(例如：铜硅穿孔电极)间的热应力所造成的半导体装置的结构不稳定，本发明提供一种降低半导体基板与硅穿孔电极间热应力的方法。在此方法中，环状结构置于半导体基板的后侧(back side)，并环绕硅穿孔电极。此处所称的“后侧”指的是位于具有电路于其上的前侧(front side)的另一侧。环状结构可直接接触硅穿孔电极或与其分离。此外，环状结构可包含绝缘材料或导电材料。另外，环状结构可与其它后侧层(例如：凸块下金属层或凸块)结合成一体或具有与后侧层不同的材料。此环状结构可降低或消除上述硅穿孔电极与半导体基板或两相邻硅穿孔电极间的热应力，以解决上述裂痕或剥离的问题。
在本发明中，六个半导体装置100、150、200、300、400、500及其制造方法10、30、50、60、80分别描述于六个实施例中。半导体装置100、150、200、300、400、500间的差异可能为下列因素之一或其组合：环状结构与硅穿孔电极间的关系(直接接触或分离)；填充于环状结构中的材料(导电材料或绝缘材料)；环状结构与其它后侧层的关系(结合或分开)。值得注意的是，本发明有关实施例的描述不可用于限制权利要求的精神与范围。
在实施例一和实施例二中，半导体装置100、150(图2D和图2E)系通过方法10，形成自具有已存在的导体(例如：前侧硅穿孔电极)于其中的基板(图2A)。半导体装置100、150包含与硅穿孔电极直接接触的环状结构于基板中。以下先介绍实施例一。
实施例一：
请参照图1及图2A，方法10起始于步骤12，其为接收基板。如图2A所示，基板110包含前侧114及后侧112，前侧114还包含晶体管130、浅沟槽隔离(STI)132、层间介电层(ILD)122及内连线结构120。此外，导体140置于基板110中，且与内连线结构120电气相连。
请再参照图2A，基板110可能包含主体硅基板(bulk silicon substrate)。或者，基板110可能包含基本半导体(例如：晶体结构的硅或锗)或化合物半导体，例如：锗化硅、碳化硅、砷化镓、磷化镓、磷化铟、砷化铟、锑化铟或其任意的组合。基板110亦可包含绝缘层覆硅(silicon-on-insulator，SOI)基板。一般来说，SOI基板包含一层具有半导体材料(例如：硅、锗、锗化硅、绝缘层覆锗化硅或其任意的组合)的层。
此外，晶体管130可能包含栅极电极、源极/漏极区域、浅掺杂漏极(LDD)区域、N井(N-well)、P井(P-well)或其组合。举例来说，N井可能包含N型掺杂质，例如：磷(P)、砷(As)、锑(Sb)、铋(Bi)、硒(Se)、碲(Te)及其任意的组合。而P井可能包含P型掺杂质，例如：硼(B)、二氟化硼(BF2)或其任意的组合。为了简洁的目的，本发明内容未绘示或进一步描述上述晶体管130中的各种结构。
此外，内连线结构120及导体140可为任何适合的半导体导电元件。举例来说，内连线结构120及导体140可能为但不局限于：内连线结构、多晶硅闸极、金属闸极、接点、前侧硅穿孔电极或其组合。在本实施例中，导体140为前侧硅穿孔电极，其于后述形成环状结构之前便已存在。内连线结构120及导体140的材料随着其用途而异。一般而言，内连线结构120及导体140的材料可各自含有一种材料选自一种组合，其包含但不局限于：银(Ag)、铜(Cu)、钨(W)、钛(Ti)、钽(Ta)、铝(Al)、镍(Ni)、钌(Ru)、钯(Pd)、铂(Pt)、锰(Mn)、氮化钨(WN)、氮化钛(TiN)、氮化钽(TaN)、氮化铝(AlN)、硅化钨(WSi)、氮化钼(MoN)、硅化镍(Ni2Si)、硅化钛(TiSi2)、铝化钛(TiAl)、砷(As)掺杂的多晶硅、氮化锆(ZrN)、TaC、TaCN、TaSiN、TiAlN及其任意的组合。
在一些实施例中，半导体装置100还包含晶种层142及衬层144。晶种层142位于导体140的上表面及侧壁上，而衬层144则于晶种层142的上表面及侧壁上。换言之，晶种层142及衬层144覆盖导体140。在一些实施例中，晶种层142包含铜或其它导电材料。在一些实施例中，衬层144可能包含任何适合的材料，例如但不局限于：四乙氧基硅烷(TEOS)、氮化硅、氮氧化硅、氧化硅及其组合。
请参照图1及图2B，方法10继续进行至步骤14，其是从后侧112削薄基板110以暴露衬层144。基板110的削薄工艺可为任何适合的工艺，例如：化学机械研磨(CMP)、蚀刻或其组合。
在暴露衬层144之后，方法10继续进行至步骤16，其是自基板110的后侧112形成沟渠152。沟渠152位于基板110中且环绕导体140。在一些实施例中，通过微影蚀刻工艺来形成具有孔洞(未标示)的光阻遮罩(未标示)。接着，通过蚀刻工艺(例如：湿蚀刻、干蚀刻或电浆蚀刻)以形成沟渠152。微影蚀刻工艺可能包含形成光阻层(未标示)于基板110的后侧112上、暴露光阻层以形成图案(未标示)、进行曝光后烘烤工艺及图案化光阻层以形成光阻遮罩。
如图2B所示，由俯视方向来看，沟渠152具有圆形形状(图10A)。沟渠152暴露衬层144的侧壁的上部。值得注意的是，沟渠152仅暴露衬层144的侧壁的上部，而非整个衬层144的侧壁。也就是说，沟渠152形成于基板110的紧邻于后侧112的上部，而非穿透基板110。在一些实施例中，沟渠152可能由多个分块所组成(如图10B所示)。在一些实施例中，由上而视，沟渠152可能具有连续正方形形状(如图10C所示)、不连续正方形形状(如图10D所示)或正多边形形状。在其它实施例中，沟渠152可能暴露浅沟槽隔离132。
请参照图1及图2C，方法10继续进行至步骤18，其为沉积材料层160于基板110的后侧112上，其中，部分的材料层160填入沟渠152中，以形成环状结构162。在一些实施例中，材料层160的材料是选自一种组合，其包含氧化硅、氮化硅、氮氧化硅及其组合。在一些实施例中，由另一种沉积工艺形成环状结构162，且其材料包含铜、钨、其它导电材料或其组合。
在形成环状结构162后，进行薄化工艺，例如：化学机械研磨、研磨或蚀刻，以自后侧112削薄基板110，以暴露导体140而保留环状结构162于基板110的后侧112。如图2C所示，沉积材料层160的方法可为任何适合的工艺，例如但不局限于：化学气相沉积(CVD)、物理气相沉积(PVD)、原子层沉积(ALD)、电浆化学气相沉积(PECVD)或其组合。值得注意的是，环状结构162是直接接触于衬层144的侧壁上部(即144a)。在一些实施例中，图2B所示的结构不包含衬层144，因此环状结构162是直接接触于晶种层142的侧壁上部。在另一些实施例中，图2B所示的结构不包含衬层144及晶种层142，因此环状结构162是直接接触于导体140的侧壁上部。因此，环状结构162能于热处理时，降低或消除前述的导体140与基板110间的热应力。从而解决结构不稳定的问题，例如：导体140的剥离及自邻近于后侧112的导体140与基板110界面所形成的裂痕。
请参照图1及图2D，方法10继续进行至步骤20，其是形成凸块下金属层(UBM)170及凸块180于基板110的后侧112上。其中，凸块下金属层170及凸块180与导体140电气相连。如图2D所示，凸块下金属层170系形成于基板110的后侧112上。其中，凸块下金属层170覆盖整个环状结构162及导体140。接着，形成凸块180于凸块下金属层170上。最后，形成回焊锡球凸块(reflowed solder bump)190于凸块180上。至此，具有环状结构162的半导体装置100便形成，而后续的工艺(例如：黏结晶圆)可继续进行。在一些实施例中，凸块下金属层170是溅镀或电镀至基板110的后侧112上。在一些实施例中，凸块下金属层170是由单层或多层所组成，其材料选自组合，其包含：铬、钛、铜、银及其组合。在一些实施例中，凸块180及回焊锡球凸块190可通过任何适合的工艺(例如：蒸镀、溅镀、电镀或印刷)形成于凸块下金属层170上。
实施例二：
不同于实施例一中的半导体装置100，可调整一些参数以符合设计需求，例如：环状结构162的形状、自衬层144的外侧壁至环状结构162的外侧壁的长度(L162)及自衬层144的外侧壁至凸块下金属层170的外侧壁的长度(L170)。举例来说，长度L170可能小于长度L162，使得凸块下金属层170覆盖部分或不覆盖环状结构162。在其它实施例中，在半导体装置150(图2E)中，从剖面方向来看，环状结构162具有弧形形状于其下部(即162a)。此外，半导体装置150的形成方法及元件的材料与前述的半导体装置100相同。值得注意的是，长度L170及长度L162之间的关系与环状结构162的形状不该局限于半导体装置100(图2D)及150(图2E)。
值得注意的是，半导体装置100、150中的环状结构162可降低或消除前述的位于导体(或硅穿孔电极)与基板110之间的热应力。更详细地说，导体140与基板110的后侧112的介面将会被推向基板110的内部，而此处的热应力小于接近后侧112的热应力。或者，环状结构162的沟渠152能消除导体140与基板110间的热应力以降低上述热应力的程度。在一些实施例中，上述环状结构162的形成(即步骤18)是进行于较低的温度，例如：300℃、200℃、100℃或室温，如此一来，沟渠152及后续形成的环状结构162能降低或消除原先于降温过程中，产生于导体140与基板110之间的热应力，而不再次产生热应力。因此，导体140与基板110间的热应力能被降低或消除。
在实施例三中，半导体装置200(图4E)是通过方法30(图3)，形成自不具有导体(例如：前侧硅穿孔电极)于其中的基板(图4A)。半导体装置200包含与硅穿孔电极分离的环状结构于基板中，其中，此环状结构包含导电材料或绝缘材料。
实施例三：
请参照图3及图4A，方法30起始自步骤32，其为接收基板210。如图4A所示，基板210包含前侧214及后侧212。其中，此前侧214还包含晶体管230、浅沟槽隔离(STI)232、层间介电层(ILD)222、内连线结构220。不同于基板110(图2A)，基板210不具有与内连线结构220电气相连的导体于其中。也就是说，基板210不包含前侧硅穿孔电极于其中。由于有关于基板210的结构或元件与前述的有关于基板110的结构与元件(图2A)相似，为了简洁的目的而不在此重复叙述。
请参照图3及图4B，方法30继续进行至步骤34，其是自后侧212形成孔洞250于基板210中。其中，此孔洞250穿透基板210并暴露内连线结构220。接着进行步骤36，其是自后侧212形成沟渠252。其中，此沟渠252位于基板210中，并环绕孔洞250。在本实施例中，步骤34及步骤36是同步进行，通过微影蚀刻工艺与蚀刻工艺，同时形成孔洞250及沟渠252。微影蚀刻工艺及蚀刻工艺类似于前述的形成沟渠152(图2B)的工艺，故不在此赘述。
请参照图3及图4C，方法30继续进行至步骤38，其是形成衬层244及晶种层242于基板210的后侧212及孔洞250和沟渠252的侧壁上。如图4C所示，衬层244及晶种层242可通过任何适合的工艺(例如：CVD、PVD、PECVD、溅镀及其组合)，沉积于后侧212、孔洞250和沟渠252的下表面及侧壁上。值得注意的是，晶种层242是用于改善衬层244与随后形成的第一导电层之间的附着结合度。衬层244及晶种层242的材料类似于前述的衬层144及晶种层142(图2A)，故不在此赘述。此外，一部分的孔洞250的底部未被衬层244及晶种层242覆盖，使得后续填入孔洞250的第一导电层与内连线结构220形成电气连接。
请参照图3及图4D，方法30继续进行至步骤40，其是形成第一材料层240于孔洞250中。接着，进行步骤42以形成第二材料层260于沟渠252中。在本实施例中，第一材料层240及第二材料层260是依次形成并由不同的材料所形成，其材料可选自组合，其包含：钛、铝、铜、铬、银、钨、氧化硅及其组合。在本实施例中，第一材料层240是由导电材料所制成，以形成硅穿孔电极。第一材料层240及第二材料层260可通过沉积(例如：CVD、PVD、PECVD或溅镀)或磊晶的方式形成。在一些实施例中，第一材料层240及第二材料层260是同时形成并由相同的材料所形成。在一些实施例中，由上而视，第二材料层260具有圆形或正方形形状，分别如图10A及图10C所示。此外，此圆形或正方形形状可为不连续的图形，分别如图10B及图10D所示。在其它实施例中，由上而视，第二材料层260具有连续或不连续的正多边形形状。
请参照图3及图4E，方法30继续进行至步骤44，其是形成凸块下金属层(UBM)270及凸块280于基板210的后侧212上。如图4E所示，凸块下金属层270是形成于基板210的后侧212上，凸块280是形成于凸块下金属层270上，且回焊锡球凸块290是形成于凸块280上。凸块下金属层270、凸块280及回焊锡球凸块290的材料及形成方式类似于凸块下金属层170、凸块180及回焊锡球凸块190(图2D)。值得注意的是，在形成凸块280之前，可能先蚀刻掉一部分未被凸块280所覆盖的凸块下金属层270和/或晶种层242，以避免相邻硅穿孔电极的不同凸块下金属层间形成电气相连而造成短路的现象。或者，在形成凸块下金属层270及凸块280后，可能蚀刻掉一部分未被凸块280所覆盖的晶种层242和/或凸块下金属层270，以避免前述的短路情形。在本实施例中，自第一材料层240侧壁上的衬层244的外侧壁至第二材料层260的外侧壁的长度(L260)与自第一材料层240侧壁上的衬层244的外侧壁至凸块下金属层270的外侧壁的长度(L270)相同。在其它实施例中，距离L260可能大于或小于距离L270。至此，半导体装置200已完成。在一些实施例中，由上而视，凸块下金属层270具有圆形或正方形形状，分别如图11A及图11B所示。
在实施例四和实施例五中，半导体装置300、400(图6C和图7E)是分别通过方法50(图5A)、60(图5B)，形成自不具有或具有导体(例如：前侧硅穿孔电极)于其中的基板。半导体装置300、400包含与硅穿孔电极分离的环状结构于基板中，其中，此环状结构与之后形成于其上的凸块整合成一体，并具有凸块下金属层于凸块与基板之间。以下将先介绍实施例四。
实施例四：
请参照图5A及图6A，方法50自方法30的步骤38(标志为“B”)继续进行至步骤52，其是形成第一材料层340于图4C的半导体装置里的孔洞250中。如图6A所示，在形成第一材料层340于孔洞250之前，通过的前述的微影蚀刻工艺，先形成光阻遮罩310于基板210的后侧212之上。光阻遮罩310覆盖沟渠252且未填入孔洞250中，因而使得后续的工艺(例如：沉积或磊晶)能只形成与内连线结构220电气相连的第一材料层340于孔洞250中。在形成第一材料层340之后，移除光阻遮罩310以暴露沟渠252。
请参照图5A及图6B，方法50继续进行至步骤54，其是沉积凸块下金属层(UBM)370于基板210的后侧212上。其中，凸块下金属层370也覆盖沟渠252的侧壁。
请参照图5A及图6C，方法50继续进行至步骤56，其是形成凸块380于凸块下金属层370上。其中，凸块380插入沟渠252，因此，环状结构(即填入一部分的凸块380的沟渠252)与凸块(即凸块380)整合成一体。接着，进行后续的工艺以形成回焊锡球凸块390于凸块380上，至此，半导体装置300已形成。值得注意的是，在形成凸块380之前，可蚀刻掉一部分未被凸块380覆盖的凸块下金属层370和/或晶种层242，以避免相邻硅穿孔电极的不同凸块下金属层间形成电气相连而造成短路的现象。或者，在形成凸块下金属层370及凸块380之后，可能蚀刻掉一部分未被凸块380所覆盖的晶种层242和凸块下金属层370，以避免的前述的短路现象。此外，凸块380包含第一部分380a于沟渠252中及第二部分380b于后侧212上。在一些实施例中，由上而视，第一部分380a具有圆形或正方形形状，分别如图10A及图10C所示。此外，此圆形或正方形形状可为不连续的图形，分别如图10B及图10D所示。在其它实施例中，由上而视，第一部分380a具有连续或非连续的正多边形形状。在一些实施例中，由上而视，第二部分380b具有圆形或正方形形状，分别如图11A及图11B所示。
实施例五：
另一方面，在实施例五中，半导体装置400大致上具有与实施例四中的半导体装置300相同的结构。半导体装置400是通过方法60(图5B)，形成自一具有导体(例如：前侧硅穿孔电极)于其中的基板。
请参照图5B及图7A，方法60自方法10的步骤14(标志为“A”)继续进行至步骤62，其是沉积氧化物层460于基板110的后侧112上，并进行薄化制成，以暴露导体140。在本实施例中，先形成氧化物层460于后侧112上，且覆盖着衬层144。接着，进行薄化工艺以去除一部分的氧化物层460、一部分的衬层144及一部分的晶种层142，已暴露导体140。在其它实施例中，先进行薄化工艺以去除一部分的衬层144及一部分的晶种层142，以暴露导体140。接着，再沉积氧化物层460于后侧112上，且覆盖着导体140。然后，再次进行薄化工艺以暴露导体140。上述的薄化工艺可能为化学机械研磨、蚀刻或其组合。
请参照图5B及图7B，方法60继续进行至步骤64，其是形成环绕导体140的沟渠452于基板110中。如图7B所示，光阻遮罩410是形成于后侧112上并覆盖氧化物层460及导体140。其中，光阻遮罩410具有开孔(未标示)于沟渠452的正上方。光阻遮罩410可通过的前述的微影蚀刻工艺的方式来形成。接着，进行蚀刻工艺(例如：湿蚀刻、干蚀刻、电浆蚀刻及其组合)以去除一部分的氧化物层460及基板110，进而形成沟渠452。
请参照图5B及图7C，方法60继续进行至步骤66，其是形成第二氧化物层462于沟渠452的侧壁上。如图7C所示，第二氧化物层462与氧化物层460直接接触，以形成连续的氧化物层，进而提供基板110保护作用。在本实施例中，第二氧化物层462是由与氧化物层460相同的材料所形成，因此，氧化物层460及第二氧化物层462形成一整合层。在其它实施例中，第二氧化物层462可能包含双层结构，其具有与的前述的晶种层142及衬层144(第2A图)相似的材料。
请参照图5B及图7D，方法60继续进行至步骤68，其是沉积凸块下金属层(UBM)470于基板110的后侧112上。其中凸块下金属层470也覆盖第二氧化物层462的侧壁。
请参照图5B及图7E，方法60继续进行至步骤70，其是形成凸块480于凸块下金属层470上。其中，凸块480插入沟渠452，因此，环状结构(即填入一部分的凸块480的沟渠452)与凸块(即凸块480)整合成一体。接着，进行后续的工艺以形成回焊锡球凸块490于凸块480上，至此，半导体装置400已形成。值得注意的是，在形成凸块480之前，可蚀刻掉一部分未被凸块480所覆盖的凸块下金属层470，以避免相邻硅穿孔电极的不同凸块下金属层间形成电气相连而造成短路的现象。或者，在形成凸块480之后，可能蚀刻掉一部分未被凸块480所覆盖的凸块下金属层470，以避免的前述的短路现象。此外，凸块480包含第一部分480a于沟渠452中及第二部分480b于后侧112上。在一些实施例中，由上而视，第一部分480a具有圆形或正方形形状，分别如第10A图及第10C图所示。此外，此圆形或正方形形状可为不连续的图形，分别如第10B图及第10D图所示。在其它实施例中，由上而视，第一部分480a具有连续或非连续的正多边形形状。在一些实施例中，从俯视方向来看，第二部分480b具有圆形或正方形形状，分别如第11A图及第11B图所示。
实施例六：
在实施例六中，半导体装置500(图9B)是通过方法80(图8)，形成自不具有导体(例如：前侧硅穿孔电极)于其中的基板。半导体装置500包含与硅穿孔电极分离的环状结构于基板中，其中，此环状结构与之后形成于其上的凸块整合以形成一体，且不具有凸块下金属层于凸块与基板之间。
请参照图8及图9A，方法80自方法30的步骤38(图3的标志“B”)继续进行至步骤82，其是形成凸块580于图4C的半导体装置中的基板210的后侧212上，且凸块580插入孔洞250与沟渠252的中。如图9A所示，通过的前述的微影蚀刻工艺，先形成光阻遮罩510。接着，通过沉积或磊晶的方法，形成与内连线结构220电气相连的凸块580于晶种层242上。接着，可接着进行后续工艺以形成回焊锡球凸块590于凸块580上，至此，半导体装置500(图9B)已形成。值得注意的是，在形成凸块580之前，可蚀刻掉一部分未被凸块580所覆盖的晶种层242，以避免相邻硅穿孔电极的不同晶种层间形成电气相连而造成短路的现象。或者，在形成凸块580的后，可能蚀刻掉一部分未被凸块580所覆盖的晶种层242，以避免的前述的短路现象。此外，凸块580包含第一部分580a于沟渠252中及第二部分580b于后侧212上。在一些实施例中，由上而视，第一部分580a具有圆形或正方形形状，分别如图10A及图10C所示。此外，此圆形或正方形形状可为不连续的图形，分别如图10B及图10D所示。在其它实施例中，由上而视，第一部分580a具有连续或非连续的正多边形形状。在一些实施例中，由上而视，第二部分580b具有圆形或正方形形状，分别如图11A及图11B所示。
值得注意的是，位于半导体装置200、300、400、500的后侧的第二材料层260和第一部分380a、480a、580a(或称作环状结构)能弱化前述位于硅穿孔电极(例如：图4D中的第一材料层240)与基板(例如：图4D中的基板210)间的热应力。更详细地说，沟渠(例如：图4C中的沟渠252)能释放由硅穿孔电极与基板间大量热膨胀是数差异所造成的拉伸应力。接着，再填入各态样的材料于沟渠的中以形成环状结构。
以上所讨论的本发明的各实施例具有现有半导体装置与工艺所没有的优点，其优点总结如下。本发明的半导体装置是新颖的结构，其应用环状结构于基板中。此环状结构位于基板的后侧，且环绕硅穿孔电极，以降低硅穿孔电极与基板间或两相邻硅穿孔电极间的热应力，此热应力可能造成结构不稳定、效能低落或甚至使得硅穿孔电极剥离自基板。更详细地说，在形成硅穿孔之后，未填入材料的环状结构(即沟渠)能释放热应力(通常为拉伸应力)。或者，在填入材料于沟渠中以形成环状材料之后，邻近基板后侧(即相对于具有电路于其上的前侧)的硅穿孔电极与基板间的介面将被往基板内部推进，使得硅穿孔电极与基板间的热应力下降。此外，环状结构可直接接触或分离自硅穿孔电极；环状结构的材料可为绝缘或导电材料；且环状结构可与其它后侧层(例如：凸块下金属层或凸块)结合成一体或具有与其它后侧层不同的材料。
上文概述若干实施例的特征，使得本发明所属领域中的普通技术人员可更好地理解的本发明的技术精神与范畴。本发明所属领域中的普通技术人员应了解，可轻易使用本发明作为设计或修改其它工艺及结构的基础，以便实施本文所介绍的实施例的相同目的及/或实现相同优势。本发明所属领域中的普通技术人员亦应认识到，此类等效结构并未脱离的本发明的精神及范畴，且可在不脱离的本发明的精神及范畴的情况下产生本文的各种变化、替代及更改，因此本发明的保护范围当视权利要求所界定者为准。

Claims (13)

1.一种半导体装置，其特征在于，包含：
基板，包含后侧与前侧，且所述前侧具有导体；
孔洞，穿透所述基板并暴露所述导体；
沟渠，从所述后侧延伸至所述基板中，并环绕所述孔洞，其中，第一材料层位于所述孔洞中并电性连接至所述导体，第二材料层位于所述沟渠中并覆盖所述基板的所述后侧，且所述第二材料层与所述第一材料层的顶表面为共平面；以及
凸块下金属层，位于所述第二材料层上，电性连接至所述第一材料层及所述基板前侧的所述导体，且直接接触所述第一材料层及所述第二材料层，其中，所述凸块下金属层与所述第二材料层由不同材料所制成。
2.如权利要求1所述的半导体装置，其特征在于，所述半导体装置还包含衬层位于所述孔洞的侧壁上。
3.如权利要求2所述的半导体装置，其特征在于，所述第二材料层直接接触部分所述衬层的侧壁。
4.如权利要求3所述的半导体装置，其特征在于，所述第二材料层包含氧化硅、氮化硅、氮氧化硅、铜、钨或其组合。
5.如权利要求1所述的半导体装置，其特征在于，所述半导体装置还包含凸块，所述凸块位于所述基板的后侧上。
6.如权利要求5所述的半导体装置，其特征在于，所述凸块下金属层位于所述凸块及所述基板的所述后侧之间。
7.如权利要求6所述的半导体装置，其特征在于，所述凸块下金属层的底表面与所述第一材料层及所述第二材料层的顶表面为共平面。
8.如权利要求1所述的半导体装置，其特征在于，所述第一材料层及所述第二材料层包含一种材料，其独立选自群组，所述群组包含：钛、铝、铜、铬、银、钨及其组合。
9.如权利要求1所述的半导体装置，其特征在于，所述导体为一种结构，其选自群组，所述群组包含：内连线结构、金属层、闸极、前侧硅穿孔电极及其组合。
10.如权利要求5所述的半导体装置，其特征在于，所述沟渠及所述凸块由上而视具有一定形状，其独立选自群组，所述群组包含：圆形、正方形及多边形。
11.一种半导体装置的制造方法，其特征在于，包含：
接收基板，所述基板包含后侧、前侧及导体，其中，所述前侧具有内连线结构，所述导体位于所述基板中，且电性连接至所述内连线结构；
形成沟渠，从所述后侧延伸至所述基板中，且环绕所述导体；
形成材料层于所述沟渠中并覆盖所述基板的所述后侧，其中，所述材料层与所述导体的顶表面为共平面；以及
形成凸块下金属层于所述材料层上，电性连接至所述导体及所述基板前侧的所述内连线结构，且所述凸块下金属层直接接触所述导体及所述材料层，其中，所述凸块下金属层与所述材料层由不同材料所制成。
12.如权利要求11所述的半导体装置的制造方法，其特征在于，所述的半导体装置的制造方法还包含形成凸块于所述基板的所述后侧上。
13.如权利要求12所述的半导体装置的制造方法，其特征在于，所述凸块下金属层形成在所述凸块与所述基板的所述后侧之间。
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