CN102130041A - 半导体装置及其半导体工艺 - Google Patents
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Abstract
本发明关于一种半导体装置及其半导体工艺。本发明的半导体装置包括一半导体基板、至少一导电孔及至少一绝缘环。该半导体基板具有一第一表面。该导电孔位于该半导体基板内。每一导电孔具有一导体及一绝缘墙位于该导体的外围,且该导电孔显露于该半导体基板的第一表面。该绝缘环位于该导电孔的外围,且该绝缘环的深度小于该绝缘墙的深度。因为该绝缘环位于该导电孔的外围,该绝缘环能保护该导电孔的末端,使其不受到损伤。此外,该绝缘环及该导电孔的尺寸大于已知导电孔的尺寸,本发明的半导体装置能利用表面处理层、重布层或球下金属层轻易连接其它半导体装置。
Description
技术领域
本发明关于一种半导体装置及其半导体工艺。
背景技术
图1显示已知硅芯片的剖面示意图。该已知硅芯片30具有一硅基材31、至少一电子装置32、至少一穿导孔33、一保护层34及一重布层35。该硅基材31具有一第一表面311、一第二表面312及至少一穿孔313。该电子装置32位于该硅基材31内,且显露于该硅基材31的第二表面312。该穿导孔33贯穿该硅基材31。该穿导孔33包括一阻隔层333及一导体334。该阻隔层333位于该穿孔313的侧壁上,且该导体334位于该阻隔层333内。该穿导孔33具有一第一端331及一第二端332。该第一端331显露于该硅基材31的第一表面311,且该第二端332连接该电子装置32。该保护层34位于该硅基材31的第一表面311上,且该保护层34具有一表面341及至少一开口342。该开口342显露该穿导孔33的第一端331。该重布层35位于该表面341及该保护层34的开口342上,该重布层35具有至少一电性连接区域351,且该电性连接区域351连接该穿导孔33的第一端331。
该已知硅芯片30具有下列缺点。该保护层34的开口342的直径必须小于该硅基材31的穿孔313的直径,否则该重布层35的电性连接区域351会直接接触该硅基材31,而导致短路。然而,一般而言,该保护层34经由一曝光显影工艺图案化,且该工艺具有低分辨率,所以无法制造准确且细致的图案。因此,该保护层34的开口342的直径很可能会大于该硅基材31的穿孔313的直径,使该重布层35的电性连接区域351会直接接触该硅基材31,而导致短路。另一方面,如果该保护层34经由一高分辨率工艺图案化,则需要更多的后续工艺,使工艺变得复杂且昂贵。
图2显示已知半导体组件的剖面示意图。该已知半导体组件41包括一底材418、一保护层414、至少一电子装置415、至少一穿导孔结构416及一重布层417。该底材418具有一第一表面411、一第二表面412及至少一凹槽413。该凹槽413开口于该第一表面411。该保护层414位于该第一表面411上。
该电子装置415位于该底材418内,且显露于该底材418的第二表面412。该穿导孔结构416位于该凹槽413内且凸出于该第一表面411。该重布层417位于该保护层414上,且电性连接至该穿导孔结构416。
图3显示具有已知半导体组件的已知封装结构的剖面示意图。该封装结构40包括一基板44、一半导体组件41、一芯片43及一保护材料45。该芯片43位于该半导体组件41上,且经由这些凸块42电性连接至该重布层417。该保护材料45位于该基板44上,且覆盖该半导体组件41及该芯片43。
该已知封装结构40具有下列缺点。该保护层414为必要的;否则,这些凸块42可能电性连接该半导体组件41,而导致短路。
因此,有必要提供一种半导体装置及其半导体工艺,以解决上述问题。
发明内容
本发明提供一种半导体工艺,包括下列步骤:(a)提供一半导体装置,其具有一半导体基板及至少一导电孔,其中该半导体基板具有一第一表面,该导电孔位于该半导体基板内,该导电孔包括一导体及一绝缘墙位于该导体的外围,且该导电孔显露于该半导体基板的第一表面;(b)于该半导体基板的第一表面,形成一孔洞于该导电孔的外围,其中该孔洞并未贯穿该半导体基板;及(c)形成一绝缘环于该导电孔的外围,其中将一绝缘材料填入该孔洞,该绝缘环的深度小于该绝缘墙的深度。
本发明更提供一种半导体装置,包括一半导体基板、至少一导电孔及至少一绝缘环。该半导体基板具有一第一表面。该导电孔位于该半导体基板内。每一导电孔具有一导体及一绝缘墙位于该导体的外围,且该导电孔显露于该半导体基板的第一表面。该绝缘环位于该导电孔的外围,且该绝缘环的深度小于该绝缘墙的深度。
因为该绝缘环位于该导电孔的外围,该绝缘环能保护该导电孔的末端,使其不受到损伤。此外,该绝缘环及该导电孔的尺寸大于已知导电孔的尺寸,本发明的半导体装置能利用表面处理层、重布层或球下金属层轻易连接其它半导体装置。
附图说明
图1显示已知硅芯片的剖面示意图;
图2显示已知半导体组件的剖面示意图;
图3显示具有已知半导体组件的已知封装结构的剖面示意图;
图4至12显示本发明半导体装置的半导体工艺的第一实施例的示意图;
图13显示本发明半导体装置的第二实施例的局部放大示意图;
图14显示本发明半导体装置的第三实施例的局部放大示意图;及
图15至22显示本发明半导体封装结构的半导体工艺的第三实施例的示意图。
具体实施方式
图4至12显示本发明半导体装置的半导体工艺的第一实施例的示意图。参考图4,显示一半导体装置50及一第一载体11。该半导体装置50包括一半导体基板10及至少一导电孔52。该半导体基板10具有一上表面101、一第二表面102、一主动层103及数个导电组件105。在本实施例中,该半导体基板10为一晶圆。该主动层103位于该第二表面102,且这些导电组件105相邻于该主动层103。该导电孔52位于该半导体基板10内。
该导电孔52具有一导体521及一绝缘墙522位于该导体521的外围。该导电孔52更包括一第一端525及一第二端526。该第二端526连接至该主动层103,且该导电孔52并未贯穿该半导体基板10;亦即,该导电孔52的第一端525并未显露于该半导体基板10的上表面101。在本实施例中,该导电孔52的导体521由铜制成。
参考图5,该半导体基板10的第二表面102经由一第一黏着层12设置于该第一载体11上。如图6所示,经由研磨该上表面101移除部分该半导体基板10,以形成一第一表面104,且该导电孔52显露于该第一表面104。较佳地,该导电孔52的第一端525显露于该半导体基板10的第一表面104,参考图7,显示该半导体装置50的局部放大示意图。
参考图8及9,显示形成一孔洞于该导电孔的外围的局部放大示意图。该孔洞53(如图9所示)形成于该半导体基板10的第一表面104且位于该导电孔52的外围。该孔洞53(如图9所示)并未贯穿该半导体基板10。
在本实施例中,经由下列步骤形成该孔洞53。形成一光阻层61(如图8所示)于该半导体基板10的第一表面104。形成一第一开口611于该光阻层61内,该第一开口611的位置对应该孔洞53及该导电孔52。该第一开口611的截面积大于该导电孔52的截面积。接着,根据该第一开口611蚀刻部分该半导体基板10的第一表面104以形成该孔洞53。移除该光阻层61。
参考图10及11,显示形成一绝缘环621于该导电孔的外围的局部放大示意图。将一绝缘材料62填入该孔洞53形成该绝缘环621。该绝缘环621位于该导电孔52的外围,且该绝缘环621的深度小于该绝缘墙的522深度。
在本实施例中,经由下列步骤形成该绝缘环621。形成该绝缘材料62于该半导体基板10的第一表面104及该孔洞53内。接着,移除部分该绝缘材料62以显露该导电孔52及该绝缘环621。经由研磨或化学机械研磨(Chemical Mechanical Polishing,CMP)移除部分该绝缘材料62。
图12显示该半导体装置50的局部放大俯视图。参考图11及12,在本实施例中,该半导体装置50包括一半导体基板10、至少一导电孔52及至少一绝缘环621。该半导体基板10具有一第一表面104。该导电孔52位于该半导体基板10内。每一导电孔52具有一导体521及一绝缘墙522位于该导体521的外围,且该导电孔52显露于该半导体基板10的第一表面104。该绝缘环621位于该导电孔52的外围,且该绝缘环621的深度小于该绝缘墙522的深度。该导体521形成一圆形,该绝缘墙522形成一环状,且该绝缘环621形成一环状。
该半导体基板10更包括至少一孔洞53位于该导电孔52的外围,该孔洞53并未贯穿该半导体基板10,且一绝缘材料填入该孔洞53以形成该绝缘环621。
参考图13,显示本发明具有该绝缘环的半导体装置的第二实施例的局部放大示意图。本发明半导体装置70的半导体工艺的第二实施例可参照上述图4至11的本发明半导体装置50的半导体工艺的第一实施例。在图11的半导体工艺之后,形成一保护层71于该半导体基板10的第一表面104。该保护层71具有一第二开口711以显露该导电孔52及部分该绝缘环621。接着,形成一重布层(Redistribution Layer,RDL)72于该导电孔52、该第二开口内711的部分该绝缘环621及部分该保护层71上。接着,形成一球下金属层(Under Ball Metal,UBM)73于该重布层72上。
利用该重布层72及该球下金属层73,该半导体装置70的电性接触位置能弹性调整,以连接其它半导体装置。此外,因为该绝缘环621位于该导电孔52的外围,该重布层72的尺寸可大于该导电孔52的尺寸。本发明的半导体工艺的第二实施例易于实施,且当该导电孔52很小时,能确保该重布层72及该导电孔52间的电性连接。
此外,因为该绝缘环621位于该导电孔52的外围,该保护层71的第二开口711的直径可大于该导电孔52的直径,且该重布层72不会接触该半导体基板10。因此,一般而言,该保护层71能经由一曝光显影工艺及一低分辨率工艺图案化,而不需准确且细致的图案,因此本发明的工艺较为简化且节省成本。
参考图14,显示本发明具有该绝缘环的半导体装置的第三实施例的局部放大示意图。部分该导电孔52及该绝缘环621凸出于该第一表面104。
第三实施例的半导体装置80更包括一表面处理层81位于该导电孔52的第一端525上。该表面处理层81可用以连接其它半导体装置(图中未示),例如,其它半导体装置的焊垫。因为该绝缘环621位于该导电孔52的外围,该表面处理层81的尺寸可大于该导电孔52,且如图4所示的该保护层414可被省略。此外,利用该表面处理层81,第三实施例的半导体装置80可轻易连接其它半导体装置(图中未示)。
在本实施例中,部分该导电孔52及该绝缘环621凸出于该第一表面104。因为该绝缘环621位于该导电孔52的外围,该绝缘环621能保护该导电孔52的末端525,使其不受到损伤。此外,该绝缘环621的尺寸加上该导电孔52的尺寸大于已知导电孔的尺寸,该半导体装置50可轻易连接至其它半导体装置(图中未示),例如,其它半导体装置的焊垫。
在其它实施例中,该绝缘环621的厚度不大于10μm,该绝缘环621的外径不大于50μm,且该绝缘环的深度不大于30μm。
参考图15,显示本发明具有该绝缘环的半导体装置的第三实施例的示意图。该半导体装置80包括该半导体基板10、至少一导电孔52、该绝缘环621及该表面处理层81。该半导体基板10具有该第一表面104、该第二表面102、该主动层103及这些导电组件105。
参考图16,切割该半导体装置80且移除该第一载体11,以形成数个半导体单元15。参考图17,该半导体单元15设置于一胶带16上。
参考图18,显示一第二载体17及一下基板18。该下基板18经由一第二黏着层19附着于该第二载体17。参考图19,该半导体单元15接合至该下基板18。形成一底胶201于该半导体单元15及该下基板18之间,以保护这些导电组件105。
参考图20,形成一非导电性高分子层202于该第一表面104上,且一半导体组件21堆栈于该半导体单元15上。在本实施例中,该非导电性高分子层202为一环氧树脂(Epoxy)材料。同时,该表面处理层81接触该半导体组件21的一导电凸块211。
参考图21,形成一封胶材料22以覆盖该下基板18、该半导体单元15及该半导体组件21。参考图22,移除该第二载体17及该第二黏着层19,且形成数个焊球23于该下基板18的下表面,以形成一半导体封装结构20。
因为该绝缘环621位于该导电孔52的外围,该表面处理层81的尺寸可大于该导电孔52。此外,利用该表面处理层81及该导电凸块211,该半导体单元15可轻易连接该半导体组件21。
惟上述实施例仅为说明本发明的原理及其功效,而非限制本发明。因此,习于此技术的人士对上述实施例进行修改及变化仍不脱本发明的精神。本发明的权利范围应如权利要求书所列。
Claims (15)
1.一种半导体工艺,其包含:
(a)提供一半导体装置,其具有一半导体基板及至少一导电孔,其中该半导体基板具有一第一表面,该导电孔位于该半导体基板内,该导电孔包括一导体及一绝缘墙位于该导体的外围,且该导电孔显露于该半导体基板的第一表面;
(b)于该半导体基板的第一表面,形成一孔洞于该导电孔的外围,其中该孔洞并未贯穿该半导体基板;及
(c)形成一绝缘环于该导电孔的外围,其中将一绝缘材料填入该孔洞,该绝缘环的深度小于该绝缘墙的深度。
2.如权利要求1的半导体工艺,其中该步骤(b)包括:
(b1)形成一光阻层于该半导体基板的第一表面;
(b2)形成一第一开口于该光阻层内,该第一开口的位置对应该孔洞及该导电孔,其中该第一开口的截面积大于该导电孔的截面积;
(b3)根据该第一开口蚀刻部分该半导体基板的第一表面以形成该孔洞;及
(b4)移除该光阻层。
3.如权利要求1的半导体工艺,其中该步骤(c)包括:
(c1)形成该绝缘材料于该半导体基板的第一表面及该孔洞内;及
(c2)移除部分该绝缘材料以显露该导电孔及该绝缘环。
4.如权利要求3的半导体工艺,其中经由研磨或化学机械研磨移除部分该绝缘材料。
5.如权利要求1的半导体工艺,更包括:
(d)形成一保护层于该半导体基板的第一表面,该保护层具有一第二开口以显露该导电孔及部分该绝缘环;
(e)形成一重布层于该导电孔、该第二开口内的部分该绝缘环及部分该保护层上;及
(f)形成一球下金属层于该重布层上。
6.如权利要求1的半导体工艺,在步骤(c)之后更包括一移除部分该半导体基板的第一表面的步骤,使部分该导电孔及该绝缘环凸出于该第一表面。
7.如权利要求1的半导体工艺,在步骤(c)之后更包括一形成一表面处理层于该导电孔上的步骤。
8.一种半导体装置,包括:
一半导体基板,具有一第一表面;
至少一导电孔,位于该半导体基板内,每一导电孔具有一导体及一绝缘墙位于该导体的外围,且该导电孔显露于该半导体基板的第一表面;及
至少一绝缘环,位于该导电孔的外围,该绝缘环的深度小于该绝缘墙的深度。
9.如权利要求8的半导体装置,其中该半导体基板更包括至少一孔洞位于该导电孔的外围,该孔洞并未贯穿该半导体基板,且一绝缘材料填入该孔洞以形成该绝缘环。
10.如权利要求8的半导体装置,更包括:
一保护层,位于该半导体基板的第一表面,该保护层具有一第二开口以显露该导电孔及部分该绝缘环;
一重布层,位于该导电孔、该第二开口内的部分该绝缘环及部分该保护层上;及
一球下金属层,位于该重布层上。
11.如权利要求8的半导体装置,其中部分该导电孔及该绝缘环凸出于该第一表面。
12.如权利要求8的半导体装置,其中该绝缘环的厚度不大于10μm。
13.如权利要求8的半导体装置,其中该绝缘环的外径不大于50μm。
14.如权利要求8的半导体装置,其中该绝缘环的深度不大于30μm。
15.如权利要求8的半导体装置,更包括一表面处理层位于该导电孔上。
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CN104952886A (zh) * | 2015-06-12 | 2015-09-30 | 宁波时代全芯科技有限公司 | 绝缘层覆硅结构及其制备方法 |
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