TW201138040A - Integrated circuit devices and method of forming a bump structure - Google Patents
Integrated circuit devices and method of forming a bump structure Download PDFInfo
- Publication number
- TW201138040A TW201138040A TW99125872A TW99125872A TW201138040A TW 201138040 A TW201138040 A TW 201138040A TW 99125872 A TW99125872 A TW 99125872A TW 99125872 A TW99125872 A TW 99125872A TW 201138040 A TW201138040 A TW 201138040A
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- layer
- copper
- bump
- electrolytic
- metal layer
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Description
201138040 六、發明說明: 【發明所屬之技術領域】 本發明係有關於積體電路的製造,特別有關於積體 電路元件的凸塊結構。 【先前技術】 現代的積體電路是由數百萬計的主動元件形成,例 如電晶體與電容器,這些元件最初是互相隔絕的,但是 之後會互相連接在一起,以形成功能性的電路。典型的 内連線結構包含橫向的内連線,例如金屬線(導線),以及 垂直的内連線,例如導孔與接點,内連線對於現代積體 電路的密度與效能的限制越來越具有影響力。接合墊 (bonding pad)在内連線結構的頂端上形成,並且在個別晶 片的表面上暴露出來,經由接合墊可形成連接晶片至封 裝基底或其他晶粒的電性連接,接合墊可用於導線接合 或覆晶接合。 覆晶封裝技術使用凸塊以建立在晶片的輸入/輸出墊 片(I/O pad)與基底或封裝體的導線架(lead frame)之間的 電性接觸,在結構上,凸塊實際上含有凸塊本身,以及 凸塊下金屬層(under bump metallurgy ; UBM),其位於凸 塊與輸入/輸出墊片之間。凸塊下金屬層通常含有黏著 層、阻障層以及導線層,並且依此順序在輸入/輸出墊片 上形成。凸塊本身基於所使用的材料可分類為銲錫凸 塊、金凸塊、銅柱凸塊以及具有混合金屬的凸塊。近年 來,銅柱凸塊技術逐漸被提出,以取代銲錫凸塊的使用。 0503-A34880TWF/kelly 3 201138040 電子元件藉由銅柱凸塊的方式連接至基底,在使用最少 凸塊架橋的情況下,達到較細微的間距,以降低電路的 電容負載,並且讓電子元件可在較高的辭下執行。銅 柱凸塊覆晶組合具有以下優點:(1)較佳的熱/電子效能, (2)較高的電流承載容積’(3)對於電子遷移具有較佳的阻 抗’因此可延長凸塊的壽命,(4)較少的禱造空隙,亦即 在銅柱凸塊之間具有較—致的間隙。此外,藉由銅柱的 使用來控制銲錫的散佈,可達到較低成本的基底,並且 不需無錯珠狀物的設計。 關於銲錫與銅之間的相互作用以及互相擴散行為已 經被研究,可以發現到,在含錫的銲錫與銅之間的界面, 錫會快速地與銅反應,形成Cu_Sn介金屬化合物 (intermetallic compounds ; IMCs),隨著在界面形 金屬化合物的厚度增加,銲錫接合的強度會減少,造成 凸塊裂開。目前利用在銅柱凸塊上提供鎳覆蓋層,以降 低介金屬化合物的厚度’然而,鎳覆蓋層會在凸塊下金 屬層的㈣製程之後造成㈣底部被⑽,結果在銅柱 的邊緣上鎳層會突出,這將會在銲錫接合與銅柱之間的 界面上造成應力,並引發脫層失效現象。 此外,銅在製造過程中很容易氧化,氧化的銅柱會 導致電子元件對基底的黏著性變差,較差的黏著性會造 成嚴重的可靠度問題,因為會產生較高的漏電流。氧化 的銅柱也會導致底部填膠沿著底部填膠與銅柱之間的界 面裂開,此裂縫會蔓延至底下的低介電常數介電層,或 蔓延至用於接合銅柱至基底的銲錫。因此,需要側壁保 0503-A34880TWF/keIIy . 201138040 -蒦層來避免銅氧化,但是傳統處理銅柱側壁的方法要 3 =成本’並且會有界面脫層問題。目前使用化 子’又’程(lmmersi〇n tin process;)在銅柱側壁上提供錫 層但疋仍然有製造成本、錫與底部填膠之間的黏著力, 以及銲錫潤濕至侧壁上的問題產生 的微細間距封裝技術是一種挑戰。 代曰曰片 【發明内容】 在一實施例中,提供積體電路元件,包括 屬=:::基底上’銅柱設置於: 置於銅柱的側壁表面盥1表面上上\面’以及保護層設 層,包括人晉二 其中保護層為含鎳 層包j含量小於〇 〇1重量百分比_。 在-實施例中,提供積體電路元件 底’凸塊下金屬層設置於半導體基底上,導電 凸塊下金屬層上,具有側壁表面與 岸 解金屬層形成與上表面上,其中保護層由電 供4體:Γ中,提供凸塊結構的形成方法,包括提 成底,形成凸塊下金屬層在半導體基底 隙’進行電解製程,以金屬層填充=層之間形成間 罩層。 具兄此間隙,以及移除遮 0503-A34880TWF/kell· 5 201138040 為了讓本發明之上述目的、特徵、及優點能更明顯 易懂,以下配合所附圖式,作詳細說明如下: 【實施方式】 在此所揭示的實施例提供用於銅柱凸塊技術的側壁 保護製程,其中在銅柱凸塊側壁上的保護層是經由電解 製程所形成的金屬層,在此也稱為電解金屬層。銅柱凸 塊可直接用在半導體晶片的導電墊或重分佈層上,也可 用於覆晶組合或其他相似的應用上。 在本發明實施例中使用參考圖式詳細說明本發明, 如附圖所示,在圖式及說明書描述中盡可能地使用相同 的標號來表示相同或相似的部分。在圖式中,實施例的 形狀及厚度可能被擴大,以達到方便說明及清楚顯示之 目的。說明書的描述直接關於依據此揭示所形成的裴置 之部分元件,或更直接關於與此裝置共同操作的元件。 可以理解的是,這些元件沒有特定的形式,或者可使用 各種形式來描繪。再者,當一層被稱為在另一層上或在 基底上時,這一層也可以是直接在其他層上或在基底 上,或者也可以存在介於中間的其他層。在整篇說明金 中所提及的,,-實施例”表示在此實施例中所#述的特; 特徵、結構或特性是被包含在至少一實施例中。因此, 在整篇說明書中所提及的”在一實施例中”不需要是指相 同的實施例。另外,特定的特徵、結構或特性可以盥一 個或更多實施例以任何適合的方式結合,可以理解的 是’以下配合的圖式並非按尺寸繪製,這些圖式僅用於 〇503-A34880TWF/kelly 6 201138040 說明本發明。· 在此,第1至8圖描繪出依據一示範性實施例,在 形成銅柱凸塊的各製程階段中,部分的半導體元件之剖 面示意圖。 參閱第1圖,用於凸塊製程的示範性半導體基底1〇 被用在半導體積體電路的製造上,並且積體電路可以在 基底中以及/或基底上形成。半導體基底被定義成包括半 導體材料的任何結構,其包含但不限定於:巨塊矽(bulk • silicon)、半導體晶圓、矽覆蓋絕緣層 (silicon-on-insulator; SOI)基底或矽鍺基底,其他的半導 體材料包含也使用第三族(group ΠΙ)、第四族(group IV) 以及第五族(group V)元素的材料。基底1〇更可包括複數 個隔絕特徵(未繪出)’例如淺溝槽隔絕(shallow trench isolation: STI)特徵或石夕的局部氧t(1〇cal 〇xidati(m 〇f silicon: LOCOS)特徵,隔絕特徵可以被定義並且隔絕各 種微電子元件(未繪出)。各種微電子元件的例子可以在包 • 含電晶體的基底1〇内形成,電晶體例如為金氧半場效電 晶體(metal oxide semiconductor field effect transistor ; MOSFET)、互補式金氧半(complementary metal oxide semiconductor;CMOS)電晶體、雙載子接面電晶體(bipolar junction transistor : BJT)、高電壓電晶體、高頻電晶體、 p通道以及/或η通道場效電晶體(PFETs/NFETs)等。此 外,基底10還可包含電阻器、二極體、電容器、電感器、 熔線以及其他合適的元件。可實施各種製程以形成微電 子元件,包含沈積 '蝕刻、離子植入、微影、退火以及 0503-A34880TWF/kelly 7 201138040 其他合適的製程。這些微電子元件互相連接以形成積體 電路元件,例如邏輯元件 '記憶體元件(如靜態隨機存取 s己憶體(SRAM))、射頻(radio frequency ; RF)元件、輸入/ 輸出(input/output ; I/O)元件、系統單晶片 (system-on-chip ; S0C)元件、前述之組合以及其他類型合 適的元件。 基底10更包含層間介電層(未繪出)以及金屬結構(未 繪出)在積體電路之上,在金屬結構内的層間介電層包含 低介電常數介電材料、未摻雜矽玻璃(und〇ped smcate glass; USG)、氮化矽、氮氧化矽或其他常用的材料,低 介電常數介電材料的介電常數值可低於約39或低於約 2.8。在金屬結構中的金屬線可由銅或銅合金形成,在此 技術領域巾具有通常知識者當可瞭解金屬層的詳細形成 方式。墊片區12為形成在頂端層間介電層内的頂端金屬 層,其為導電路線的—部份,並且如果需要,其具有經 由平坦化製程,例如化學機械研磨製程 meChanical polishing ; CMp)處理過的暴露表面。適用於 墊片區12的材料可包含但不限定於例如銅(〇0、!_)、 銘銅(AlCu)、銅合金、或其他可動的導電材料。塾片區 可用在接σ製在中,以連接個別晶片中 圖也顯示出形成在基底10上的鈍化^ 二,-部份的塾…,以容許後續的凸二 貫施例中’鈍化層14由非有機材料形成,其卷 0503-A34880TWF/kelly 201138040 選自於未摻雜矽玻璃、氮化矽、氮氧化矽、氧化石夕以及 前述之組合。在另一實施例中,鈍化層14由高分子層形 成,例如環氧化物(epoxy)、聚亞醯胺(p〇lyimide)、笨環 丁 烯(benzocyclobutene ; BCB)、聚苯。吳 〇坐 (polybenzoxazole ; PBO)以及類似的材料,也可以使用其 他相對軟性,通常是有機的介電材料。 ' 第1圖更顯示出形成在純化層14上的高分子層π, 以及將高分子層16圖案化’形成開口 17暴露出—部份 φ 的墊片區12 ’以容許後續的凸塊形成。開口 I?可小於、 等於或大於開口 15,在一實施例中,開口 17設置在開口 15内。高分子層16由高分子形成,例如環氧化物 (epoxy)、聚亞醯胺(polyimide)、笨環丁—(BCB)、聚苯喝 唑(PBO)以及類似的材料,也可以使用其他相對軟性,通 常是有機的介電材料。在一實施例中,高分子層丨6為聚 亞醯胺層。在另一實施例中,高分子層丨6為聚笨噪吐 (PB0)層。高分子層16是軟性的,因此具有降低在個別 • 基底上的固有應力之功能’此外,高分子層16很容易以 數十微米的厚度形成。 參閱第2圖,在產生的結構上形成凸塊下金屬層 (under-bump-metallurgy ; UBM) 18,其可以由任何數量的 合適技術形成,包含物理氣相沈積(PVD)、化學氣相沈積 (CVD)、電化學沈積(electrochemical deposition ; ECD)、 分子束蠢晶(molecular beam epitaxy ; MBE)、原子層沈積 (ALD)、電鍍以及類似的方式。凸塊下金屬層18在高分 子層16以及墊片區12暴露出來的部分上形成,並且形 0503-A34880TWF/kelly 9 201138040 成在開口 17的側壁及底部上。凸塊下金屬層18包含擴 散阻障層’其由鈦(titanium)、叙(tantalum)、氮化鈦、氮 化组或類似的材料形成。擴散阻障層沈積的厚度介於約 500A至2000A之間,例如厚度約為1000人。凸塊下金屬 層18更可包含銅層,其形成在擴散阻障層上,銅層可由 銅合金形成’其包含銀、鉻、鎳、錫、金以及前述之組 合。銅層沈積的厚度介於約5〇〇A至ιοοοοΑ之間,例如 厚度約為5000A。 接著,參閱第3圖,為了定義凸塊視窗,在凸塊下 金屬層18上提供遮罩層20,並且將遮罩層2〇圖案化 形成開口 21 ’暴露出一部份的凸塊下金屬層18,用於带 成銅柱凸塊(Cu pillar bump)。遮罩層20可以是乾膜咬^ 阻膜,經由塗佈、固化(curing)、去除殘膠(descum)以及 類似的步驟形成,接著進行微影技術以及/或餘刻製程, 例如乾蝕刻以及/或濕蝕刻製程。 參閱第4圖,在開口 21内利用銲錫濕潤性 wettability)部分地或完全地填充導電材料。在一實施例 中’在開口 21内形成銅層22接觸凸塊下金屬層18,銅 層22大抵上是一層包含純元素銅、含有不可避免的雜質 的銅以及含有少量元素的銅合金,例如含有超、銦、錫 鋅、猛、鉻、鈦、鍺、銀、翻、鎮、|g或錘。形成鋼芦 22的方法可包含藏鑛、印刷、電鍵、無電電錢以及常用 的化學氣相沈積(CVD)法,例如利用電化學電的 (electrochemical plating ; ECP)形成銅層 22。在一示範故 實施例中,銅層22的厚度大於25/zm。在另一示範性實 0503-A34880TWF/kelly 10 201138040 施例中,銅層22的厚度大於4〇//m,例如銅層22的厚 度介於約40-50/zm之間,約為45//m,或者介於約4〇_7〇 /z m之間,雖然其厚度也可以更大或更小。銅層22形成 柱狀’因此之後可稱為銅柱22。 然後,如第5圖所示,進行遮罩拉回(puUback)製程, 使得遮罩層20從銅柱22的侧壁22s被拉回,以加寬開 口 21,並在銅柱22的侧壁22s與擴大的開口 21,,的内部 周圍之間留下空隙24。遮罩拉回製程包含微影技術以及/ • 或蝕刻製程,其移除一部份的遮罩層20。 參閱第6圖,在產生的結構上藉由電解製程鍍上保 護層26’保護層26覆蓋銅柱22的上表面22t,並且填充 在銅柱22的侧壁表面22s與遮罩層20之間的空隙24 中。保護層26是藉由電鍍製程從電解槽(electrolytic bath) 中形成的金屬層,其沈積的金屬並未特別限定,此金屬 可以是鎳(Ni)、銅(CU)、銀(Ag)、金(Au)、鈀(Pd)、鉑(Pt)、 錫(Sn)、鋅(Zn)、貴重金屬或前述之組合。電解槽通常含 • 有更多進行沈積製程所需的成分,以及改善沈積金屬層 的品質所需的成分。這些物質例如為晶粒細化劑 (grain-refining agent)、潤濕劑(wetting agent)、光亮劑 (brightener)、錯合劑(complexing agent)以及抑制劑 (inhibitor)。當沈積製程實行時,這些有機以及/或無機添 加物/成分會從電解槽中更快或更慢地消耗、破壞或移 除。因此,這些成分的濃度會隨著時間更快或更慢地降 低。 在一實施例中,保護層26是經由鎳電鍍製程所形成 0503-A34880TWF/ke1Iy 11 201138040 包含將物體放置在以錄作為陰極的電解槽中, i要沈積的金屬棒也放置在此電解射,並與陽極 ^-旦施加電壓,要沈積㈣正離子會朝向負極遷移, 在此沈積形成金屬層。所產生的鎳層中的主要雜質 可包含碳(〇、氫⑻以及/或硫⑻,藉由此方法產 純度錄層只具有極少量的雜質,雜質的濃度取決於製: 控制而改變’電解的錄沈積所含㈣含量少於0.01重量 百分比。 里 在另-實施例中,保護層26是經由銅電錢製程所形 成的銅層’在電解射具有專㈣有機以及/或無機添加 ^ ’所產生的銅層中的主要雜質可包含氣(Ο)、硫⑻、 厌()乂及/或氧(〇) ’藉由此方法I生的高純度銅層只含 有極>的雜質’雜質的濃度取決於製程控制而改變。電 解的銅沈積所含有的納(Na)含量少於G.G1重量百分比, 以及鐵(Fe),量少於_重量百分比。在其他實施例中, 保濩層26是經由銀電鍍製程所形成的銀層,在電解槽中 具有專用的有機以及/或無機添加物,所產生的銀層中的 主要雜質可包含卸(K)、碳(C)、氧(0)以及/或氮(N)。電解 的銀'尤積所含有的鈉(Na)含量少於〇.〇1重量百分比。在 其他實施例中’保護層26是經由金電鍍製程所形成的金 在電解槽中具有專用的有機以及/或無機添加物,所 ^生的金層中的主要雜質可包含硫(s)、鈦(Ti)、鈉(Na)、 = (=)、氯(Η)以及/或氧(〇)。電解的金沈積所含有的鉀(κ) 3里少於0.01重量百分比,以及氣(Cl)含量少於0.01重 量百分比。 〇503-A34880TWF/kell· 12 201138040 在形成保護層26之後,選擇性地在保護層26的上 表面26t上以及在擴大的開口 21”内形成覆蓋層28。覆蓋 層28可作為阻障層,以避免銅柱22内的銅擴散至接合 材料,例如銲錫合金中,接合材料係用於接合基底10至 外部特徵,防止銅的擴散可以增加封裝的可靠度以及增 加接合強度。覆蓋層28可包含金(Au)、錫(Sn)、錫錯 (SnPb)、銀(Ag)、鈀(Pd)、銦(In)、鎳鈀金(NiPdAu)、鎳 金(NiAu)、其他相似的材料,或藉由電鍍法形成的合金。 φ 覆蓋層28的厚度約為l-10#m,在一些實施例中,覆蓋 層28為多層結構,包含Au、Pd、Ni合金、Au合金或 Pd合金。在一些實施例中,覆蓋層28為銲錫層,由Sn、 SnAg、Sn-Pd、SnAgCu(具有的Cu重量百分比少於〇.3%)、 SnAgZn、SnZn、SnBi-In、Sn-In、Sn-Au、SnPb、SnCu、
SnZnln或SnAgSb等,藉由電鍍製程形成。在一些實施 例中,覆蓋層28為多層結構,包含金屬層與録錫層。 參閱第7圖’移除遮罩層20,暴露出在擴大的開口 # 21”内形成之金屬結構以及底下的凸塊下金屬層18。在此 例中,遮罩層20是乾膜,其可以使用驗性溶液移除。如 果遮罩層20是由光阻形成,則可以使用丙酮(acetone)、 N-曱基0比π各烧酮(n-methyl pyrrolidone ; NMP)、二曱基亞 砜(dimethyl sulfoxide ; DMSO)、二甘醇胺(aminoeth〇xy ethanol)以及類似的溶劑移除。 然後,如第8圖所示’使用金屬結構作為遮罩,將 凸塊下金屬層18暴露出來的部分蝕刻,暴露出底下的高 分子層16的表面區16s。在一示範性實施例中,餘刻凸 0503-A34880TWF/keIly 13 201138040 塊下金屬層18的步驟為乾蝕刻或濕蝕刻,濕钱刻例如為 使用氨酸(ammonia-based acid)進行的等向性濕姓刻’或 者乾蝕刻製程,例如為標準的反應式離子蝕刻法(reactive ion etch ; RIE)程序。因此,所完成的凸塊結構包含在金 屬墊區域12上形成的凸塊下金屬層18、在凸塊下金屬層 18上形成的銅柱22、在銅柱22的上表面22t及侧壁表面 22s上的保護層26,以及在保護層26的上表面26t上的 選擇性覆蓋層28。因為保護層26是電解金屬層,可利用 感應耦合電漿(ICP)或掃瞄式電子顯微鏡能量分散X射線 能譜分析系統(SEM-EDX)進行分析,結果顯示在保護層 26内關鍵性的雜質含量非常低(少於0.01 wt%)。接著,基 底10被切割並封裝在封裝基底或另一晶粒上,並利用錫 球或銅凸塊固定在封裝基底或其他晶粒上的墊片上。 此揭示提供由電解金屬層形成的侧壁保護層’以避 免銅柱側壁氧化,並且增加在銅柱侧壁與後續形成的底 部填充材料之間的黏著力。相較於傳統的浸錫(immersion Sn)製程,以及接著進行退火製程的方法,在凸塊下金屬 層的蝕刻步驟之前,於鋼柱側壁上以電鍍法形成保護層 可以節省製程成本,並且藉由控制電鍍製程的時間,很 容易調整膜的厚度’以避免底切(undercut)問題發生,並 且克服Ni突出(overhanging)的結構產生。再者,凸塊結 構可以阻止應力集中在一些點上,並且因而解決從銅柱 側壁上剝離或脫層的問題。 雖然本發明已揭露較佳實施例如上,然其並非用 以限定本發明,在此技術領域中具有通常知識者當可 0503-A34880TWF/kel!y 14 201138040 瞭解,在不脫離本發明之精神和範圍内,當可做些許 更動與潤飾。因此,本發明之保護範圍當視後附之申 請專利範圍所界定為準。
0503-A34880TWF/kelly 15 201138040 【圖式簡單說明】 第1至8圖係顯示依據一示範性實施例,形成銅柱 凸塊的方法之剖面示意圖。 【主要元件符號說明】 10〜基底; 12〜墊片區; 14〜純化層; 15、17、21〜開口; 16〜高分子層; 16s〜高分子層表面區; 鲁 18〜凸塊下金屬層; 20〜遮罩層; 21”〜擴大的開口; 22〜銅柱; 22t〜銅柱的上表面; 22s〜銅柱的側壁表面; 24〜空隙; 2 6〜保護層; · 26t〜保護層的上表面; 28〜覆蓋層。 0503-A34880TWF/kelly 16
Claims (1)
- 201138040 七、申請專利範圍: h一種積體電路元件,包括: 一半導體基底; 一凸塊下金屬層,設置於該半導體基底上; 鋼柱’设置於該凸塊下金屬層上,且具有一側壁 表面與一上表面;以及 保護層’ S又置於該銅柱的該侧壁表面與該卜表面 上,其中該保護層為一含鎳層,包括含量小於0.01重量 百分比的碟。 2.如申請專利範圍第1項所述之積體電路元件,其中 該含錄層包括含有硫。 3·如申請專利範圍第1項所述之積體電路元件,更包 括一覆蓋層設置於該銅柱上表面上的該保護層上,其中 該覆蓋層為一含金層或一銲錫層。 4. 一種積體電路元件,包括: 一半導體基底; 一凸塊下金屬層,設置於該半導體基底上; 導電柱,s史置於該凸塊下金屬層上,且具有一侧 壁表面與一上表面;以及 一保護層,設置於該導電柱的該側壁表面與該上表 面上其中該保護層由一電解金屬層形成。 5. 如申請專利範圍» 4項所述之積體電路元件,其中 該該保護層為-電解鎳層、一電解金層、一電解銅層或 一電解銀層。 6. 如申請專利範圍第4項所述之積體電路元件,更包 0503-A34880TWF/keliy 17 201138040 由兮層°又置於該導電柱上表面上的該保護層上,其 中該7覆_盖層為-含金層或—銲錫層,料妹為銅柱 •種凸塊結構的形成方法,包括: 提供一半導體基底; 形成一凸塊下金屬層在該半導體基底上; 形成-遮罩層在該凸塊下金屬層上 具有一開口,暴露出一部份的該凸塊下金屬層遮罩層 形成一銅層在該遮罩層的該開口内; 形成遮罩層的—部份,在該銅層與該遮罩層之間 及 進行一電解製程,以形成一金屬層填充該間隙;以 移除該遮罩層。 法 m 法 面1 ===第7項所述之凸塊結構的形成方 ' 日已錄或金’該銅層的厚度大於40# =申請專利範圍第7項所述之凸塊 其中該電解製程形成該金屬 形成方 战及金屬層,以覆蓋該銅層的表 10.如申請專利範圍第 法,更包括: 、α之凸塊結構的形成方 於移除該遮罩層之前,形成蓋 該開口内之該金屬層上。 復盖層在該遮罩層的 0503-A34880TWF/keliy 18
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2013
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CN103515341B (zh) * | 2012-06-20 | 2016-12-21 | 讯忆科技股份有限公司 | 晶圆焊垫的化镀镍凸块结构及其制造方法 |
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TWI551199B (zh) * | 2014-04-16 | 2016-09-21 | 矽品精密工業股份有限公司 | 具電性連接結構之基板及其製法 |
TWI488244B (zh) * | 2014-07-25 | 2015-06-11 | Chipbond Technology Corp | 具有凸塊結構的基板及其製造方法 |
US10892241B2 (en) | 2016-06-20 | 2021-01-12 | Sony Corporation | Substrate device, electronic apparatus, and method for manufacturing substrate device |
Also Published As
Publication number | Publication date |
---|---|
CN102237316B (zh) | 2015-08-12 |
US9006097B2 (en) | 2015-04-14 |
US8492891B2 (en) | 2013-07-23 |
US20130295762A1 (en) | 2013-11-07 |
CN102237316A (zh) | 2011-11-09 |
US20110260317A1 (en) | 2011-10-27 |
TWI427751B (zh) | 2014-02-21 |
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