TW200529408A - Semiconductor device and its manufacturing method - Google Patents

Semiconductor device and its manufacturing method Download PDF

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Publication number
TW200529408A
TW200529408A TW93133221A TW93133221A TW200529408A TW 200529408 A TW200529408 A TW 200529408A TW 93133221 A TW93133221 A TW 93133221A TW 93133221 A TW93133221 A TW 93133221A TW 200529408 A TW200529408 A TW 200529408A
Authority
TW
Taiwan
Prior art keywords
semiconductor wafer
semiconductor
electrodes
leads
lead
Prior art date
Application number
TW93133221A
Other languages
English (en)
Chinese (zh)
Inventor
Kouichi Kanemoto
Kazunari Suzuki
Toshihiro Shiotsuki
Hideyuki Suga
Original Assignee
Renesas Tech Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Tech Corp filed Critical Renesas Tech Corp
Publication of TW200529408A publication Critical patent/TW200529408A/zh

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/811—Multiple chips on leadframes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H10W72/07351—Connecting or disconnecting of die-attach connectors characterised by changes in properties of the die-attach connectors during connecting
    • H10W72/07352—Connecting or disconnecting of die-attach connectors characterised by changes in properties of the die-attach connectors during connecting changes in structures or sizes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/321—Structures or relative sizes of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/536—Shapes of wire connectors the connected ends being ball-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5522—Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/853—On the same surface
    • H10W72/865—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/932—Plan-view shape, i.e. in top view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/24—Configurations of stacked chips at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/736—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Lead Frames For Integrated Circuits (AREA)
  • Wire Bonding (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
TW93133221A 2003-11-20 2004-11-01 Semiconductor device and its manufacturing method TW200529408A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2003390029A JP2005150647A (ja) 2003-11-20 2003-11-20 半導体装置及びその製造方法

Publications (1)

Publication Number Publication Date
TW200529408A true TW200529408A (en) 2005-09-01

Family

ID=34587426

Family Applications (1)

Application Number Title Priority Date Filing Date
TW93133221A TW200529408A (en) 2003-11-20 2004-11-01 Semiconductor device and its manufacturing method

Country Status (4)

Country Link
US (1) US20050110127A1 (https=)
JP (1) JP2005150647A (https=)
KR (1) KR20050049346A (https=)
TW (1) TW200529408A (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112447691A (zh) * 2019-08-28 2021-03-05 富士电机株式会社 半导体装置及半导体装置的制造方法

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4602223B2 (ja) * 2005-10-24 2010-12-22 株式会社東芝 半導体装置とそれを用いた半導体パッケージ
KR100844630B1 (ko) * 2006-03-29 2008-07-07 산요덴키가부시키가이샤 반도체 장치
US9202776B2 (en) * 2006-06-01 2015-12-01 Stats Chippac Ltd. Stackable multi-chip package system
TWI327365B (en) * 2007-01-19 2010-07-11 Chipmos Technologies Inc Zigzag-stacked chip package structure
JP4751351B2 (ja) * 2007-02-20 2011-08-17 株式会社東芝 半導体装置とそれを用いた半導体モジュール
JP2008270302A (ja) * 2007-04-16 2008-11-06 Sanyo Electric Co Ltd 半導体装置
KR100881198B1 (ko) * 2007-06-20 2009-02-05 삼성전자주식회사 반도체 패키지 및 이를 실장한 반도체 패키지 모듈
KR101557273B1 (ko) 2009-03-17 2015-10-05 삼성전자주식회사 반도체 패키지
KR101563630B1 (ko) * 2009-09-17 2015-10-28 에스케이하이닉스 주식회사 반도체 패키지
JP2014036179A (ja) * 2012-08-10 2014-02-24 Ps4 Luxco S A R L 半導体装置
JP6110769B2 (ja) * 2013-09-25 2017-04-05 ルネサスエレクトロニクス株式会社 半導体装置
JP5856274B2 (ja) * 2014-11-06 2016-02-09 ルネサスエレクトロニクス株式会社 半導体装置、半導体装置の製造方法、及びリードフレーム
JP2018049942A (ja) * 2016-09-21 2018-03-29 アイシン精機株式会社 変位センサ
US10373895B2 (en) * 2016-12-12 2019-08-06 Infineon Technologies Austria Ag Semiconductor device having die pads with exposed surfaces
US10714418B2 (en) * 2018-03-26 2020-07-14 Texas Instruments Incorporated Electronic device having inverted lead pins
JP7192688B2 (ja) 2019-07-16 2022-12-20 Tdk株式会社 電子部品パッケージ
US11469163B2 (en) * 2019-08-02 2022-10-11 Semiconductor Components Industries, Llc Low stress asymmetric dual side module

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5615475A (en) * 1995-01-30 1997-04-01 Staktek Corporation Method of manufacturing an integrated package having a pair of die on a common lead frame
US6476474B1 (en) * 2000-10-10 2002-11-05 Siliconware Precision Industries Co., Ltd. Dual-die package structure and method for fabricating the same
JP2002231882A (ja) * 2001-02-06 2002-08-16 Mitsubishi Electric Corp 半導体装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112447691A (zh) * 2019-08-28 2021-03-05 富士电机株式会社 半导体装置及半导体装置的制造方法

Also Published As

Publication number Publication date
US20050110127A1 (en) 2005-05-26
JP2005150647A (ja) 2005-06-09
KR20050049346A (ko) 2005-05-25

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