CN101211897A - 多芯片半导体封装结构及封装方法 - Google Patents

多芯片半导体封装结构及封装方法 Download PDF

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CN101211897A
CN101211897A CNA2006101482399A CN200610148239A CN101211897A CN 101211897 A CN101211897 A CN 101211897A CN A2006101482399 A CNA2006101482399 A CN A2006101482399A CN 200610148239 A CN200610148239 A CN 200610148239A CN 101211897 A CN101211897 A CN 101211897A
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die pad
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王津洲
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Semiconductor Manufacturing International Shanghai Corp
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Abstract

一种多芯片半导体封装方法，包括下列步骤：提供引线框架和至少两个芯片，所述引线框架包括管芯垫和位于管芯垫外围的引线，在管芯垫上有通孔且位于管芯垫边缘；将第一芯片的基底相对面与管芯垫粘合；穿过通孔将第一芯片与引线电连接；将第二芯片的基底面与管芯垫粘合，所述第二芯片与第一芯片位于管芯垫的相对面；将第二芯片与引线电连接；将其余芯片堆叠在第一芯片和第二芯片之上且与引线电连接；将至少两个芯片和引线框架封装成型。经过上述步骤，简化多芯片封装制程的效果，提升封装电路的密度；同时降低制造成本，并增强电路运作的性能。

Description

多芯片半导体封装结构及封装方法
技术领域
本发明涉及多芯片半导体封装结构及封装方法，尤其涉及将多个芯片通过引线框架相互连接的半导体封装结构及封装方法。
背景技术
随着电子元件的小型化、轻量化及多功能化的需求日渐增加，导致半导体封装密度不断增加，因而必须缩小封装尺寸及封装时所占的面积。为满足上述的需求所发展出的技术中，多芯片半导体封装技术对于封装芯片的整体成本、效能及可靠度有着深远的贡献。
现有多芯片半导体封装制造方法如专利号为US6674173的美国专利公开的技术方案所描述，包括下列步骤：如图1A所示，首先，将第一芯片100正置装配于引线框架102的管芯垫104上，所述第一芯片100上分布有第一焊盘106，第一芯片100带有第一焊盘106的面为第一基底相对面，与第一基底相对面对应的为第一基底面；通过第一粘合剂层105将第一芯片100的第一基底面与管芯垫104粘合；用第一键合线108将第一焊盘106与引线框架102的引线103进行电连接。
如图1B所示，在与第一芯片100不同侧的管芯垫104上倒置装配第二芯片110，所述第二芯片110上有第二焊盘114，第二芯片110带有第二焊盘106的面为第二基底相对面，与第二基底相对面对应的为第二基底面；通过第二粘合剂层112将第二芯片110的第二基底相对面与管芯垫104粘合；用第二键合线116将第二焊盘114与引线框架102的引线103进行电连接。由于第一芯片100与第二芯片110属于相同类型芯片，第二芯片110倒置，使第二芯片110与第一芯片100内部接线不对称，因此需要在第二芯片110上进行重新布线，使第二芯片110上的第二焊盘110位置与第一芯片100的第一焊盘106位置镜像对称，
如图1C所示，最后以封装胶体118将第一芯片100、第二芯片110以及引线框架102封装成型，两端仅露出引线框架102的引线103的一部分区域。
现有技术将单层结构的引线框架两侧用粘合剂粘合芯片以形成多芯片半导体封装，由于引线框架两侧的芯片类型一致，但安置方向不同，使两侧芯片的内部接线不对称，则需要对其中一侧的芯片上进行进一步的布线加工，使引线框架两侧的芯片上的焊盘成镜像对称，增加了芯片的封装工艺复杂度，进而提高了成本。
发明内容
本发明解决的问题是提供一种多芯片半导体封装结构和封装方法，防止封装工艺复杂，增加普遍应用的困难。
为解决上述问题，本发明提供一种多芯片半导体封装结构，包括：引线框架和至少两个芯片，所述引线框架包括管芯垫和位于管芯垫外围的引线，其中第一芯片和第二芯片位于管芯垫相对面，其余芯片堆叠在第一芯片和第二芯片之上，第二芯片的基底面与管芯垫粘合，管芯垫上有通孔且位于管芯垫边缘，第一芯片的基底相对面与管芯垫粘合，穿过通孔将第一芯片与引线电连接。
所述通孔边缘是封闭的与引线不连通，或者是开放的与引线连通。
穿过通孔将第一芯片与引线电连接的是键合线，所述键合线的材料是金、铜、铝或铜铝合金。
第一芯片和第二芯片通过薄膜绝缘隔离物质粘合于引线框架上，所述薄膜绝缘隔离物质是有机化合物，为环氧树脂或聚酰亚胺。
本发明提供一种多芯片半导体封装方法，包括下列步骤：提供引线框架和至少两个芯片，所述引线框架包括管芯垫和位于管芯垫外围的引线，在管芯垫上有通孔且位于管芯垫边缘；将第一芯片的基底相对面与管芯垫粘合；穿过通孔将第一芯片与引线电连接；将第二芯片的基底面与管芯垫粘合，所述第二芯片与第一芯片位于管芯垫的相对面；将第二芯片与引线电连接；将其余芯片堆叠在第一芯片和第二芯片之上且与引线电连接；将至少两个芯片和引线框架封装成型。
所述通孔边缘是封闭的与引线不连通，或者是开放的与引线连通。
穿过通孔将第一芯片与引线电连接的是键合线，所述键合线的材料是金、铜、铝或铜铝合金。
第一芯片和第二芯片通过薄膜绝缘隔离物质粘合于引线框架上，所述薄膜绝缘隔离物质是有机化合物，为环氧树脂或聚酰亚胺。
与现有技术相比，本发明具有以下优点：本发明将第一芯片的基底相对面与管芯垫粘合并通过通孔与引线电连接；第二芯片的基底面与管芯垫粘合，所述第二芯片与第一芯片位于管芯垫的相对面。因为第一芯片和第二芯片是同类型的芯片并且都是正置的，因此芯片内部接线对称，第一芯片和第二芯片上的焊盘成镜像对称，从而无需进行重新布线加工，达到简化多芯片封装工艺的效果，提升封装电路的密度；同时降低制造成本，并增强电路运作的性能。
附图说明
图1A至图1C是现有技术多芯片半导体封装示意图；
图2为本发明多芯片半导体封装流程图；
图3为本发明多芯片半导体封装第一实施例引线框架示意图；
图3A至图3C是本发明多芯片半导体封装第一实施例示意图；
图4为本发明多芯片半导体封装第二实施例引线框架示意图；
图4A至图4C是本发明多芯片半导体封装第二实施例示意图。
具体实施方式
现有技术将单层结构的引线框架两侧用粘合剂粘合芯片以形成多芯片半导体封装，由于引线框架两侧的芯片类型一致，但安置方向不同，使两侧芯片的内部接线不对称，则需要对其中一侧的芯片上进行进一步的布线加工，使引线框架两侧的芯片上的焊盘成镜像对称，增加了芯片的封装工艺复杂度，进而提高了成本。：本发明将第一芯片的基底相对面与管芯垫粘合并通过通孔与引线电连接；第二芯片的基底面与管芯垫粘合，所述第二芯片与第一芯片位于管芯垫的相对面。因为第一芯片和第二芯片是同类型的芯片并且都是正置的，因此芯片内部接线对称，第一芯片和第二芯片上的焊盘成镜像对称，从而无需进行重新布线加工，达到简化多芯片封装工艺的效果，提升封装电路的密度；同时降低制造成本，并增强电路运作的性能。
本发明的多芯片半导体封装结构，包括：引线框架和至少两个芯片，所述引线框架包括管芯垫和位于管芯垫外围的引线，其中第一芯片和第二芯片位于管芯垫相对面，其余芯片堆叠在第一芯片和第二芯片之上，第二芯片的基底面与管芯垫粘合，其特征在于，管芯垫上有通孔且位于管芯垫边缘，第一芯片的基底相对面与管芯垫粘合，穿过通孔将第一芯片与引线电连接。
图2为本发明多芯片半导体封装流程图。如图2所示，执行步骤S101提供引线框架和至少两个芯片，所述引线框架包括管芯垫和位于管芯垫外围的引线，在管芯垫上有通孔且位于管芯垫边缘；执行步骤S102将第一芯片的基底相对面与管芯垫粘合；执行步骤S103穿过通孔将第一芯片与引线电连接；执行步骤S104将第二芯片的基底面与管芯垫粘合，所述第二芯片与第一芯片位于管芯垫的相对面；执行步骤S105将第二芯片与引线电连接；执行步骤S106将其余芯片堆叠在第一芯片和第二芯片之上且与引线电连接；执行步骤S107将至少两个芯片和引线框架封装成型。
图3为本发明多芯片半导体封装第一实施例引线框架示意图。如图3所示，引线框架202包括管芯垫204和位于管芯垫204外围的引线203，引线203以梳形向外延伸且与管芯垫204隔开；所述管芯垫204上有形状相同且数量和位置与引线204数量和位置对应的封闭通孔207，封闭通孔207位于管芯垫204边缘，其中标号为a的封闭通孔与标号为1的引线对应......标号为g的封闭通孔与标号为7的引线对应、标号h的封闭通孔与标号为8的引线对应......标号为n的封闭通孔与标号为14的引线对应。
本实施例中，所述引线框架202为单层结构。
本实施例既可以是双列直插式封装型引线框架，也可以是四方扁平封装型引线框架。
本实施例中，所述封闭通孔207是管芯垫204边缘封闭，封闭通孔207与引线203不连通；所述封闭通孔207的数量可以是与引线203的数量一一对应，且各个封闭通孔207的大小一致，也可以是封闭通孔207的数量与引线203的数量不一致，几个引线203可以共用一个封闭通孔207，只要封闭通孔207大小不会使管芯垫204与整个引线框架202断开，并且能使管芯垫204上有区域承载芯片。
图3A至图3C是本发明多芯片半导体封装第一实施例示意图。如图3A所示，首先，将第一芯片210放置于如图3所示的引线框架202的管芯垫204上，并通过第一粘合剂层212将第一芯片210的第一基底相对面与管芯垫204粘合，所述第一芯片210上具有第一焊盘214，其中具有第一焊盘214的第一芯片210表面为第一基底相对面，与第一基底相对面对应的为第一基底面；第一键合线216穿过管芯垫204上的封闭通孔207将第一芯片210上的第一焊盘214与引线框架202的引线203进行一一对应电连接。
本实施例中，第一粘合剂层212为薄膜绝缘隔离物质，所述薄膜绝缘隔离物质是有机化合物，具体例如环氧树脂或聚酰亚胺。
所述第一焊盘214的材料是金属或合金，具体例如铜、铝或铜铝合金。
第一键合线216的材料是金、铜、铝或铜铝合金。
如图3B所示，在与第一芯片210不同侧的引线框架202的管芯垫上配置第二芯片200，通过第二粘合剂层205将第二芯片200的第二基底面与管芯垫204粘合，所述第二芯片200上具有第二焊盘206，其中具有第二焊盘206的第二芯片200表面为第二基底相对面，与第二基底相对面对应的为第二基底面；然后，通过第二键合线208将第二芯片200上的第二焊盘206与引线框架202上的引线203。由于第一芯片210与第二芯片200属于相同类型芯片，同样正置安装于管芯垫204上，这样使第一芯片210和第二芯片200的内部接线对称，从而第一芯片210上的第一焊盘214位置与第二芯片200的第二焊盘206位置镜像对称，因此不需要在第一芯片200上进行重新布线。
本实施例中，第二粘合剂层205为薄膜绝缘隔离物质，所述薄膜绝缘隔离物质的材料是有机化合物，具体例如环氧树脂或聚酰亚胺。
所述第二焊盘206的材料是金属或合金，具体例如铜、铝或铜铝合金。
第二键合线208的材料是金、铜、铝或铜铝合金。
如图3C所示，最后以封装胶体218将第一芯片210、第二芯片200以及引线框架202封装成型，仅露出引线框架202的引线203的一部分区域。
本实施例中，采用两个芯片分别放置于引线框架的不同侧，并且其中一个芯片带焊盘的表面与引线框架粘合。除实施例外，还可以就一个芯片将带焊盘的表面与引线框架粘合并且键合线穿过引线框架上的封闭通孔将芯片上的焊盘与引线连接，省去了在芯片上重新布线的过程；而且可以在引线框架的不同侧分别堆叠两个芯片。
继续参考图3A至图3C，引线框架202包括管芯垫204和位于管芯垫204外围的引线203，其中管芯垫204上具有封闭通孔207，且封闭通孔207位于管芯垫207边缘；第一芯片210，位于引线框架202上，并且通过第一粘合剂层212与管芯垫204粘合，其中与管芯垫204粘合的是第一基底相对面；第一焊盘214，位于第一芯片210的基底相对面；第一键合线216，穿过封闭通孔207将第一焊盘214与引线203电连接；第二芯片200，位于与第一芯片210不同侧的引线框架202上，且通过第二粘合剂层205与管芯垫204粘合，其中与管芯垫204粘合的是第二基底面；第二焊盘206，位于第二芯片200的基底面；第二键合线208，将第二焊盘206与引线203电连接。
图4为本发明多芯片半导体封装第二实施例引线框架示意图。如图4所示，引线框架302包括管芯垫304和位于管芯垫304外围的引线303，引线303以梳形向外延伸且与管芯垫304隔开；所述管芯垫304上有形状相同且数量和位置与引线304数量和位置对应的开放通孔307，且开放通孔307位于管芯垫304边缘，其中标号为b的开放通孔与标号为2的引线对应......标号为c的开放通孔与标号为3的引线对应、标号d的开放通孔与标号为4的引线对应......标号为e的开放通孔与标号为5的引线对应。
本实施例中，所述引线框架302为单层结构。
本实施例既可以是双列直插式封装型引线框架，也可以是四方扁平封装型引线框架。
本实施例中，所述开放通孔307是管芯垫304边缘开放，开放通孔307与引线303连通；所述开放通孔307的数量可以是与引线303的数量一一对应，且各个开放通孔307的大小一致，也可以是开放通孔307的数量与引线303的数量不一致，几个引线303可以共用一个开放通孔307，只要开放通孔307大小不会使管芯垫304与整个引线框架302断开，并且能使管芯垫304上有区域承载芯片。
图4A至图4C是本发明堆叠式多芯片半导体封装第二实施例示意图。如图4A所示，首先，将第一芯片310放置于如图4所示的引线框架302的管芯垫304上，并通过第一粘合剂层312将第一芯片310的第一基底相对面与管芯垫304粘合，所述第一芯片310上具有第一焊盘314，其中具有第一焊盘314的第一芯片310表面为第一基底相对面，与第一基底相对面对应的为第一基底面；第一键合线316穿过管芯垫304上的开放通孔307将第一芯片310上的第一焊盘314与引线框架302的引线303进行一一对应电连接。
本实施例中，第一粘合剂层312为薄膜绝缘隔离物质，所述薄膜绝缘隔离物质的材料是有机化合物，具体例如环氧树脂或聚酰亚胺。
所述第一焊盘314的材料是金属或合金，具体例如铜、铝或铜铝合金。
第一键合线316的材料是金、铜、铝或铜铝合金。
如图4B所示，在与第一芯片310不同侧的引线框架302的管芯垫上配置第二芯片300，通过第二粘合剂层305将第二芯片300的第二基底面与管芯垫304粘合，所述第二芯片300上具有第二焊盘306，其中具有第二焊盘306的第二芯片300表面为第二基底相对面，与第二基底相对面对应的为第二基底面；然后，通过第二键合线308将第二芯片300上的第二焊盘306与引线框架302上的引线303。由于第一芯片310与第二芯片300属于相同类型芯片，同样正置安装于管芯垫304上，这样使第一芯片310和第二芯片300的内部接线对称，从而第一芯片310上的第一焊盘314位置与第二芯片300的第二焊盘306位置镜像对称，因此不需要在第一芯片300上进行重新布线。
本实施例中，第二粘合剂层305为薄膜绝缘隔离物质，所述薄膜绝缘隔离物质的材料是有机化合物，具体例如环氧树脂或聚酰亚胺。
所述第二焊盘306的材料是金属或合金，具体例如铜、铝或铜铝合金。
第二键合线308的材料是金、铜、铝或铜铝合金。
如图4C所示，最后以封装胶体318将第一芯片310、第二芯片300以及引线框架302封装成型，仅露出引线框架302的引线303的一部分区域。
本实施例中，采用两个芯片分别放置于引线框架的不同侧，并且其中一个芯片带焊盘的表面与引线框架粘合。除实施例外，还可以就一个芯片将带焊盘的表面与引线框架粘合并且键合线穿过引线框架上的开放通孔将芯片上的焊盘与引线连接，省去了在芯片上重新布线的过程；而且可以在引线框架的不同侧分别堆叠两个芯片。
继续参考图4A至图4C，引线框架302包括管芯垫304和位于管芯垫204外围的引线303，其中管芯垫304上具有开放通孔307，且开放通孔307位于管芯垫304边缘；第一芯片310，位于引线框架302上，并且通过第一粘合剂层312与管芯垫304粘合，其中与管芯垫304粘合的是第一基底相对面；第一焊盘314，位于第一芯片310的基底相对面；第一键合线316，穿过开放通孔307将第一焊盘314与引线303电连接；第二芯片300，位于与第一芯片310不同侧的引线框架302上，且通过第二粘合剂层305与管芯垫304粘合，其中与管芯垫304粘合的是第二基底面；第二焊盘306，位于第二芯片300的基底面；第二键合线308，将第二焊盘306与引线303电连接。
本发明虽然以较佳实施例公开如上，任何本领域技术人员在不脱离本发明的精神和范围内，都可以做出可能的变动和修改，因此本发明的保护范围应当以本发明权利要求所界定的范围为准。

Claims (12)

1.一种多芯片半导体封装结构，包括：引线框架和至少两个芯片，所述引线框架包括管芯垫和位于管芯垫外围的引线，其中第一芯片和第二芯片位于管芯垫相对面，其余芯片堆叠在第一芯片和第二芯片之上，第二芯片的基底面与管芯垫粘合，其特征在于，管芯垫上有通孔且位于管芯垫边缘，第一芯片的基底相对面与管芯垫粘合，穿过通孔将第一芯片与引线电连接。
2.根据权利要求1所述的多芯片半导体封装结构，其特征在于：所述通孔边缘是封闭的与引线不连通，或者是开放的与引线连通。
3.根据权利要求2所述的多芯片半导体封装结构，其特征在于：穿过通孔将第一芯片与引线电连接的是键合线。
4.根据权利要求3所述的多芯片半导体封装结构，其特征在于：所述键合线的材料是金、铜、铝或铜铝合金。
5.根据权利要求1所述的多芯片半导体封装结构，其特征在于：第一芯片和第二芯片通过薄膜绝缘隔离物质粘合于管芯垫上。
6.根据权利要求5所述的多芯片半导体封装结构，其特征在于：所述薄膜绝缘隔离物质是有机化合物，为环氧树脂或聚酰亚胺。
7.一种多芯片半导体封装方法，其特征在于，包括下列步骤：
提供引线框架和至少两个芯片，所述引线框架包括管芯垫和位于管芯垫外围的引线，在管芯垫上有通孔且位于管芯垫边缘，；
将第一芯片的基底相对面与管芯垫粘合；
穿过通孔将第一芯片与引线电连接；
将第二芯片的基底面与管芯垫粘合，所述第二芯片与第一芯片位于管芯垫的相对面；
将第二芯片与引线电连接；
将其余芯片堆叠在第一芯片和第二芯片之上且与引线电连接；
将至少两个芯片和引线框架封装成型。
8.根据权利要求7所述的多芯片半导体封装方法，其特征在于：所述通孔边缘可以是封闭的与引线不连通，也可以是开放的与引线连通。
9.根据权利要求8所述的多芯片半导体封装方法，其特征在于：穿过通孔将第一芯片与引线电连接的是键合线。
10.根据权利要求9所述的多芯片半导体封装方法，其特征在于：所述键合线的材料是金、铜、铝或铜铝合金。
11.根据权利要求7所述的多芯片半导体封装方法，其特征在于：第一芯片和第二芯片通过薄膜绝缘隔离物质粘合于引线框架上。
12.根据权利要求11所述的多芯片半导体封装方法，其特征在于：所述薄膜绝缘隔离物质是有机化合物，为环氧树脂或聚酰亚胺。
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CN109585392A (zh) * 2017-09-29 2019-04-05 英飞凌科技股份有限公司 包括设置在两个基底之间的半导体芯片和引线框的半导体芯片封装件
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CN109585392A (zh) * 2017-09-29 2019-04-05 英飞凌科技股份有限公司 包括设置在两个基底之间的半导体芯片和引线框的半导体芯片封装件
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