CN106531713A - 电子装置和封装 - Google Patents

电子装置和封装 Download PDF

Info

Publication number
CN106531713A
CN106531713A CN201610580181.9A CN201610580181A CN106531713A CN 106531713 A CN106531713 A CN 106531713A CN 201610580181 A CN201610580181 A CN 201610580181A CN 106531713 A CN106531713 A CN 106531713A
Authority
CN
China
Prior art keywords
lead frame
frame element
encapsulated
tube core
closing line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201610580181.9A
Other languages
English (en)
Inventor
沙亚通·萨克朗
威瓦·坦翁旺
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP BV
Original Assignee
NXP BV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NXP BV filed Critical NXP BV
Publication of CN106531713A publication Critical patent/CN106531713A/zh
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R33/00—Arrangements or instruments for measuring magnetic variables
    • G01R33/0047—Housings or packaging of magnetic sensors ; Holders
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49537—Plurality of lead frames mounted in one device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01P—MEASURING LINEAR OR ANGULAR SPEED, ACCELERATION, DECELERATION, OR SHOCK; INDICATING PRESENCE, ABSENCE, OR DIRECTION, OF MOVEMENT
    • G01P3/00—Measuring linear or angular speed; Measuring differences of linear or angular speeds
    • G01P3/42—Devices characterised by the use of electric or magnetic means
    • G01P3/44—Devices characterised by the use of electric or magnetic means for measuring angular speed
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R33/00—Arrangements or instruments for measuring magnetic variables
    • G01R33/0052—Manufacturing aspects; Manufacturing of single devices, i.e. of semiconductor magnetic sensor chips
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/293—Organic, e.g. plastic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H01L23/4951—Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H01L23/49513—Lead-frames or other flat leads characterised by the die pad having bonding material between chip and die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H01L23/4952—Additional leads the additional leads being a bump or a wire
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49562—Geometry of the lead-frame for devices being provided for in H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3201—Structure
    • H01L2224/32012—Structure relative to the bonding area, e.g. bond pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/85455—Nickel (Ni) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85463—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/85464—Palladium (Pd) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/157—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2924/15738—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950 C and less than 1550 C
    • H01L2924/15747—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3512—Cracking
    • H01L2924/35121—Peeling or delaminating

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

本发明公开一种经封装的电子装置，其包括：封装、管芯(204)和第一接合线(212)。所述封装包括引线框架。所述引线框架包括彼此分离的第一导电引线框架元件(208)和第二导电引线框架元件(206)。所述管芯(204)包括第一接合垫。所述第一接合线(212)将所述第一接合垫电连接到所述第一导电引线框架元件(208)。所述管芯(204)以机械方式将所述第一引线框架元件(208)和第二引线框架元件(206)耦合在一起。

Description

电子装置和封装
技术领域
本发明涉及一种用于电子装置或组件的封装布置，且更具体地说涉及一种管芯和引线框架的布置。
背景技术
例如集成电路或传感器等电子装置常常包括电连接，借助所述电连接，此类组件可连接到较大系统。另外常常是以下情况：电子装置放置于封装中，封装保护所述装置且提供去往和来自所述装置的一组标准化电连接。
电子装置可呈管芯的形式，其可包括例如硅等半导体衬底。常规地，导电区(接合垫)在管芯的表面处暴露以便形成到管芯的电连接，且这些导电区可使用接合线依次连接到封装的电导体(即，连接到封装引线框架)。
封装引线框架可包括例如铜等金属。所述封装可另外包括例如塑料材料等聚合囊封材料。CTE(热膨胀系数)的失配因此可在装置的各种元件之间存在，所述各种元件包括管芯和封装的各种元件。
当经封装电子装置经受温度变化时，经封装装置的元件之间的差分膨胀可产生将结合垫连接到引线框架的接合线上的热引发的应力循环。此类应力可导致接合线的过早故障，从而导致装置的故障。
减小此类故障的发生率的封装布置是合乎需要的。
发明内容
根据第一方面，提供一种经封装电子装置，其包括：封装、管芯和第一接合线。所述封装包括引线框架。所述引线框架包括彼此分离的第一和第二导电引线框架元件。管芯包括第一接合垫。第一接合线将第一接合垫电连接到第一引线框架元件。管芯以机械方式将第一和第二引线框架元件耦合在一起。
通过管芯将第一和第二引线框架元件机械耦合在一起可大大减少第一接合线上的热引发的应变，从而产生总体装置的改进的可靠性。
所述管芯可另外包括第二接合垫。所述装置可另外包括第二接合线。所述第二接合线可将第二接合垫连接到第二引线框架元件。
所述管芯可通过粘合剂层耦合到第一和第二引线框架元件。
第一接合线与第一接合垫和/或第一引线框架元件之间的连接可包括楔形结合。
所述装置可另外包括囊封元件，该囊封元件完全囊封管芯、第一接合垫和第一接合线。囊封元件可部分囊封第一和第二引线框架元件，使得第一和第二引线框架元件从囊封元件伸出。
第一和第二引线框架元件可各自包括在大体上相同方向上远离第一管芯延伸的伸长主体。
第一引线框架元件可包括接近于管芯的第一端，以及远离管芯的第二端。管芯到第二端的第一距离可为管芯(或囊封元件)在第一距离的方向上的尺寸的至少五倍。
所述装置可另外包括耦合到第一和/或第二引线框架元件的另一管芯。
管芯可耦合到第二引线框架元件的第一表面，且另一组件可耦合到第二引线框架元件的第二相对表面。
另一囊封元件可提供在第一囊封元件与相应第一和第二引线框架元件的第二端之间。所述另一囊封元件可包围相应第一和第二引线框架元件的邻近部分。
所述装置可包括磁场传感器。所述装置可供在转速传感器中使用。
根据第二方面，提供一种转速传感器，其包括根据在前的任一项权利要求所述的装置。
根据第三方面，提供一种防抱死制动系统，该防抱死制动系统包括根据第二方面的速度传感器。
通过下文中所描述的实施例将清楚本发明的这些以及其它方面并且参考这些实施例阐明本发明的这些以及其它方面。
附图说明
将参考图式仅借助于实例描述实施例，在图式中
图1为经封装电子装置的等距视图，其中引线框架上具有聚合物囊封的管芯；
图2为图1的装置的平面图；
图3为根据一个实施例的经封装电子装置的等距视图，其中引线框架上具有聚合物囊封的管芯；
图4为图3的装置的平面图；
图5为图3的引线框架元件的第一端的细节视图，其包括管芯和相关联的线接合；
图6为根据一个实施例比较用于图1的布置中的线接合和用于图3的布置的应变水平的曲线；以及
图7为根据一个实施例的ABS(防抱死制动系统)速度传感器的示意图，其包括类似于图3中示出的装置的装置，用包覆模制的聚合材料囊封。
应注意，图式是用于图解说明且未必按比例绘制。为图式中清楚和便利起见，这些图式的部分的相对尺寸和比例已经在大小方面夸大或缩小。相同附图标记一般用于指代经修改且不同实施例中的对应或类似特征。
具体实施方式
图1和2示出装置100，该装置100包括管芯104、第一引线框架元件108、第二引线框架元件106、囊封元件130、另一囊封元件122、第一接合线112和第二接合线110。
管芯104可包括传感器，例如磁场传感器(其可为霍尔传感器、AMR传感器，或某一其它传感器)。管芯104可包括集成电路，且可包括用于传感器的读出电路。管芯104可包括硅衬底，或某一其它半导体材料的衬底。
在此布置中的管芯104由第二引线框架元件106支撑，第二引线框架元件106包括其第一端处的桨状区，管芯104可例如通过粘合剂层附接到所述桨状区。管芯104可附接到第二引线框架元件106的第一表面，且另一组件(未图示)可附接到第二引线框架元件106的第二相对表面。
管芯104包括第一和第二接合垫，其每一者用于形成到第一管芯104的电连接。第一接合线112将第一接合垫连接到第一引线框架元件108，且第二接合线110将第二接合垫连接到第二引线框架元件106。
囊封元件130为大体上立方体形状，具有远离第一引线框架元件108和第二引线框架元件106的平面朝内成楔形的侧壁。囊封元件130完全包围管芯104和第二引线框架元件106的第一端处的桨状区。第一接合线112和第二接合线110也被囊封元件130包围。囊封元件130可包括例如塑料材料等聚合材料，且可包覆模制在其所包围的组件上方。第一引线框架元件108和第二引线框架元件106两者从囊封元件130的相同侧壁伸出，且在指状伸长突出部中向外延伸。
第一引线框架元件108和第二引线框架元件106在图2中更清楚地示出。图1和2布置的布置中的第一引线框架元件108和第二引线框架元件106仅在其相应第一端处通过囊封元件130以机械方式耦合在一起。提供另一囊封元件122来以机械方式将第一引线框架元件108和第二引线框架元件106耦合在一起，距囊封元件130一段距离(此距离可大于相同方向上囊封元件130的跨度)。
第一引线框架元件108和第二引线框架元件106在大体上相同方向上远离另一囊封元件122并排延伸。第一引线框架元件108和第二引线框架元件106之间的距离可在若干步骤中随着距囊封元件130的距离的增加而增加。第一引线框架元件108和第二引线框架元件106可分别包括第二端。所述第二端可包括适于连接到插头或插口的电连接器。第一引线框架元件108和第二引线框架元件106可远离囊封元件130伸出第一距离(即，从囊封元件130的边缘到第二端)。所述第一距离可为与第一距离相同的方向上测得的囊封元件的尺寸的至少五倍(即，引线框架元件108、106从囊封元件130延伸相对较长距离)。
第一引线框架元件108和第二引线框架元件106可各自包括铜层，其具有涂层以防止腐蚀。所述涂层(例如，在引线框架元件的接合线附接区中)可包括镍，和/或镍和钯。
当经封装装置100经受温度循环时，装置的各种元件之间的差分膨胀可导致管芯104与第一引线框架元件108的第一端之间的距离的改变。这继而可导致第一接合线(其可在管芯104与第一引线框架元件108的第一端之间延伸)上的热引发的应变。此热引发的应变可随时间推移导致第一接合线112的故障，例如归因于疲劳。此类故障可往往在第一接合线112到第一引线框架元件108的附接点附近发生，所述位置可大致与最大反转应力的位置对应。这可限制装置100的使用寿命。
图3和4描绘根据一个实施例的装置200。装置200具有与图1和2的布置共同的若干特征。图3和4的装置200包括管芯204、第一引线框架元件208、第二引线框架元件206、囊封元件230、另一囊封元件222、第一接合线212和第二接合线210。装置200可包括图1和2的装置100中所见的所有元件。参看图1和图2描述的特征中的每一个特征可适用于图3和4的装置(具有被给予始于‘2’而非‘1’的参考标号的类似特征)。然而，在图3和4的装置200中，囊封元件230内的特征以不同方式布置。
在图3的装置200中，第一引线框架元件208和第二引线框架元件206的设计已经修改。如图5中更清楚地示出，第一接合线212将管芯204电连接到第一引线框架元件208的第一端。第二接合线210将管芯204连接到第二引线框架元件206。在一个实施例中，管芯204以机械方式将第一引线框架元件208和第二引线框架元件206的第一端耦合在一起。这减少或防止了管芯204与第一引线框架元件208的第一端之间的相对移动，从而大大减少第一接合线212上的热引发的应变的量。第一引线框架元件208和第二引线框架元件206中的每一者的第一端的设计已经更改以使管芯204能够跨越第二引线框架元件206的第一端处的桨状物与第一引线框架元件208的第一端之间的间隙。所述设计改变使得引线框架元件208、206和囊封元件230、222上的外部设计保持不变，使得实施例可提供用于图1的装置的更可靠的更换。管芯204可通过粘合剂层(未图示)附接到第一引线框架元件208和第二引线框架元件206两者。另一管芯(未图示)可包括在第一引线框架元件208或第二引线框架元件206上。
图6示出归因于用于以下各者的经封装装置的各种材料之间TCE的失配而在温度循环上产生的第一接合线112、212中的最大等效塑料应变的曲线：根据图1的装置(301)，以及根据图3中示出的实施例的装置(302)。结果301、302基于经封装装置的有限元件模拟，且清楚地示出针对根据一个实施例的装置由于温度循环引起的最大热引发的应变的显著缩减。最大等效塑料应变可在接合线与引线框架之间的结合处或附近发生。所述结合可为楔形结合(或球形结合)。
如图7中所示出，装置200可包括在包覆模制的外部封装401内从而形成经囊封装置400，所述经囊封装置400可包括用于收容电耦合到引线框架元件208、206的第二端的可移除连接器的连接器套筒(未图示)。
通过阅读本发明，技术人员将明白其它变化和修改。此类变化和修改可涉及等效和其它特征，所述等效和其它特征在电子装置封装的领域中已经为我们知晓且可用作本文已经描述的特征的替代或补充。
尽管所附权利要求书是针对特定特征组合，但应理解，本发明的公开内容的范围还包括本文中明确地或隐含地公开的任何新颖特征或任何新颖特征组合或其任何一般化形式，而不管其是否涉及与当前在任何权利要求中主张的相同的发明或其是否缓解与本发明所缓解的任一或全部技术问题相同的技术问题。
在单独实施例的上下文中描述的特征也可以组合地提供于单一实施例中。相反，为了简洁起见，在单一实施例的上下文中所描述的多种特征也可以单独地或以任何合适的子组合形式提供。申请人特此提醒，在审查本申请案或由此衍生的任何另外的申请案期间，可根据此类特征及/或此类特征的组合而制订新的权利要求。
为了完整起见，还指出，术语“包括”并不排除其它元件或步骤，术语“一”并不排除多个，并且权利要求书中的附图标记不应被解释为限制权利要求书的范围。

Claims (13)

1.一种经封装的电子装置，其特征在于，包括：
封装，具有引线框架，所述引线框架包括彼此分离的第一导电引线框架元件和第二导电引线框架元件；
管芯，包括第一接合垫；以及
第一接合线，将所述第一接合垫电连接到所述第一引线框架元件；
其中，所述管芯将所述第一引线框架元件和第二引线框架元件机械耦合在一起。
2.根据权利要求1所述的装置，其特征在于，所述管芯另外包括第二接合垫，并且所述装置包括将所述第二接合垫连接到所述第二引线框架元件的第二接合线。
3.根据在前的任一项权利要求所述的装置，其特征在于，所述管芯通过粘合剂层耦合到所述第一引线框架元件和第二引线框架元件。
4.根据在前的任一项权利要求所述的装置，其特征在于，所述第一接合线与所述第一接合垫和/或第一引线框架元件之间的连接包括楔形结合。
5.根据在前的任一项权利要求所述的装置，其特征在于，另外包括囊封元件，所述囊封元件完全囊封所述管芯、第一接合垫和第一接合线，并且部分囊封所述第一引线框架元件和第二引线框架元件，使得所述第一引线框架元件和第二引线框架元件从所述囊封元件伸出。
6.根据权利要求5所述的装置，其特征在于，所述第一引线框架元件和第二引线框架元件各自包括在大体上相同的方向上远离所述管芯延伸的伸长主体。
7.根据权利要求6所述的装置，其特征在于，所述第一引线框架元件包括接近于所述管芯的第一端和远离所述第一管芯的第二端，其中所述第一管芯到所述第二端的第一距离为所述第一距离的方向上所述管芯的尺寸的至少五倍。
8.根据权利要求5到7中任一权利要求所述的装置，其特征在于，另外包括另一管芯，所述另一管芯耦合到所述第一引线框架元件和/或第二引线框架元件。
9.根据在前的任一项权利要求所述的装置，其特征在于，所述管芯耦合到所述第二引线框架元件的第一表面，并且另一组件耦合到所述第二引线框架元件的第二相对表面。
10.根据权利要求5到9中任一权利要求所述的装置，其特征在于，另一囊封元件提供在所述第一囊封元件与所述相应第一引线框架元件和第二引线框架元件的所述第二端之间，所述另一囊封元件包围所述相应第一引线框架元件和第二引线框架元件的邻近部分。
11.根据在前的任一项权利要求所述的装置，其特征在于，所述装置包括磁场传感器。
12.一种转速传感器，其特征在于，包括根据在前的任一项权利要求所述的装置。
13.一种防抱死制动系统，其特征在于，包括根据权利要求11所述的速度传感器。
CN201610580181.9A 2015-07-31 2016-07-21 电子装置和封装 Pending CN106531713A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP15179394.0 2015-07-31
EP15179394.0A EP3125290A1 (en) 2015-07-31 2015-07-31 Electronic device

Publications (1)

Publication Number Publication Date
CN106531713A true CN106531713A (zh) 2017-03-22

Family

ID=53776426

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201610580181.9A Pending CN106531713A (zh) 2015-07-31 2016-07-21 电子装置和封装

Country Status (3)

Country Link
US (1) US20170033034A1 (zh)
EP (1) EP3125290A1 (zh)
CN (1) CN106531713A (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7293818B2 (ja) 2019-04-03 2023-06-20 株式会社プロテリアル センサ装置、センサ付きケーブル及び複合ケーブル
US11114239B2 (en) * 2019-11-20 2021-09-07 Nxp B.V. Electronic device, device package, and method of fabrication

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101211897A (zh) * 2006-12-28 2008-07-02 中芯国际集成电路制造(上海)有限公司 多芯片半导体封装结构及封装方法
US20130249027A1 (en) * 2012-03-20 2013-09-26 Allegro Microsystems, Inc. Integrated circuit package having a split lead frame
US20130249546A1 (en) * 2012-03-20 2013-09-26 Allegro Microsystems, Llc Integrated circuit package having a split lead frame
US20140320124A1 (en) * 2013-04-26 2014-10-30 Allegro Microsystems, Llc Integrated circuit package having a split lead frame and a magnet

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100902766B1 (ko) * 2002-09-27 2009-06-15 페어차일드코리아반도체 주식회사 절연성 세라믹 히트 싱크를 갖는 디스크리트 패키지
TWI280399B (en) * 2004-10-01 2007-05-01 Yamaha Corp Physical amount sensor and lead frame used therein

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101211897A (zh) * 2006-12-28 2008-07-02 中芯国际集成电路制造(上海)有限公司 多芯片半导体封装结构及封装方法
US20130249027A1 (en) * 2012-03-20 2013-09-26 Allegro Microsystems, Inc. Integrated circuit package having a split lead frame
US20130249546A1 (en) * 2012-03-20 2013-09-26 Allegro Microsystems, Llc Integrated circuit package having a split lead frame
US20140320124A1 (en) * 2013-04-26 2014-10-30 Allegro Microsystems, Llc Integrated circuit package having a split lead frame and a magnet

Also Published As

Publication number Publication date
EP3125290A1 (en) 2017-02-01
US20170033034A1 (en) 2017-02-02

Similar Documents

Publication Publication Date Title
CN106461705B (zh) 电流传感器
US10718794B2 (en) Current sensor with power calculation
CN106298757B (zh) 具有集成式磁场传感器的功率封装体
JP5965924B2 (ja) プッシュプル型ブリッジ磁気抵抗センサ
CN105452880B (zh) 电流传感器
CN101253399A (zh) 具有基片和壳体的传感器装置及制造传感器装置的方法
US9231118B2 (en) Chip package with isolated pin, isolated pad or isolated chip carrier and method of making the same
US10145904B2 (en) Multi-die integrated circuit device with overvoltage protection
TW200924147A (en) Stackable integrated circuit package
US7745916B2 (en) Module comprising polymer-containing electrical connecting element
US8264074B2 (en) Device for use as dual-sided sensor package
CN108226627A (zh) 电流传感器以及制造电流传感器的方法
US9000761B2 (en) Hall-effect sensor isolator
CN106531713A (zh) 电子装置和封装
CN110364512A (zh) 用以防止短路事件的半导体功率模块
CN104282635B (zh) 具有互锁连接的半导体模块
CN209016054U (zh) 带引脚封装的功率模块和无引脚封装的功率模块
CN208636360U (zh) 一种电流传感器封装结构
CN103715161A (zh) 芯片装置，芯片封装和用于制作芯片装置的方法
CN206293435U (zh) 半导体器件与半导体封装件
CN109148397A (zh) 半导体装置封装
TWI237528B (en) Circuit device and method for manufacturing same
CN104779023B (zh) 一种电路保护用平板式半导体元器件
CN109449150A (zh) 带引脚封装、无引脚封装的功率模块及其对应加工方法
CN217641313U (zh) 单芯片封装结构

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
WD01 Invention patent application deemed withdrawn after publication

Application publication date: 20170322

WD01 Invention patent application deemed withdrawn after publication