CN103715161A - 芯片装置，芯片封装和用于制作芯片装置的方法 - Google Patents

芯片装置，芯片封装和用于制作芯片装置的方法 Download PDF

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CN103715161A
CN103715161A CN201310455546.1A CN201310455546A CN103715161A CN 103715161 A CN103715161 A CN 103715161A CN 201310455546 A CN201310455546 A CN 201310455546A CN 103715161 A CN103715161 A CN 103715161A
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chip
terminal
conducting element
wire
voltage supply
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CN103715161B (zh
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张翠嶶
J.赫格劳尔
G.内鲍尔
R.奥特伦巴
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Infineon Technologies AG
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Infineon Technologies AG
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Abstract

芯片装置，芯片封装和用于制作芯片装置的方法。提供芯片封装。该芯片封装包括芯片载体，电压供应引线，感测端子和被设置芯片载体上的芯片。芯片包括第一端子和第二端子，其中第一端子电接触芯片载体。芯片封装也包括形成在第二端子上的导电元件，导电元件将第二端子电耦合到电压供应引线和感测端子。

Description

芯片装置,芯片封装和用于制作芯片装置的方法
技术领域
各种实施例总体上涉及芯片装置，芯片封装和用于制作芯片装置的方法。
背景技术
芯片接触区域，例如源极和/或漏极接触每个通常被提供有电压直通连接元件，例如导电线，导电引线或者线夹。此外，源极感测引线可以被连接到源极接触以测量和/或监测源极接触的电势。源极感测引线可以通过另外的再分配元件连接到源极接触，例如通过导电线。导电线可以例如通过线结合被连接到源极接触。这些多个接触机构可以导致另外的封装成本，其具体地可以被归因于对额外源极感测引线的需要。
发明内容
各种实施例提供芯片封装，其包括：芯片载体；电压供应引线；感测端子；设置在芯片载体上的芯片，该芯片包括第一端子和第二端子，其中第一端子电接触芯片载体；形成在第二端子上的导电元件，该导电元件将第二端子电耦合到电压供应引线和感测端子。
附图说明
在附图中，贯穿不同视图，相似的参考字符通常指的是相同的部分。附图不一定按比例绘制，而是将重点通常放在说明本发明的原理上。在下面的描述中，参照下面的附图来描述本发明的各种实施例，其中：
图1示出根据各种实施例的用于制作芯片装置的方法；
图2示出根据各种实施例的用于制作芯片装置的方法的示例性视图；
图3A示出芯片装置的顶视图图示；
图3B示出芯片装置的截面图示；
图3C示出根据各种实施例的芯片装置的顶视图图示；
图3D示出根据各种实施例的芯片装置的截面图示；
图4示出根据各种实施例的芯片装置的顶视图；
图5示出根据各种实施例的芯片装置的顶视图；
图6示出根据各种实施例的芯片装置的顶视图；
图7示出根据各种实施例的芯片装置的顶视图；
图8示出根据各种实施例的芯片装置的顶视图。
具体实施方式
下面详细的描述参照附图，所述附图作为示例示出其中本发明可被实施的具体细节和实施例。
本文使用词“示例性的”来意指“用作实例，例子，或者示例”等。本文描述为“示例性的”的任何实施例或者设计不一定被解释为比其它实施例或者设计优选或者有利。
 词“上面”在本文被用来描述在面或者表面“上面”形成特征，例如层，并且可以被用来表示该特征，例如该层，可以“直接”形成在暗指的面或者表面“上”，例如与暗指的面或者表面直接接触。词“上面”在本文也可以被用来描述在面或者表面“上面”形成特征，例如层，并且可以被用来表示该特征，例如该层，可以“间接”形成在暗指的面或者表面“上”，其中在暗指的面或者表面和被形成的层之间布置一个或者多个另外的层。
各种实施例提供可以使用接触线夹用于源极感测的芯片装置，同时避免使用另外的线结合（WB）用于源极感测。
图1示出根据实施例的用于制作芯片装置的方法100。方法100可以包括：
在芯片载体上设置包括第一端子和第二端子的芯片，其中该第一端子电接触芯片载体（在110中）；并且
在第二端子上形成导电元件，该导电元件将第二端子电耦合到电压供应引线和感测端子（在120中）。
图2示出根据实施例的用于制作芯片装置的方法200的示例性视图210至260。方法200可以包括已经关于方法100描述的工艺中的一个或多个或全部。
如在视图210中所示，方法200可以包括提供芯片载体202。芯片载体202可以包括引线框的至少一部分。例如，芯片载体可以包括来自下面材料组的至少一种材料，元素或者合金，该组由下述构成：铜，铝，银，锡，金，钯，锌，镍，铁。芯片载体202可以包括至少一个基本平面状表面204。此外，可以提供一个或者多个导电引线。如作为实例示出的，为了说明的目的，一个或者多个导电引线可以包括一个或者多个电压供应引线206，例如源极引线，一个或者多个另外的电压供应引线208，例如漏极引线和感测端子212。该一个或者多个引线可以包括引线框材料。作为实例，该一个或者多个引线可以是导电腿或者导电延伸部，其可以是或者可以已经是引线框的一部分。一个或者多个引线可以包括来自下面材料组的至少一种材料，元素或者合金，该组由下述构成：铜，铝，银，锡，金，钯，锌，镍，铁。
如在视图220中示出的，导电接合材料214可以被沉积在芯片载体202的平面状表面204上，用于管芯附着。导电接合材料214可以包括粘合剂和焊接材料中的至少一个。作为实例，导电接合材料214可以包括来自下面材料组中的至少一种，该组由下述构成：焊料，软焊料，扩散焊料，膏剂，纳米膏剂，粘合剂，导电粘合剂。导电接合材料214可以被散布或者分散在芯片载体202的平面状表面204上，为放置管芯或者芯片作准备。
如在视图230中示出的，芯片216可以被设置在芯片载体202上。芯片216可以包括第一端子218，例如在芯片第一面222上的第一源极/漏极接触218，其可以是芯片216的面朝下的面。芯片216可以被焊接附着到芯片载体202。芯片216可以被布置在芯片载体202上，其中第一端子218可以面对芯片载体202，并且第一端子218可以电接触芯片载体202。第一源极/漏极接触218可以通过导电接合材料214被直接电耦合到芯片载体202。更多的电压供应引线208可以被物理和电接合到芯片载体202。更多的电压供应引线208可以被配置为供应电压到第一端子218。芯片216也可以包括第二端子224，例如在第二芯片面226上（即在芯片216的面向上的面上）形成的第二源极/漏极接触224。第二芯片面226可以面向基本上与第一芯片面222相反的方向。
芯片216可以包括垂直器件，因为，例如，漏极接触，诸如第一源极/漏极接触218可以被形成在芯片第一面222上，并且源极接触，诸如第二源极/漏极接触224可以被形成在芯片第二面226上。芯片216可以支持电流流动，其可以垂直流过芯片216，例如在源极接触224和漏极接触218之间。芯片216可以包括功率半导体器件。芯片216可以包括来自由下述构成的功率半导体器件组中的至少一个功率半导体器件：功率晶体管，功率MOS晶体管，功率双极晶体管，功率场效应晶体管，功率绝缘栅双极晶体管，晶闸管，MOS控制晶闸管，硅控整流器和功率肖特基二极管。
如在视图240中示出的，可以在第二芯片面226上沉积另外的导电接合材料228。另外的导电接合材料228可以与上面已经描述的导电接合材料214相似。可以在第二端子224上，例如在第二源极/漏极接触224上沉积另外的导电接合材料228，例如焊膏层。也可以在电压供应引线206和感测端子212上沉积另外的导电接合材料228。
如在视图250中示出的，可以在第二端子224上形成导电元件232。导电元件232可以包括接触线夹。该接触线夹可以包括至少一个基本平面状表面234，该表面可以被用来将线夹216固定到芯片载体202上的适当位置。可以由引线框材料形成导电元件232，例如接触线夹。导电元件232可以包括来自下面材料组中的至少一种材料，元素或者合金，该组由下述构成：铜，铝，银，锡，金，钯，锌，镍，铁。
基本平面状表面234可以覆盖第二端子224中的至少一部分。基本平面状表面234可以具有大于第二端子234的表面面积的表面面积，例如大于第二端子224的表面面积的约30%，例如大于第二端子234的表面面积的约50%，例如大于第二端子234的表面面积的约70%，例如大于第二端子234的表面面积的约90%。可以在大于第二端子224的表面面积的约30%的上面形成导电元件232，例如在大于第二端子234的表面面积的约50%的上面形成导电元件232，例如在大于第二端子234的表面面积的约70%的上面形成导电元件232，例如在大于第二端子234的表面面积的约90%的上面形成导电元件232，例如在第二端子234的表面面积的约100%的上面形成导电元件232。导电元件232的基本平面状表面234可以通过设置在第二端子224上的另外的导电接合材料228被电耦合到第二端子224。导电元件232可以具有从大约0.1mm2变动到大约10mm2的表面面积，例如，从大约0.1mm2变动到大约1mm2。
也可以在电压供应引线206和感测端子212上形成导电元件232。导电元件232可以被物理和电连接到电压供应引线206。导电元件232可以利用焊接材料，例如另外的导电接合材料228，被电耦合到电压供应引线206。导电元件232可以通过焊接材料例如另外的导电接合材料228被焊接到电压供应206引线。导电元件232可以被物理和电连接到感测端子212。导电元件232可以通过焊接材料例如另外的导电接合材料228被焊接到感测端子212。因此导电元件232可以将第二端子224电耦合到电压供应引线206和感测端子212。
如在视图260中示出的，可以在导电元件232上沉积密封材料236，并且其中密封材料236可以围绕芯片216和一个或多个引线。可以在第二芯片面226上和在芯片载体202的平面状表面204上沉积密封材料236。密封材料也可以至少部分地围绕一个或多个引线，包括电压供应引线206，一个或多个另外的电压供应引线208和感测端子212。密封材料236可以至少部分地围绕芯片216，从而使芯片216的各部分与其环境电绝缘。密封材料236可以包括模塑料（mold compound），通常用于芯片封装。例如，密封材料236可以包括填充的或未填充的环氧树脂，预浸渍的复合纤维，增强纤维，层压材料，模具材料，热固性材料，热塑性材料，填充粒子，纤维增强层压材料，纤维增强聚合物层压材料和具有填充粒子的纤维增强聚合物层压材料中的至少一种。
根据各种实施例的芯片封装238在视图250中被示出。芯片封装238可以包括：芯片载体202，电压供应引线206和感测端子212。芯片封装238可以包括芯片216，其可被设置在芯片载体202上。芯片216可以包括第一端子218和第二端子224。第一端子218可以电接触芯片载体202。芯片封装238可以包括可被形成在第二端子224上的导电元件232。因此导电元件232可以将第二端子224电耦合到电压供应引线206和感测端子212。根据各种实施例，芯片封装238也可以包括如在视图260中示出的密封材料236。
图3A在视图310中示出芯片装置342的顶视图图示。图3B在视图320中示出芯片装置342的截面图示。芯片装置342可以包括多芯片器件。芯片装置342可以包括芯片216和芯片344。芯片216和芯片344可以设置在芯片载体202上，并且第一端子218（面朝下并因此未被示出）可电接触芯片载体202。导电元件332可以被形成在芯片216中的至少一部分上，例如导电元件332可以被形成在第二端子224上。因为芯片装置342可以包括多芯片装置，芯片216和芯片344例如可以被布置成半桥电路装置。即，可以在第二端子224例如芯片216的源极接触上以及在芯片344的另外的端子346上形成导电元件332。另外的端子346可以包括例如漏极接触。导电元件332可以将第二端子224和另外的端子346电耦合到电压供应引线206。电压供应引线206可以供应电压到第二端子224和另外的端子346两者。
通常，感测端子212可以通常通过线结合348或者带状结合348被电耦合到第二端子224的一部分。线结合/带状结合348可能导致另外的加工成本，并且此外，可能占用在第二端子224上的空间，否则其可以被导电元件332覆盖。芯片装置342可以包括标准功率芯片封装例如TO220-3芯片封装的一部分。
图3C在视图330中示出根据实施例的芯片装置338的顶视图图示。图3D在视图340中示出根据实施例的芯片装置338的截面图示。芯片装置338可以包括芯片装置342的特性和特征，然而可以去除线结合/带状结合348。导电元件332可以被可将第二端子224和另外的端子346电耦合到电压供应引线206以及感测端子212的导电元件232替代。此外，与导电元件332相比，导电元件232可以被放大，并且在导电元件232和第二端子224之间的接触区域可以被增加，因为导电元件232甚至可以被形成在不再被线结合/带状结合348占用的空间上。用于供应电压，例如用于供应源极电压的增加的面积可以改善电器件的性能。此外，在接触区域和导电元件232的尺寸方面的增加可能导致面226的改进的冷却，即更好的顶面冷却。
根据各种实施例，芯片装置338可以包括至少一个另外的引线356和至少一个线结合/带状结合354；其中线结合/带状结合354可以将另外的引线356电耦合到芯片216。在实施例中，如在图3C中示出的，芯片216还可以包括第三端子352。第三端子352可以被设置或者形成在第二芯片面226上，例如在与第二端子352相同的芯片216的面上。在第二端子224可以包括源极接触的同时，第三端子352可以包括栅极接触。线结合/带状结合354可以将至少一个另外的引线356电耦合到第三端子352。另外的引线356可以将电压供应到第三端子352，即栅极接触。
图4和5示出根据各种实施例的芯片装置的顶视图410和510。
在顶视图410中的芯片装置438示出芯片216。芯片216可以包括设置在芯片216的面222上的底部接触218，例如第一端子，例如漏极接触。面222可以是面朝下的面并且因此底部接触218和面222可以是从顶视图410不可见的。芯片装置438可以包括电压供应引线206，例如源极引线。芯片装置438可以包括感测端子212，例如源极感测引线。芯片装置438可以包括另外的电压供应引线208，例如漏极引线。芯片装置438可以包括另外的引线356，例如栅极引线。芯片216可以被形成在芯片载体202上。即，底部接触218可以在芯片载体202上被面朝下布置。底部接触218，即漏极接触可以被电连接或者接合到芯片载体202。另外的电压供应引线208，例如漏极引线可以将电压提供到芯片载体202，并因此提供到底部接触218。导电接触224可以被形成在芯片216的面226上。导电元件232可以被形成在导电接触224上。导电元件232可以将导电接触224电连接到电压供应引线206，例如连接到一个或多个源极引线。换句话说，导电元件232可以将电压提供到导电接触224。在由电压供应引线206对导电接触224和由另外的电压供应引线208对底部接触218提供的电压的差异可导致在导电接触224和底部接触218之间的电势差，该电势差可驱动在导电接触224和底部接触218之间的电流，即在面226和面222之间的垂直电流。
导电元件232也可以将感测端子212电耦合到导电接触224。导电元件232可以利用焊膏，例如另外的导电接合材料228被接合到导电接触224。
芯片216还可以包括第三端子352，例如形成在第二芯片面226上的栅极接触。至少一个线结合/带状结合354可以将另外的引线356，例如栅极引线电耦合到第三端子352，其中另外的引线356可以将电压供应到第三端子352，即栅极接触。
图5在顶视图510中示出芯片装置538。芯片装置538可以包括已经关于芯片装置438描述的特征中的一个或多个或全部。根据一些实施例，芯片装置538可以包括另外的端子558，562。如在顶视图510中示出的，第一个另外的端子558可以包括电流感测端子，并且第二个另外的端子562可以包括温度感测端子。另外的端子558，562每个可以通过线结合/带状结合564，566被分别电耦合到芯片216，例如电耦合到芯片216的导电接触224。第一个另外的端子558可以连接到被配置为测量导电接触224的温度的电路。第二个另外的端子562可以连接到被配置为在导电接触224处测量电流的电路。
根据各种实施例，本文已经关于芯片装置338，438，538和芯片封装238描述的感测端子212可以包括电压感测端子。感测端子212可以形成电压感测电路568的至少一部分。电压感测电路568可以被配置为通过感测端子212测量第二端子224，即导电接触224的电压或者电势。电压感测电路568可以被进一步配置为确定由另外的引线356提供到第三端子352，即栅极端子352的电压。被确定为由另外的引线356提供到第三端子352的电压可以取决于由感测端子212，电压感测电路568和导电元件232测量的第二端子的电势。
如在图6的顶视图610中示出的，根据各种其它实施例，感测端子212可以形成电流感测电路668的至少一部分。电流感测电路668可以被配置为通过感测端子212测量在第二端子224，即导电接触224中的电流。在这个实施例中，另外的端子558可以包括电压感测端子，其可以被连接到电压感测电路（未示出）。
如在图7的顶视图710中示出的，根据各种其它实施例，导电接触224可以将感测端子212电耦合到电压感测电路568，并且将另外的感测端子558电耦合到另外的感测电路，即电流感测电路668。感测端子212可以形成被配置为测量第二端子224的电压的电压感测电路568的至少一部分，并且另外的感测端子558可以形成被配置为测量第二端子212的电流的电流感测电路668的至少一部分。
图8在顶视图810中示出根据实施例的芯片装置838。芯片装置838可以包括多个芯片，其可以被布置成例如具有栅极集成电路的DrMOS功率半桥。芯片装置838可以包括可被布置成如关于图3A至3D描述的半桥结构的芯片216和344。芯片装置838也可以包括栅极驱动器集成电路572。
芯片装置838可以包括芯片载体202。芯片216可以包括电接触芯片载体202的面朝下的第一端子218（未示出），和面朝上的第二端子224。
可以在芯片216的第二端子224上和芯片344的另外的端子346上形成导电元件232。导电元件232可以将第二端子224和另外的端子346电耦合到电压供应引线206，其中电压供应引线206可以将电压供应到第二端子224和另外的端子346两者。导电元件232也可以将第二端子224和另外的端子346两者电耦合到感测端子212。感测端子212可以形成电压感测电路568的至少一部分。电压感测电路568可以形成栅极驱动器电路572的一部分。栅极驱动器电路572可以通过线结合/带状结合354被电耦合到第三端子352，即栅极接触。由线结合/带状结合354提供到第三端子352的电压可取决于由电压感测电路568测量的第二端子的电势。
各种实施例提供包括使用接触线夹进行感测的芯片装置和芯片封装。根据各种实施例的各种芯片装置和芯片封装可以包括用于功率器件的芯片装置和芯片封装。各种实施例可以包括用于功率的芯片装置和芯片封装，其中基于混合逻辑分配，例如使用线结合和/或带状结合和/或线夹来进行感测。各种实施例可以被实施而没有明显的额外的封装成本和人工。
各种实施例提供一种芯片装置，其包括：芯片载体；电压供应引线；感测端子；设置在芯片载体上的芯片，该芯片包括第一端子和第二端子，其中第一端子电接触芯片载体；和在第二端子上形成的导电元件，该导电元件将电压供应引线电耦合到第二端子；其中导电元件进一步将第二端子电耦合到感测端子。
根据实施例，芯片载体包括引线框的至少一部分。
根据实施例，电压供应引线包括引线框的至少一部分。
根据实施例，芯片载体包括来自下面材料组中的至少一种材料，元素或者合金，该组由下述构成：铜，铝，银，锡，金，钯，锌，镍，铁。
根据实施例，芯片包括功率半导体器件。
根据实施例，第一端子包括形成在第一芯片面上的第一源极/漏极接触。
根据实施例，第一源极/漏极接触通过导电接合材料电耦合到芯片载体。
根据实施例，导电接合材料包括粘合剂和焊接材料中的至少一个。
根据实施例，导电元件包括接触线夹。
根据实施例，导电元件包括来自下面材料组中的至少一种材料，元素或者合金，该组由下述构成：铜，铝，银，锡，金，钯，锌，镍，铁。
根据实施例，导电元件包括至少一种基本平面状表面；并且该至少一个基本平面状表面覆盖第二端子的至少一部分。
根据实施例，该至少一个基本平面状表面通过设置在第二端子上的焊膏层被电耦合到第二端子。
根据实施例，第二端子包括在第二芯片面上形成的第二源极/漏极接触，该第二芯片面面向与第一芯片面相反的方向。
根据实施例，第二端子具有表面面积；并且在大于第二端子的表面面积的大约30%的上面形成导电元件。
根据实施例，导电元件利用焊接材料被电耦合到电压供应引线。
根据实施例，导电元件被物理和电连接到电压供应引线。
根据实施例，导电元件通过焊接材料被焊接到电压供应引线。
根据实施例，导电元件被物理和电连接到感测端子。
根据实施例，导电元件通过焊接材料被焊接到感测端子。
根据实施例，感测端子形成被配置为测量第二端子的电压的电压感测电路的至少一部分。
根据实施例，感测端子形成被配置为测量第二端子的电流的电流感测电路的至少一部分。
根据实施例，芯片装置还可以包括另外的感测端子，其中导电元件进一步将第二端子电耦合到该另外的感测端子；其中感测端子形成被配置为测量第二端子的电压的电压感测电路的至少一部分，并且其中该另外的感测端子形成被配置为测量第二端子的电流的电流感测电路的至少一部分。
根据实施例，该芯片装置进一步包括至少一个另外的引线；和至少一个线结合；其中该至少一个线结合将该至少一个另外的引线电耦合到芯片。
根据实施例，芯片进一步包括第三端子；并且该至少一个线结合将该至少一个另外的引线电耦合到第二端子或者第三端子。
各种实施例提供一种芯片装置，其包括：芯片，其包括设置在芯片的面上的导电接触；电压供应引线；感测端子；形成在导电接触上的导电元件，其中导电元件将导电接触电连接到电压供应引线和感测端子。
各种实施例提供一种芯片封装，其包括：芯片载体；电压供应引线；感测端子；设置在芯片载体上的芯片，该芯片包括第一端子和第二端子，其中第一端子电接触芯片载体；形成在第二端子上的导电元件，导电元件将第二端子电耦合到电压供应引线和感测端子。
各种实施例提供用于制作芯片装置的方法，该方法包括：在芯片载体上设置包括第一端子和第二端子的芯片，其中第一端子电接触芯片载体；并且在第二端子上形成导电元件，导电元件将第二端子电耦合到电压供应引线和感测端子。
虽然已经参照特定实施例具体示出和描述了本发明，但是本领域技术人员应该理解在不脱离如由所附权利要求限定的本发明的精神和范围的情况下，可以在其中做出各种形式和细节上的变化。本发明的范围因而由所附权利要求表明，并且因此在权利要求的等同物的含义和范围内的所有改变旨在被包含。

Claims (27)

1.一种芯片装置，包括：
芯片载体；
电压供应引线；
感测端子；
设置在所述芯片载体上的芯片，所述芯片包括第一端子和第二端子，其中所述第一端子电接触所述芯片载体；和
在所述第二端子上形成的导电元件，所述导电元件将所述电压供应引线电耦合到所述第二端子；
其中所述导电元件进一步将所述第二端子电耦合到所述感测端子。
2.根据权利要求1的芯片装置，其中所述芯片载体包括引线框的至少一部分。
3.根据权利要求1的芯片装置，其中电压供应引线包括引线框的至少一部分。
4.根据权利要求1的芯片装置，其中所述芯片载体包括来自下面材料组中的至少一种材料，元素或者合金，该组由下述构成：铜，铝，银，锡，金，钯，锌，镍，铁。
5.根据权利要求1的芯片装置，其中所述芯片包括功率半导体器件。
6.根据权利要求1的芯片装置，其中所述第一端子包括形成在第一芯片面上的第一源极/漏极接触。
7.根据权利要求1的芯片装置，其中所述第一源极/漏极接触通过导电接合材料电耦合到所述芯片载体。
8.根据权利要求1的芯片装置，其中所述导电接合材料包括粘合剂和焊接材料中的至少一个。
9.根据权利要求1的芯片装置，其中所述导电元件包括接触线夹。
10.根据权利要求1的芯片装置，其中所述导电元件包括来自下面材料组中的至少一种材料，元素或者合金，该组由下述构成：铜，铝，银，锡，金，钯，锌，镍，铁。
11.根据权利要求1的芯片装置，其中所述导电元件包括至少一种基本平面状表面；
其中所述至少一个基本平面状表面覆盖所述第二端子的至少一部分。
12.根据权利要求11的芯片装置，其中所述至少一个基本平面状表面通过设置在所述第二端子上的焊膏层被电耦合到所述第二端子。
13.根据权利要求1的芯片装置，其中所述第二端子包括在第二芯片面上形成的第二源极/漏极接触，所述第二芯片面面向与所述第一芯片面相反的方向。
14.根据权利要求1的芯片装置，
其中所述第二端子具有表面面积；并且
其中在大于所述第二端子的表面面积的大约30%的上面形成所述导电元件。
15.根据权利要求1的芯片装置，其中所述导电元件利用焊接材料被电耦合到所述电压供应引线。
16.根据权利要求1的芯片装置，其中所述导电元件被物理和电连接到电压供应引线。
17.根据权利要求1的芯片装置，其中所述导电元件通过焊接材料被焊接到电压供应引线。
18.根据权利要求1的芯片装置，其中所述导电元件被物理和电连接到所述感测端子。
19.根据权利要求1的芯片装置，其中所述导电元件通过焊接材料被焊接到所述感测端子。
20.根据权利要求1的芯片装置，其中所述感测端子形成被配置为测量所述第二端子的电压的电压感测电路的至少一部分。
21.根据权利要求1的芯片装置，其中所述感测端子形成被配置为测量所述第二端子的电流的电流感测电路的至少一部分。
22.根据权利要求1的芯片装置，进一步包括：
另外的感测端子，
其中所述导电元件进一步将所述第二端子电耦合到所述另外的感测端子；
其中所述感测端子形成被配置为测量所述第二端子的电压的电压感测电路的至少一部分，并且
其中所述另外的感测端子形成被配置为测量所述第二端子的电流的电流感测电路的至少一部分。
23.根据权利要求1的芯片装置，进一步包括：
至少一个另外的引线；和
至少一个线结合；
其中所述至少一个线结合将所述至少一个另外的引线电耦合到所述芯片。
24.根据权利要求23的芯片装置，
其中所述芯片进一步包括第三端子；并且
其中所述至少一个线结合将所述至少一个另外的引线电耦合到所述第二端子或者所述第三端子。
25.一种芯片装置，包括：
芯片，其包括设置在所述芯片的面上的导电接触；
电压供应引线；
感测端子；
形成在导电接触上的导电元件，其中所述导电元件将所述导电接触电连接到所述电压供应引线和所述感测端子。
26.一种芯片封装，包括：
芯片载体；
电压供应引线；
感测端子；
设置在所述芯片载体上的芯片，所述芯片包括第一端子和第二端子，其中所述第一端子电接触所述芯片载体；
形成在所述第二端子上的导电元件，所述导电元件将所述第二端子电耦合到所述电压供应引线和所述感测端子。
27.一种用于制作芯片装置的方法，所述方法包括：
在芯片载体上设置包括第一端子和第二端子的芯片，其中所述第一端子电接触所述芯片载体；并且
在所述第二端子上形成导电元件，所述导电元件将所述第二端子电耦合到电压供应引线和感测端子。
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