CN104681517A - 一种适合于led照明应用的多芯片qfn封装 - Google Patents

一种适合于led照明应用的多芯片qfn封装 Download PDF

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Publication number
CN104681517A
CN104681517A CN201310650663.3A CN201310650663A CN104681517A CN 104681517 A CN104681517 A CN 104681517A CN 201310650663 A CN201310650663 A CN 201310650663A CN 104681517 A CN104681517 A CN 104681517A
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chip
qfn
encapsulating structure
dao
package structure
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陆宇
蒋德军
程玉华
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Shanghai Research Institute of Microelectronics of Peking University
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Shanghai Research Institute of Microelectronics of Peking University
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Led Device Packages (AREA)

Abstract

本发明公开了用于大功率道路照明的一种多芯片QFN(方形扁平无引脚封装，Quad Flat No Lead)封装结构，包括了占用系统面积较大的芯片子模块：PWM(脉冲宽度调制，Pulse Width Modulation)控制器，功率MOS(金氧半场效晶体管，Metal Oxide Semiconductor)管，基岛，围绕所述基岛布置的多个焊盘，所述封装结构的封装空间内填充的绝缘材质。其中，所述不同芯片设置在基岛上，至少一个所述焊盘与所述基岛连通，其余焊盘通过金线与所述芯片连接。本发明公开的多芯片QFN封装结构，通过加入电连接芯片，为一颗或多颗芯片封装在一个QFN里提供了可行性，减少了封装成本，从而大大提高了系统的集成度和可靠性。

Description

一种适合于LED照明应用的多芯片QFN封装
技术领域
本发明涉及半导体器件的封装技术领域，尤其涉及一种多芯片QFN封装结构。
背景技术
随着LED照明普及到百姓家庭中，对于LED的便携性要求越来越重视，本发明的QFN封装结构能够极大的减小LED照明系统的体积。
随着产品的越做越小越精致，芯片产生的热量如何散发出去就变为一个不得不考虑的问题。现在的技术中，虽然可以通过提升制程能力来降低电压等方式来减小发热量，但是仍然不能避免发热密度增加的趋势。散热问题不解决，会使得芯片过热而影响到产品的可靠性，严重地会缩短产品寿命甚至造成产品损害。
此外，实现各个功能的芯片需要封装，现有技术中，QFN封装结构是一种方形扁平无引脚的半导体芯片封装结构。由于QFN封装不像传统的SOIC（小外形集成电路封装，Small Outline Integrated Circuit Package）与TSOP(薄型小尺寸封装，Thin Small Outline Package)封装那样具有鸥翼状引线，内部引脚与焊盘之间的导电路径短，自感系数以及封装体内布线电阻很低，所以它能提供卓越的电性能。
在封装形式固定的情况下，为使得产品散热满足要求，产品设计时只能靠牺牲性能来实现，以现在需求很大的快速充电为例，300mA的充电电流，功耗接近1.5W，如果电流再大，芯片发热量增加。
发明内容
本发明的目的是针对LED照明提出的特定封装解决方案，用以实现一颗比较复杂的芯片采用一个QFN封装。
本发明提供了一种多芯片QFN封装结构，用以提高集成度，并且解决芯片发热量较大的问题；
QFN封装管壳；
电连接芯片，用于与所述QFN封装管壳以及所述三个芯片进行点连接。
本发明所述多芯片QFN封装结构还包括金属连接线，用于所述电连接芯片的压焊盘相连接，再通过金属连接线与另一所述的几个芯片的压焊盘相连接。
进一步优选地，所述PWM控制器的芯片的压焊盘通过金属连接线与所述功率MOS，肖特基二极管和电连接芯片的一个压焊盘相连接，再通过金属连接线与所述QFN封装管壳的电极触点相连接。
进一步优选地，所述带有PWM控制器的芯片的压焊盘通过金属连接线与所述电连接芯片的一个压焊盘相连接，再通过金属连接线与另一所述功率MOS和肖特基二极管的芯片的压焊盘相连接，并且所述带有PWM控制器的芯片的另一压焊盘通过金属连接线与所述电连接芯片的另一压焊盘相连接，再通过金属连接线与QFN封装管壳的电极触点相连接。
本发明通过在QFN封装结构中增加一颗电连接芯片，实现了将一颗或多颗芯片封装在QFN管壳内，从而解决了由于受到QFN封装设计规则的限制，如封装内部短引线，引线不能交叉等而导致很多复杂芯片在需要进行多芯片封装时无法采用QFN封装的问题。
附图说明
图1是本发明实施例提供的QFN封装结构的俯视图；
图2是本发明实施例提供的QFN封装结构的俯视图；
图3为图2中沿A-A直线的剖视图；
图4为图2中沿B-B直线的剖视图。
具体实施方式
为使本发明的目的，技术方案和优点更加清楚，下面结合附图对本发明具体实施例作进一步的详细描述。
下述实施例描述的为一种多芯片QFN封装结构。
图1为本发明实施例一中QFN封装结构的俯视示意图；图2为QFN管壳示意图；图3为die10示意图；图4为die20示意图。
如图1所示，QFN封装结构具体包括多芯片die，QFN管壳，以及各个芯片的压焊盘之间以及QFN管壳的电极触点与各个芯片压焊盘之间的连接线。
在现有技术中，因为受限于QFN封装工艺的设计规则，金属连接线的长度不能超过一定的值，因而如果不同芯片的die间进行引线键合可能会出现交叉等问题。若想实现连接起来的电路功能，必须通过对这些芯片进行单独封装，再进行外部点连接才能实现。

Claims (6)

1.一种多芯片QFN封装结构，其特征在于包括，至少一颗PWM控制器的芯片，用于实现封装器件的控制LED照明功能；QFN封装管壳；基岛，所述芯片设置在所述基岛上；围绕所述基岛布置的多个焊盘；所述封装结构的封装空间内填充的绝缘材质；其特征在于，至少一个所述焊盘与所述基岛连通，其余焊盘通过金线与所述芯片连接。
2.如权利要求1所述的多芯片QFN封装结构，其特征在于，与基岛所在的一面相对的所述封装结构的另一面设置有导热金属结构。
3.如权利要求2所述的QFN封装结构，其特征在于，所述导热金属结构材质为不锈钢。
4.如权利要求2所述的封装结构，其特征在于，所述导热金属结构的厚度范围为：150um—350um。
5.如权利要求2所述的QFN封装结构，其特征在于，所述导热金属结构与所述绝缘材质之间通过银浆粘结。
6.如权利要求1所述的QFN封装结构，其特征在于，所述芯片的背面与所述基岛通过银浆粘结。
CN201310650663.3A 2013-12-03 2013-12-03 一种适合于led照明应用的多芯片qfn封装 Pending CN104681517A (zh)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104064560A (zh) * 2014-07-08 2014-09-24 苏州卓能微电子技术有限公司 一种适合于大功率led照明驱动电路应用的多芯片qfn封装
WO2018176656A1 (zh) * 2017-03-28 2018-10-04 山东晶泰星光电科技有限公司 Qfn表面贴装式rgb-led封装模组及其制造方法

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CN102738365A (zh) * 2012-06-05 2012-10-17 华天科技（西安）有限公司 一种基于dfn、qfn的新型led封装件及其制作方法
CN202930380U (zh) * 2012-10-22 2013-05-08 金建电子有限公司 整合驱动机制的全彩led封装结构
CN203013791U (zh) * 2012-06-05 2013-06-19 华天科技（西安）有限公司 一种基于dfn、qfn的新型led封装件
CN103296187A (zh) * 2013-06-06 2013-09-11 东莞博用电子科技有限公司 一种用于led交流驱动高压芯片的封装结构

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Publication number Priority date Publication date Assignee Title
CN101465348A (zh) * 2007-12-19 2009-06-24 台达电子工业股份有限公司 可降低操作温度的发光二极管封装模块
CN201289865Y (zh) * 2008-12-02 2009-08-12 深圳市聚飞光电有限公司 贴片发光二极管
CN202195296U (zh) * 2011-07-13 2012-04-18 深圳市三迅光电有限公司 一种可调色温的led照明灯
CN202188397U (zh) * 2011-08-08 2012-04-11 东莞柏泽光电科技有限公司 用于帮助植物生长的照明设备
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104064560A (zh) * 2014-07-08 2014-09-24 苏州卓能微电子技术有限公司 一种适合于大功率led照明驱动电路应用的多芯片qfn封装
WO2018176656A1 (zh) * 2017-03-28 2018-10-04 山东晶泰星光电科技有限公司 Qfn表面贴装式rgb-led封装模组及其制造方法

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Application publication date: 20150603