CN103367350A - 电子模块 - Google Patents

电子模块 Download PDF

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Publication number
CN103367350A
CN103367350A CN2013101145516A CN201310114551A CN103367350A CN 103367350 A CN103367350 A CN 103367350A CN 2013101145516 A CN2013101145516 A CN 2013101145516A CN 201310114551 A CN201310114551 A CN 201310114551A CN 103367350 A CN103367350 A CN 103367350A
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China
Prior art keywords
semiconductor chip
electronic module
material layer
carrier
module according
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Granted
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CN2013101145516A
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CN103367350B (zh
Inventor
K.霍赛尼
S.兰道
J.马勒
I.尼基廷
L.奥索夫斯基
T.沃夫拉
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Infineon Technologies AG
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Infineon Technologies AG
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Publication of CN103367350A publication Critical patent/CN103367350A/zh
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Abstract

电子模块包括第一载体和布置在第一载体上的第一半导体芯片。第二半导体芯片布置在第一半导体芯片上方。材料层将第二半导体芯片粘合至第一载体并封装第一半导体芯片。

Description

电子模块
技术领域
本发明涉及一种电子模块和一种用于制造电子模块的方法。
背景技术
在半导体芯片封装的领域中，非常经常出现以下问题：必须在载体上安装两个或更多个芯片，以制造半导体芯片封装。半导体芯片可以具有不同的功能、大小和属性。特别地，半导体芯片中的一个可以由功率半导体芯片组成，并且半导体芯片中的另一个可以由逻辑集成电路（IC）芯片组成，这两个芯片均是例如功率转换器或电源电路的一部分。原理上，可以将半导体芯片并排地布置在芯片载体上，这需要特殊的过程并导致具有相对大的基座面积的封装。然而，电子器件的领域中的总体目的在于：以小的总体大小尺寸，特别地以小的基座面积，制造电子器件。
附图说明
附图被包括以提供对实施例的进一步理解，并且被并入到本说明书中并构成本说明书的一部分。附图图解说明了实施例，并与描述一起用于说明实施例的原理。其他实施例以及实施例的许多预期优势随着它们参照以下详细描述变得更好理解而将容易地意识到。附图的元件不必相对于彼此按比例绘制。相似的参考标记指示对应的类似部分。
图1图解说明了根据实施例的电子模块的示意横截面侧视图表示；
图2图解说明了根据实施例的电子模块的示意横截面侧视图表示；
图3图解说明了根据实施例的电子模块的示意横截面侧视图表示；
图4图解说明了根据实施例的电子模块的示意横截面侧视图表示；
图5示出了用于图解说明根据实施例的用于制造电子模块的方法的流程图；
图6A-6D图解说明了用于图解说明根据实施例的用于制造电子模块的方法的示意横截面侧视图表示；
图7A-7C图解说明了用于图解说明根据实施例的用于制造电子模块的方法的示意横截面侧视图表示；以及
图8A-8B图解说明了用于图解说明根据实施例的用于制造电子模块的方法的示意横截面侧视图表示。
具体实施方式
现在参照附图来描述这些方面和实施例，其中，自始至终，相似的参考标记一般用于指代相似的元件。在以下描述中，出于说明的目的，阐述了许多具体细节以便提供对实施例的一个或多个方面的透彻理解。然而，对本领域技术人员来说可以显而易见，可以利用更小程度的具体细节来实施这些实施例的一个或多个方面。在其他实例中，以示意的形式示出了已知的结构和元件以便于描述实施例的一个或多个方面。要理解，在不脱离本发明的范围的前提下，可以利用其他实施例并且可以进行结构或逻辑的改变。应当进一步注意，附图不要按比例绘制或不必按比例绘制。
此外，尽管可以关于多个实施方式中的仅一个公开实施例的特定特征或方面，但是如对任何给定或特定应用来说可期望且有利的那样，可以将这种特征或方面与其他实施方式的一个或多个其他特征或方面进行组合。此外，在该详细描述或权利要求中使用术语“包括”、“具有”、“带有”或这些术语的其他变型的意义上，这些术语意在以与术语“包括”类似的方式是包含性的。可以使用术语“耦合”和“连接”以及派生词。应当理解，这些术语可以用于指示两个元件彼此协作或交互，不论它们是直接物理或电接触还是它们彼此不直接接触。此外，术语“示例性”仅意在作为示例，而不是最佳或最优的。因此，以下详细描述不要在限制的意义上理解，并且本发明的范围由所附权利要求限定。
电子模块和用于制造电子模块的方法的实施例可以使用各种类型的半导体芯片或在半导体芯片中并入的电路，在它们当中有逻辑集成电路、模拟集成电路、混合信号集成电路、传感器电路、MEMS（微机电系统）、功率集成电路、具有集成无源器件的芯片等。实施例也可以使用半导体芯片，包括晶体管、功率晶体管、MOS晶体管结构或垂直晶体管结构，像例如IGBT（绝缘栅双极晶体管）结构，或者一般地，以下晶体管结构：其中，至少一个电接触端子布置在半导体芯片的第一主面上并且至少一个其他电接触端子布置在半导体芯片的与半导体芯片的第一主面相对的第二主面上。
在多个实施例中，对彼此施加层或层堆叠，或者将材料施加或沉积至层上。应当意识到，诸如“施加”或“沉积”之类的任何术语意在在字面上覆盖将层施加至彼此之上的所有种类和技术。特别地，它们意在覆盖作为整体同时施加层的技术（比如例如层压技术）以及以顺序的方式沉积层的技术（像例如溅射、电镀、模塑、CVD等）。
参照图1，示出了根据实施例的电子模块的示意横截面侧视图表示。图1的电子模块10包括第一载体1、布置在第一载体1上的第一半导体芯片2、布置在第一半导体芯片2上方的第二半导体芯片3、以及将第二半导体芯片3粘合至第一载体1且封装第一半导体芯片2的材料层4。
根据电子模块10的实施例，材料层4可以由粘合箔或粘合带组成。原理上，粘合箔可以由任何种类的塑料材料或聚合物材料制成。它可以具有从20 μm至150 μm的范围内的厚度。
根据电子模块10的实施例，材料层4可以由粘合膏组成。
根据电子模块10的实施例，第二半导体芯片3可以具有比第一半导体芯片2更大的大小尺寸。特别地，如可在图1中看出，沿被表示为“x”的至少一个方向，第二半导体芯片3可以大于第一半导体芯片2。此外，沿与x方向垂直的另一水平方向（即，被表示为“y”的方向），第二半导体芯片3也可以大于第一半导体芯片2。在这种情况下，可以以如下方式将第二半导体芯片3布置在第一半导体芯片2上方：第二半导体芯片3具有横向延伸至第一半导体芯片2的相应侧边缘之外的外侧边缘。换言之，可以以如下方式将第二半导体芯片3布置在第一半导体芯片2上方：第二半导体芯片3沿所有方向与第一半导体芯片2全部重叠。
根据电子模块10的实施例，第二半导体芯片3和材料层4可以具有类似或相等的横侧尺寸，这意味着：其相应侧边缘横向彼此对准。
根据电子模块10的实施例，材料层4可以具有比第二半导体芯片3更大的横向大小尺寸。
根据电子模块10的实施例，第一半导体芯片2可以具有小于100 μm的厚度，特别地，10 μm至100 μm的厚度，特别地，20 μm至50 μm的厚度。
根据电子模块10的实施例，第二半导体芯片3可以具有从40 μm至800 μm的范围内的厚度。
根据电子模块10的实施例，第二半导体芯片3可以具有比第一半导体芯片2的厚度大的厚度。特别地，第二半导体芯片2可以具有为第一半导体芯片2的厚度至少两倍的厚度。要理解，厚度方向与如图1所示的z方向相对应。
根据电子模块10的实施例，第一和第二半导体芯片2和3可以彼此电连接。
根据电子模块10的实施例，第一半导体芯片3可以由晶体管芯片、MOS晶体管芯片、垂直晶体管芯片、IGBT晶体管芯片和功率晶体管芯片中的一个或多个组成。第二半导体芯片3可以由处理器芯片、控制器芯片、逻辑电路芯片和集成电路芯片中的一个或多个组成。
根据电子模块10的实施例，第一半导体芯片2可以由处理器芯片、控制器芯片、逻辑电路芯片和集成电路芯片中的一个或多个组成。第二半导体芯片3可以由晶体管芯片、MOS晶体管芯片、垂直晶体管芯片、IGBT晶体管芯片和功率晶体管芯片中的一个或多个组成。
根据电子模块10的实施例，材料层4可以是导电的。材料层4可以包括各向同性导电性或各向异性导电性。还可以是以下情况：第一和第二半导体芯片2和3中的一个或多个可以包括至少一个电接触元件，并且材料层4可以将第一半导体芯片2或第二半导体芯片3的电接触元件与第一载体1电连接，或者与第一和第二半导体芯片2和3中相应的另一个的电接触元件电连接。稍后将示出并说明稍微更详细的实施例。
根据电子模块10的实施例，材料层4可以包括嵌入其中的导电颗粒。导电颗粒可以均匀分布在材料层4内，使得材料层4可以包括各向同性导电性。导电颗粒还可以非均匀分布在材料层4内，使得材料层4可以包括各向异性导电性。
根据电子模块10的实施例，第三半导体芯片可以布置在第一半导体芯片2上方且横向靠近第二半导体芯片3。第三半导体芯片可以通过材料层4粘合至第一载体1。可以对第二和第三半导体芯片进行尺寸调整，使得它们中的每一个具有比第一半导体芯片2更小的横向大小尺寸，但是可以以如下方式布置第二和第三半导体芯片：第二和第三半导体芯片沿所有方向均与第一半导体芯片1横向完全重叠。稍后将示出并说明稍微更详细的实施例。
根据电子模块10的实施例，第一半导体芯片1可以在面向第二半导体芯片2的第一主面上包括第一电接触元件。电子模块10还可以包括电连接器以及将第一电接触元件与电连接器相连接的电气构件。电连接器可以设置在与第一载体1相同的平面中。第一载体1和电连接器均可以源自同一个引线框，其可以在制造过程的开始时邻接并且然后可以在制造过程期间被分离为不同电气构件。电气构件可以包括在金属夹上，金属夹可以具有刚性形式和形状并可以以上部分的平面下表面连接至第一半导体芯片2的第一电接触元件上、并且然后可以向下延伸至电连接器并可以以下部分与电连接器相连接。稍后将示出并说明稍微更详细的实施例。
根据电子模块10的实施例，电子模块10还可以包括第二载体，第二载体可以布置在与第一载体1相同的平面中，但与第一载体1电隔离。第一半导体芯片2可以布置在第一载体1上和第二载体上。特别地，第一半导体芯片2可以包括至少两个电接触元件，其中一个与第一载体1相连接并且其中另一个与第二载体相连接。还可以是以下情况：第二半导体芯片3横向延伸至第二载体上方，并且材料层4附着至第二载体。以下将示出并说明稍微更详细的实施例。
参照图2，示出了根据实施例的电子模块的示意横截面侧视图表示。图2的电子模块20包括第一载体21、第二载体22、布置在第一和第二载体21和22上的第一半导体芯片23、布置在第一半导体芯片23上方的第二半导体芯片24、以及将第二半导体芯片24粘合至第一和第二载体21和22且封装第一半导体芯片23的材料层25。
第一半导体芯片23可以由晶体管芯片、MOS晶体管芯片、垂直晶体管芯片、IGBT晶体管芯片和功率晶体管芯片中的一个或多个组成。在任何情况下，第一半导体芯片23可以包括：第一电接触元件23.1和第二电接触元件23.2，均布置在第一半导体芯片23的下主表面上；以及第三电接触元件23.3，布置在第一半导体芯片23的上主表面上。第一电接触元件23.1可以是源极接触元件，第二电接触元件23.2可以是栅极接触元件，并且第三电接触元件23.3可以是晶体管芯片的漏极接触元件。第一电接触元件23.1可以附着至第一载体21并与第一载体21电连接，并且第二电接触元件23.2可以附着至第二载体22并与第二载体22电连接。
图2的电子模块20还可以包括电连接器26，电连接器26可以与第一和第二载体21和22布置在同一个平面中。第一和第二载体21和22以及电连接器26可以源自同一个引线框，其可以在制造过程的开始时邻接并且可以相继被分离为彼此电隔离的不同电气载体和连接器。电连接器26可以通过可以具有刚性形式和形状的电气构件27与第三电接触元件23.3相连接。
第一半导体芯片23可以具有从10 μm至100 μm的范围内的厚度，特别地从20 μm至50 μm的范围内的厚度。
第二半导体芯片24可以由处理器芯片、控制器芯片、集成电路芯片和逻辑集成电路芯片中的一个或多个组成。其可以具有从40 μm至800 μm的范围内的厚度。第二半导体芯片24可以包括可远离材料层25的电接触元件24.1。然而，电接触元件24.1还可以被布置为与材料层25相接触或面向材料层25。
这里要理解，以上结合图1的电子模块10描述的不同特征和实施例也可以适用于图2的电子模块20的相应部件中的每一个。
参照图3，示出了根据实施例的电子模块的示意横截面侧视图表示。图3的电子模块30包括第一载体31和第二载体37、电连接器元件36、布置在载体31上的第一半导体芯片32、布置在第一半导体芯片32上方的第二半导体芯片34、以及将第二半导体芯片34粘合至载体31且封装第一半导体芯片32的材料层33。
第一半导体芯片32可以由处理器芯片、控制器芯片、集成电路芯片和逻辑集成电路芯片中的一个或多个组成。第一半导体芯片32还可以包括布置在下主面上的一个或多个电接触元件32.1，并且电接触元件32.1中的每一个通过焊球35连接至电连接器元件36。电连接器元件36以及第一和第二载体31和37中的每一个可以源自同一个引线框，其在制造过程的开始时邻接并且被分离为第一和第二载体31和37以及电连接器元件36。
第二半导体芯片34可以由晶体管芯片、MOS晶体管芯片、垂直晶体管芯片、IGBT晶体管芯片和功率晶体管芯片中的一个或多个组成。第二半导体芯片34包括第一下主面上的第一电接触元件34.1、布置在第二上主面上的第二电接触元件34.2、以及布置在第二半导体芯片34的第二上主面上的第三电接触元件34.3。第一电接触元件34.1可以是漏极接触元件，第二电接触元件34.2可以是源极接触元件，以及第三电接触元件34.3可以是晶体管芯片的栅极接触元件。
材料层33可以封装第一半导体芯片32，并且它可以同时充当布置在第一半导体芯片32下方的焊球35的底部填充并将电接触元件32.1分别与第一和第二载体31和37以及电连接器元件36相连接。
这里要理解，以上结合图1的电子模块10描述的不同特征和实施例也可以适用于图3的电子模块30的相应部件中的每一个。
参照图4，示出了根据实施例的电子模块的示意横截面侧视图表示。图4的电子模块40可以包括载体41、布置在载体41上的第一半导体芯片42、布置在第一半导体芯片42上方的第二半导体芯片43、布置在第一半导体芯片42上方的第三半导体芯片44、以及将第二和第三半导体芯片43和44粘合至载体41且封装第一半导体芯片42的材料层45。
第一半导体芯片42可以是晶体管芯片、MOS晶体管芯片、垂直晶体管芯片、IGBT晶体管芯片和功率晶体管芯片中的一个或多个。第一半导体芯片42包括：第一电接触元件42.1，布置在第一半导体芯片42的下表面上并附着至载体41并与载体41电连接；第二电接触元件42.2，布置在第一半导体芯片42的第二上表面上；以及第三电接触元件42.3，布置在半导体芯片42的第二上表面上。第一电接触元件42.1可以由漏极接触元件组成，第二电接触元件42.2可以由源极接触元件组成，以及第三电接触元件42.3可以由第一半导体芯片42的栅极接触元件组成。
第二半导体芯片43可以由晶体管芯片、MOS晶体管芯片、垂直晶体管芯片、IGBT晶体管芯片和功率晶体管芯片中的一个或多个组成。第二半导体芯片43包括：第一电接触元件43.1，处于与材料层45的上表面附着的第一下表面上；第二电接触元件43.2，布置在第二上表面上；以及第三电接触元件43.3，布置在第二半导体芯片43的第二上表面上。第一电接触元件43.1可以是漏极接触元件，第二电接触元件43.2可以是源极接触元件，以及第三电接触元件43.3可以是第二半导体芯片43的栅极接触元件。材料层45可以包括各向异性导电性，该各向异性导电性可以是通过以非均匀分布的方式利用导电颗粒45.1填充材料层45来实现的。如图4所示，可以将导电颗粒45.1填充至材料层45中，以使得在材料层45的处于第一半导体芯片42的第二电接触元件42.2与第二半导体芯片43的第一电接触元件43.1之间的区域中聚集导电颗粒45.1，从而可以提供这些电接触元件之间的电连接并因此可以提供第一和第二半导体芯片42和43之间的电连接。还示出了：可以将导电颗粒45.1填充至材料层45中，以使得在材料层45的处于第一半导体芯片42的第三电接触元件42.3与第三半导体芯片44的下表面之间的区域中聚集导电颗粒45.1，从而还可以提供第一和第三半导体芯片42和44之间的电连接。
第三半导体芯片44可以由处理器芯片、控制器芯片、集成电路芯片和逻辑集成电路芯片中的一个或多个组成。第三半导体芯片44可以在与材料层45远离的表面上，或者可替换地，在与材料层45相邻的表面上，包括接触元件44.1。
这里要理解，以上结合图1的电子模块10描述的不同特征和实施例也可以适用于图4的电子模块40的相应部件中的每一个。
参照图5，示出了用于图解说明根据实施例的用于制造电子模块的方法的流程图。方法50包括：将第一半导体芯片附着在第一载体上（51）；将材料层附着在第二半导体芯片的主面上（52）；以及将第二半导体芯片布置在第一半导体芯片上方，使得材料层附着至第一载体并封装第一半导体芯片（53）。
根据图5的方法50的实施例，材料层可以由粘合箔组成，并且将材料层附着在第二半导体芯片的主面上可以包括将粘合箔层压在第二半导体芯片的主面上。
根据图5的方法50的实施例，材料层可以由粘合膏组成，并且将材料层附着在第二半导体芯片的主面上可以包括将粘合膏施加在第二半导体芯片的主面上。
根据图5的方法50的实施例，方法50还包括：在将第二半导体芯片施加于第一半导体芯片之前，通过使用电气构件，将第一半导体芯片与电连接器电连接。电连接器可以设置在与第一载体相同的平面中并可以与第一载体源自同一个引线框。
根据图5的方法50的实施例，还可以将第一半导体芯片附着在可与第一载体电隔离的第二载体上。第二载体可以设置在与第一载体相同的平面中，并且它可以与第一载体源自同一个引线框。第一半导体芯片可以在其主表面之一上包括第一电接触元件和第二电接触元件，并且可以将第一电接触元件附着至第一载体并与第一载体电连接，并且可以将第二电接触元件附着至第二载体并与第二载体电连接。可以以如下方式将第二半导体芯片布置在第一半导体芯片上方：材料层也附着至第二载体。
根据图5的方法50的实施例，将第三半导体芯片布置在第一半导体芯片上方且靠近第二半导体芯片，其中，该方法还可以包括：通过使用材料层，将第三半导体芯片粘合至载体。
参照图6A-6D，示出了用于图解说明根据实施例的示例性方法的示意横截面侧视图表示。图6A示出了第一载体61.1、第二载体61.2、第三载体61.3、第一电连接器61.4和第二电连接器61.5，所有这些可以源自同一个引线框61并将要在制造过程期间彼此分离。第一功率晶体管芯片62附着在第一和第二载体61.1和61.2上，并且第二功率晶体管芯片63附着在第二和第三载体61.2和61.3上。第一功率晶体管芯片62在其下主表面上包括源极接触元件62.1和栅极接触元件62.2，并且源极接触元件62.1附着至第一载体61.1并与第一载体61.1电连接，并且栅极接触元件62.2附着至第二载体61.2并与第二载体61.2电连接。功率晶体管芯片62还在其上主表面上包括漏极接触元件62.3。第二功率晶体管芯片63在其下主表面上包括源极接触元件63.1和栅极接触元件63.2，并且源极接触元件63.1附着至第三载体61.3并与第三载体61.3电连接，并且栅极接触元件63.2附着至第二载体61.2并与第二载体61.2电连接。第二功率晶体管芯片63还在其上主表面上包括漏极接触元件63.3。
图6B示出了在将第一和第二功率晶体管芯片62和63分别电连接至第一和第二电连接器61.4和61.5之后的组件。利用第一电气构件64在漏极接触元件62.3与第一电连接器61.4之间进行电连接，并且利用第二电气构件65在漏极接触元件63.3与第二电连接器61.5之间进行电接触。第一和第二电气构件64和65可以由金属夹制成。
图6C示出了包括具有电接触元件66.1的逻辑集成电路芯片66的组件的示意横截面侧视图表示。在逻辑集成电路芯片66的与电接触元件66.1远离的主表面上，附着了粘合箔67，粘合箔67可以具有从20 μm至150 μm的范围内的厚度。附图不必按比例绘制，这意味着：原理上，芯片66可以具有从40 μm至800 μm的范围内的任何期望厚度。
图6D再次示出了完整组件，其中，逻辑集成电路芯片66与粘合箔67一起附着至第一功率晶体管芯片62以及第一和第二载体61.1和61.2。粘合箔67的尺寸可以使得粘合箔67在所有侧封装第一功率晶体管芯片62。
图7A-7C示出了用于图解说明根据实施例的用于制造电子模块的方法的示意横截面侧视图表示。图7A示出了以下组件，该组件包括第一载体71.1、第二载体71.2、第一电连接器71.3、第二电连接器71.4和第三电连接器71.5，所有这些可以源自同一个引线框71并可以在制造过程期间彼此分离。该组件还可以包括逻辑集成电路72，逻辑集成电路72在其下主表面处包括电接触元件72.1。电接触元件72.1中的每一个通过焊球73与第一和第二载体71.1和71.2之一或电连接器71.3至71.5之一电连接。
图7B示出了包括功率晶体管芯片74和粘合箔75的组件。功率晶体管芯片74在其下主表面上包括漏极接触元件74.1，并在其上主表面上包括源极接触元件74.2和栅极接触元件74.3。粘合箔75附着至功率晶体管芯片74的下主表面，即，附着至漏极接触元件74.1。粘合箔可以包括从20 μm至150 μm的范围内的厚度。附图不必按比例绘制，这意味着：原理上，功率晶体管芯片可以具有任何期望厚度。
图7C示出了在将功率晶体管芯片74与粘合箔75一起附着至逻辑集成电路芯片72、第一和第二载体71.1和71.2以及第一至第三电连接器71.3至71.5之后的组件。粘合箔75的尺寸可以使得粘合箔75从所有侧完全封装逻辑集成电路芯片72。
图8A和8B示意性地示出了用于图解说明根据实施例的用于制造电子模块的方法的横截面侧视图表示。图8A示出了由载体81、第一功率晶体管芯片82和粘合膏83组成的组件。第一功率晶体管芯片82可以包括漏极接触元件82.1、源极接触元件82.2和栅极接触元件82.3。第一功率晶体管芯片82可以以如下方式附着至载体81：漏极接触元件82.1附着至载体81的表面并与载体81的表面电连接。粘合膏83可以以如下方式附着至第一功率晶体管芯片：粘合膏83在所有侧完全封装第一功率晶体管芯片82。粘合膏83可以包括导电颗粒83.1，导电颗粒83.1可以非均匀地分布在粘合膏83内，使得粘合膏83可以包括各向异性导电性。
图8B示出了将第二功率晶体管芯片84和逻辑集成电路芯片85附着至粘合膏83的上表面之后的组件。第二功率晶体管芯片84可以在其下主表面上包括漏极接触元件84.1，并在其上主表面上包括源极接触元件84.2和栅极接触元件84.3。第二功率晶体管芯片84可以以如下方式附着至粘合膏83：漏极接触元件84.1附着至粘合膏83的上表面，并与粘合膏83的导电区域进行电接触。粘合膏83的导电区域由粘合膏83的处于第一功率晶体管芯片82的源极接触元件82.2与第二功率晶体管芯片84的漏极接触元件84.1之间的区域中的导电颗粒83.1的高聚集用符号表示。逻辑集成电路芯片85可以在与粘合膏83远离的上主表面处包括电接触元件85.1，并且逻辑集成电路芯片85还可以在其下主表面（未示出）上包括电接触元件，该电接触元件可以通过粘合膏83的导电区域电连接至第一功率晶体管芯片82的栅极接触元件82.3。
尽管关于一个或多个实施方式示意和描述了本发明，但是在不脱离所附权利要求的精神和范围的前提下，可以对所图解说明的示例进行更改和/或修改。特别地，关于由上述部件或结构（组件、器件、电路、系统等）执行的各种功能，除另有指示外，用于描述这种部件的术语（包括对“装置”的引用）意在与执行所描述的组件的指定功能的任何组件或结构相对应（例如，在功能上等同），即使未在结构上与执行本发明的本文图解说明的示例性实施方式中的功能的所公开结构等同。

Claims (30)

1.一种电子模块，包括：
载体；
第一半导体芯片，布置在所述载体上；
第二半导体芯片，布置在所述第一半导体芯片上方；以及
材料层，将所述第二半导体芯片粘合至所述载体并封装所述第一半导体芯片。
2.根据权利要求1所述的电子模块，其中，所述材料层包括聚合物。
3.根据权利要求1所述的电子模块，其中，所述材料层包括粘合箔。
4.根据权利要求1所述的电子模块，其中，所述材料层包括粘合膏。
5.根据权利要求1所述的电子模块，其中，所述第二半导体芯片比所述第一半导体芯片大。
6.根据权利要求1所述的电子模块，其中，所述第一半导体芯片具有小于100 μm的厚度。
7.根据权利要求1所述的电子模块，其中，所述第二半导体芯片具有从40 μm至800 μm的范围内的厚度。
8.根据权利要求1所述的电子模块，其中：
所述第一半导体芯片包括功率晶体管芯片；以及
所述第二半导体芯片包括集成电路芯片。
9.根据权利要求1所述的电子模块，其中：
所述第一半导体芯片包括集成电路芯片；以及
所述第二半导体芯片包括功率晶体管芯片。
10.根据权利要求1所述的电子模块，其中，所述材料层是导电的。
11.根据权利要求10所述的电子模块，其中，所述材料层具有各向异性导电性。
12.根据权利要求10所述的电子模块，其中，所述材料层具有各向同性导电性。
13.根据权利要求10所述的电子模块，其中：
所述第二半导体芯片包括电接触元件；以及
所述材料层将所述第二半导体芯片的电接触元件与所述载体电连接。
14.根据权利要求10所述的电子模块，其中：
所述第一半导体芯片和所述第二半导体芯片中的每一个包括电接触元件；以及
所述材料层将所述第一半导体芯片的电接触元件电连接至所述第二半导体芯片的电接触元件。
15.根据权利要求1所述的电子模块，还包括：第三半导体芯片，布置在所述第一半导体芯片上方且靠近所述第二半导体芯片。
16.根据权利要求15所述的电子模块，其中，所述材料层将所述第三半导体芯片粘合至所述载体。
17.根据权利要求1所述的电子模块，其中：
所述第一半导体芯片在面向所述第二半导体芯片的第一主面上包括第一电接触元件，所述电子模块还包括将所述第一电接触元件与电连接器相连接的电气构件。
18.根据权利要求17所述的电子模块，其中，所述电连接器设置在与所述载体相同的平面中。
19.一种模块，包括：
第一载体；
第一半导体芯片，布置在所述第一载体上；
材料层，封装所述第一半导体芯片；以及
第二半导体芯片，布置在所述材料层上。
20.根据权利要求19所述的电子模块，还包括：
第二载体，
其中，所述第一半导体芯片还布置在所述第二载体上；以及
其中，所述材料层覆盖所述第一载体和所述第二载体以及所述第一半导体芯片。
21.根据权利要求20所述的电子模块，其中，所述第一半导体芯片包括与所述第一载体相连接的第一电接触元件和与所述第二载体相连接的第二电接触元件。
22.根据权利要求19所述的电子模块，其中，所述第一半导体芯片在与所述第一载体远离的主面上包括电接触元件。
23.根据权利要求22所述的电子模块，还包括：
电连接器；以及
电气构件，将所述电接触元件与所述电连接器相连接。
24.根据权利要求23所述的电子模块，其中，所述电连接器设置在与所述第一载体相同的平面中。
25.一种用于制造电子模块的方法，所述方法包括：
将第一半导体芯片附着至第一载体；
在第二半导体芯片的主面上形成材料层；以及
将所述第二半导体芯片施加于所述第一半导体芯片，使得所述材料层附着至所述第一载体并封装所述第一半导体芯片。
26.根据权利要求25所述的方法，其中，所述第一半导体芯片具有小于100 μm的厚度。
27.根据权利要求25所述的方法，其中，所述材料层具有比所述第一半导体芯片的厚度大的厚度。
28.根据权利要求25所述的方法，其中：
所述材料层包括粘合箔，以及
形成材料层包括将所述粘合箔层压在所述第二半导体芯片的主面上。
29.根据权利要求25所述的方法，其中：
所述材料层包括粘合膏，以及
形成材料层包括将所述粘合膏施加在所述第二半导体芯片的主面上。
30.根据权利要求25所述的方法，其中，所述材料层包括聚合物。
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