CN104701308A - 电子器件 - Google Patents

电子器件 Download PDF

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Publication number
CN104701308A
CN104701308A CN201410742258.9A CN201410742258A CN104701308A CN 104701308 A CN104701308 A CN 104701308A CN 201410742258 A CN201410742258 A CN 201410742258A CN 104701308 A CN104701308 A CN 104701308A
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CN
China
Prior art keywords
semiconductor element
electronic device
substrate
contact
semiconductor
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CN201410742258.9A
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English (en)
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CN104701308B (zh
Inventor
K·霍塞尼
J·马勒
R·奥特雷姆巴
J·赫格劳尔
J·施雷德尔
X·施勒格尔
K·希斯
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Infineon Technologies Austria AG
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Infineon Technologies Austria AG
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Priority to CN201810140687.7A priority Critical patent/CN108155168B/zh
Publication of CN104701308A publication Critical patent/CN104701308A/zh
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Publication of CN104701308B publication Critical patent/CN104701308B/zh
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Abstract

本发明涉及电子器件。该电子器件包括在单个壳体中的多个半导体芯片。这样的半导体芯片可以包括不同的半导体材料，例如它们可以包括GaN。使用键合夹片而不是键合线是将这样的半导体芯片连接到衬底的高效方式。

Description

电子器件
技术领域
本发明涉及电子器件和用于制造电子器件的方法。
背景技术
对于面向应用的电子器件的不断增长的需求导致半导体元件在壳体中的日益复杂的布局。这样的元件可以按照不同的配置来布置，如“芯片并排(chip by chip)”、“芯片在芯片上(chip on chip)”“芯片在夹片上(chip on clip)”等。用语“系统级封装”(SIP)是指在单个壳体中包括多芯片模块的器件。SIP可以用于简化模块组件并且减小在板上的所需空间。此外，对于利用除了常规器件中采用的那些半导体材料之外的半导体材料，存在日益增长的需求，以便从它们的电子特性中受益。
发明内容
本发明的目的在于提供一种电子器件，满足现有技术中的上述需求。
根据本发明一个方面的实施例，提供一种电子器件，包括：衬底；第一半导体元件，包括一个或多个第一接触元件，所述第一半导体元件布置在所述衬底上；第二半导体元件，包括一个或多个第二接触元件，所述第二半导体元件布置在所述衬底上；以及键合夹片，将所述第一半导体元件和所述第二半导体元件上的所述第一接触元件和所述第二接触元件中的一个或多个电连接到所述衬底。
根据本发明另一方面的实施例，提供一种电子器件，包括：第一半导体元件，包括第一接触元件；第二半导体元件，包括第二接触元件；以及第一衬底元件和与所述第一衬底元件不同的第二衬底元件，其中所述第一半导体元件和所述第二半导体元件布置在所述第一衬底元件上。
根据本发明又一方面的实施例，提供一种电子器件，包括：第一半导体元件，包括第一接触元件；第二半导体元件，包括第二接触元件；以及第一衬底元件和与所述第一衬底元件不同的第二衬底元件，其中所述第一半导体元件和所述第二半导体元件布置在所述第一衬底元件上，其中所述电子器件包括共源共栅电路。
根据本发明的电子器件的实施例，可以提供若干优势，诸如允许在一个壳体中的更高度集成、提供更好的导热性和导电性。
附图说明
附图被包括在内以提供对实施例的进一步理解，并且附图被结合到本说明书中并构成本说明书的一部分。附图图示了实施例并且与本描述一起用于说明实施例的原理。将容易认识到其它实施例和实施例的许多预期优势，因为通过参考以下的详细描述，它们变得更好理解。附图的元件不一定相对彼此成比例。相同的参考标号标示对应的类似部分。
图1包括图1A-图1E，示意性地示出电子器件及其组件的各种阶段的实施例。
图2包括图2A-图2D，示意性地示出电子器件的进一步实施例。
图3包括图3A和图3B，示出了使用电子器件的一些实施例实现的电路的电路图。
图4示出了用于制造电子器件的方法的实施例的流程图。
具体实施方式
现在参照附图描述各方面和实施例，其中贯穿所有附图，类似的参考标号通常用于指代类似的元件。在以下的描述中，为说明的目的，阐述很多特定细节，以便提供对实施例的一个或多个方面的透彻理解。然而，本领域技术人员可以明白的是，实施例的一个或多个方面可以在更少程度的特定细节的情况下实施。在其它情形中，将已知结构和元件以示意形式示出，以便于描述实施例的一个或多个方面。将理解的是，可以利用其它实施例，并且可以进行结构或逻辑的改变，而不脱离本发明的范围。应进一步注意的是，附图并未按比例或者不一定按比例。
此外，尽管实施例的具体特征或方面可能关于若干实现中的仅一种实现而公开，但如对于任何给定或具体应用可能期望和有利的那样，可以将这种特征或方面与其它实现的一个或多个其它特征或方面结合。而且，在详细描述或权利要求中使用用语“包含”、“含有”、“具有”或其其它变体的程度上，这种用语旨在以类似于用语“包括”的方式为包含性的。可以使用用语“耦合”和“连接”以及派生词。应理解的是，这些用语可以用于指示两个元件彼此合作或交互，而不管它们是直接物理接触或电接触，还是它们没有彼此直接接触。而且，用语“示例性”仅旨在作为示例，而非最佳或最优。因此，以下的详细描述并不是在限制意义上作出的，并且本发明的范围由所附权利要求限定。
电子器件的实施例可以使用各种类型的晶体管器件。实施例可以使用在半导体裸片或半导体芯片中实施的晶体管器件，其中半导体裸片或半导体芯片可以提供为从半导体晶片制造并从半导体晶片切割出来的半导体材料块的形式，或者提供为其中已经执行进一步的工艺步骤的另一形式，例如，对该半导体裸片或半导体芯片施加封装层。实施例也可以使用包括MOS晶体管结构或IGBT(绝缘栅双极晶体管)结构的晶体管器件，其中这些结构可以提供为其中晶体管器件的接触元件设置在半导体裸片的主面之一上的形式(水平晶体管结构)，或者提供为其中至少一个电接触元件布置在半导体裸片的第一主面上且至少一个其它电接触元件布置在与半导体裸片的主面相对的第二主面上的形式(垂直晶体管结构)。
在任何情况下，半导体裸片或半导体芯片都可以包括在其外表面的一个或多个上的接触元件或接触焊盘，其中接触元件用于电接触半导体裸片。接触元件可以具有任何期望的形式或形状。例如它们在半导体裸片的外表面上可以具有连接盘(land)的形式，即，平坦接触层。接触元件或接触焊盘可以从任何导电材料制成，例如从金属如铝、镍、银、金或铜，或金属合金，或导电有机材料，或导电半导体材料。接触元件也可以形成为上述材料中的一个或多个的层堆叠。
根据电子器件的实施例，期望的是提供用于嵌入半导体裸片的封装。根据其实施例，电子器件可以符合单列直插式封装形式。此外或独立于此，电子器件可以包括具有外部引线的封装，该外部引线布置成使得封装类似TO(晶体管外形)类型封装，诸如TO-220或TO-247或TO-264封装。根据电子器件的实施例，提供作为外部引线的多个引线，使得可以将电子器件安装到如印刷电路板(PCB)的基板。
电子器件的实施例或晶体管器件的实施例可以包括其中嵌入有半导体裸片或晶体管器件的密封剂或密封材料。密封材料可以是任何电绝缘材料，例如任何种类的模制材料、任何种类的树脂材料或任何种类的环氧树脂材料。密封材料也可以是聚合物材料、聚氨酰胺材料、热塑性材料、有机硅材料、陶瓷材料和玻璃材料。密封材料也可以包括上述材料中的任意材料，并且进一步包括其中嵌入的填充剂材料例如导热添加物(increments)。这些填充剂添加物可以由例如AlO或Al2O3、AlN、BN或者SiN制成。
这里所述的器件可以包括一个或多个半导体芯片。半导体芯片可以为不同类型的，并且可以通过不同的技术制造。例如，半导体芯片可以包括集成电、光电或机电的电路或无源器件。集成电路可以设计为逻辑集成电路、模拟集成电路、混合信号集成电路、功率集成电路、存储器电路、集成无源器件或者微机电系统，微机电系统可以包括诸如桥、薄膜或舌结构之类的微机械结构。半导体芯片不是必需由例如Si、SiC、SiGe、GaAs、GaN的特定半导体材料制造，而是可以包含不是半导体的无机和/或有机材料，例如绝缘体、塑料或金属。此外，半导体芯片可以是封装的或未封装的。
在图1A-图1E中示出了电子器件100及其组件的实施例。该电子器件可以包括如图1A所示那样的两个半导体元件101和102。半导体元件101可以包括大量接触元件(电极)，例如半导体元件101可以包括三个电极103A、103B、103C。根据一个实施例，电极103A可以为漏极电极，103B可以为源极电极，103C可以为栅极电极。
根据一个实施例，所有电极可以布置在半导体元件101的一个主表面上。当如下面进一步描述的那样，将半导体元件101、102集成到一个电子器件中时，以此方式布置电极可以是有利的。
根据一个实施例，半导体元件102可以包括两个电极104。两个电极104可以布置在半导体元件102的彼此相对的两个主表面上。
根据一个实施例，半导体元件101可以包括基于III-V的半导体材料，例如GaN。在其它实施例中，半导体元件101可以包括其它合适材料或材料组成。
在一些实施例中，半导体元件101可以包括高电子迁移率晶体管(HEMT)。
在一些实施例中，半导体元件102可以包括特别是续流二极管的二极管、MOSFET或IGBT。在其它实施例中，半导体元件102可以包括本领域公知的功能性。
图1B示出了布置在半导体元件101上的衬底105。衬底105例如可以包括引线框架、印刷电路板(PCB)或直接键合铜(DBC)。在一个实施例中，衬底105可以包括多个接触105A、105B、105C，该多个接触被设计成电接触电极103A、103B、103C。衬底105可以经由焊接、导电膏剂或胶、导电胶类型、扩散焊接或本领域公知的任何其它合适工艺连接到半导体元件101。
衬底105可以具有任何合适形状，例如，接触105A、105B、105C不必一定呈现如图1B示意性绘出的规则形状。在一些实施例中，衬底105可以包括如铝、镍、银、金或铜的金属，或者在其它实施例中，衬底105可以包括金属合金或其它合适导电材料。接触105A、105B、105C例如可以被设计成覆盖电极103A、103B、103C的表面的大部分或甚至全部。这可以提高电子器件100的电性能和热性能。
衬底105可以包括延伸到半导体元件101的区域之外的多个引线。这些引线可以被设计成将电子器件100连接到PCB。根据一个实施例，可以经由通孔技术来实现该连接。引线可以是弯曲的，并且不必一定布置在一个平面中，而是可以布置在不同的平面中。例如，一些引线可以弯曲，使得它们与其它引线并行地但在其它引线之上或之下的平面中延伸到半导体元件101的区域之外。
图1C示出了在衬底105之上和之下的半导体元件101、102的布置，使得衬底105被夹在两个半导体元件之间。半导体元件102可以使用与连接上述半导体元件101时的相同技术来连接到衬底105。图1C进一步示出键合夹片(bonding clip)106，该键合夹片被设计成使半导体元件102上的电极电连接到衬底105，该半导体元件102上的电极并不直接接触衬底。该夹可以经由焊接、导电膏剂或胶、导电胶类型、扩散焊接或本领域公知的任何其它合适工艺接触到半导体元件102上的电极。
在一些实施例中，键合夹片106可以包括如铝、镍、银、金或铜的金属，或者在其它实施例中，键合夹片106可以包括金属合金或其它合适导电材料。特别地，键合夹片106可以包括与衬底105相同的材料。
根据一个实施例，键合夹片106可以包括单个结构元件。根据另一实施例，键合夹片106由多于一个的连接的结构元件组成。此外，键合夹片106可以具有任何合适的形状和定向。
键合夹片106可以被设计成覆盖电极104的大部分或全部。这可以提高电子器件100的电性能和热性能。
根据一个实施例，半导体元件102可以连接到衬底105B，使得半导体元件102的正极与源极电极103B电接触。键合夹片106用于将半导体元件102的负极连接到衬底105A并且因此连接到漏极电极103A。
使用具有大接触面积的键合夹片而不是键合线可以提高导电性和导热性，并因而提高电子器件100的性能。使用键合夹片而不是键合线因此可以是必需的，以便高效地使用包括如GaN的基于III-V的半导体材料的半导体元件101。
图1D示出沿图1C所示的箭头A1的视图。如所见，键合夹片106可以用于将半导体元件102的相对侧上的电极连接到衬底105。
图1E示出沿图1C所示的箭头A2的视图。图1E进一步示出根据电子器件100的一个实施例的密封剂107，该密封剂密封半导体芯片101、102、键合夹片106和衬底105的一部分。这样的电子器件100可以称为系统级封装(SIP)。图1E所示的电子器件包括具有水平晶体管结构的半导体元件101和具有垂直晶体管结构的半导体元件102。在一个实施例中，衬底105和夹片106从密封材料107部分地露出。
根据一些实施例，电子器件100可以遵循如TO-220或TO-247或TO-264的晶体管外形或另一晶体管外形。
在一些实施例中，电子器件100可以包括图1E中未示出的其它元件。
根据一个实施例，电子器件100为信号转换器或反相器。
电子器件100的实施例可以提供若干优势，诸如允许在一个壳体中的更高度集成、由于引线框架或DBC构造而提供更好的导热性和导电性、以及由于电极和引线之间的直接连接而减小电感。
在图2A-图2D中，示出电子器件的实施例200A、200B。如图2A所示，电子器件200A可以包括第一半导体元件201、第二半导体元件202和衬底205。衬底205可以包括两个电断开的部分，其中在一个实施例中，第一部分可以包括引线205A、205B、205C，第二部分可以包括支架205D，在支架205D上布置半导体元件201、202。
半导体元件201可以以源极朝下的配置布置在支架205D上，也就是，源极电极面向支架205D并电连接到支架205D。漏极电极203A和栅极电极203B背向支架205D地布置在半导体元件201的顶表面上。相反，半导体元件202可以以漏极朝下的配置布置在支架205D上，也就是，漏极电极面向支架205D并电连接到支架205D。源极电极208A和栅极电极208B背向支架205D地布置在半导体元件202的顶表面上。
根据该实施例200A，可以使用键合线来创建顶部电极203A、203B、208A、208B与引线205A、205B、205C之间的电连接。
根据一个实施例，半导体元件201可以包括基于III-V的半导体材料，特别是GaN，并且可以配置为支持大于200V的高电压的HEMT。半导体元件202可以包括Si或SiC，并且可以配置为低于200V的低电压的功率MOSFET。根据其它实施例，半导体元件201和202可以与上面相反地布置，也就是，半导体元件202可以配置为上述的HEMT，半导体元件201可以配置为上述的功率MOSFET。
根据一些实施例，可以通过键合夹片替代键合线209的一些或全部。在图2B所示的实施例200B中，使用键合夹片206A、206B来实现至功率电极203A(源极电极)和208A(漏极电极)的电连接。注意，键合夹片206A也连接到栅极电极208B。如上述，使用键合夹片代替键合线可以是有利的。
衬底205和键合夹片206A、206B可以包括如铝、镍、银、金或铜的金属，或金属合金，或任何其它合适导电材料。键合夹片可以包括单个结构元件或可以由多于一个的连接的结构元件组成。
如图2C所示，密封剂207可以用于电子器件的实施例200A、200B中以提供保护。根据一些实施例，密封剂207可以仅部分地密封支架205D。特别地，支架205的包括通孔的部分可以伸出密封剂207之外。
图2D示出电子器件200B的侧视图。注意，衬底205的第一部分和第二部分，也就是，图2D所示实施例中的引线205A、205B、205C和支架205D，可以布置在不同平面中。根据另一实施例，衬底205的第一部分和第二部分可以布置在同一平面中。
根据一个实施例，电子器件200A、200B遵循如TO-220或TO-247或TO-264的晶体管外形。
根据一个实施例，电子器件200A、200B包括共源共栅电路，以便创建晶体管外形共源共栅器件。共源共栅电路可以包括半导体元件201、202。根据一些实施例，电子器件可以包括半桥或功率半导体元件以及集成电路或两个集成电路。
注意，电子器件200A、200B可以包括未示出的其它元件。此外，半导体元件201、202不是仅可以如图2A-图2D所示彼此相邻布置(芯片并排)，而是根据一些实施例，也可以布置成一个芯片位于另一个芯片的顶上(芯片在芯片上)。
图3A示出电子器件的电路图300A，该电子器件包括如GaN BJT的基于III-V的双极结型晶体管(BJT)和续流二极管。字母B、C、E分别表示基极、集电极、发射极。根据一个实施例，使用电子器件100来实现这样的电路装置。
图3B示出电子器件的电路图300B，该电子器件包括共源共栅电路装置。该共源共栅电路装置包括第一晶体管301和第二晶体管302。字母D、G、S分别表示漏极、栅极、源极。根据一个实施例，第一晶体管301包括GaN并且配置为HEMT，第二晶体管302可以包括Si或SiC并且可以是功率MOSFET。根据一个实施例，使用电子器件200A、200B来实现这样的电路装置。
图4示出用于制造电子器件的方法400的流程图。方法400包括步骤401、402、403。步骤401包括提供第一半导体元件、第二半导体元件和衬底。每个半导体元件可以包括若干电极。步骤402包括将第一半导体元件和第二半导体元件布置在衬底上。
根据方法400的一个实施例，步骤402进一步包括将半导体元件固定到衬底，使得实现半导体元件上的面向衬底的电极与衬底之间的电连接。
步骤403包括使用键合夹片将第二半导体元件上的电极电连接到衬底。根据方法400的一个实施例，步骤403进一步包括使用键合夹片将第一半导体元件上的电极连接到衬底。
根据一个实施例，方法400可以包括以密封剂密封电子器件使得引线伸出到密封剂之外的进一步步骤。
尽管已经详细描述了本发明及其优势，但应理解的是，这里可以进行各种改变、替代或更改，而不脱离所附权利要求限定的本发明的范围和精神。
而且，本申请的范围并不旨在限于说明书中描述的工艺、机器、制造、组成、装置、方法和步骤的具体实施例。如本领域普通技术人员从本发明的公开将容易认识到的那样，根据本发明可以利用当前存在的或后面将开发的、执行与这里所述对应实施例基本相同功能或实现基本相同效果的工艺、机器、制造、组成、装置、方法或步骤。因此，所附权利要求旨在于将这样的工艺、机器、制造、组成、装置、方法或步骤包括在其范围内。
尽管已经关于一种或多种实现图示和描述本发明，但可以对所图示示例进行更改和/或修改，而不脱离所附权利要求的范围和精神。特别是关于通过上述部件或结构(组件、器件、电路、系统等)执行的各种功能，除非另外指出，否则用于描述这种部件的用语(包括对“装置”的引用)旨在对应于执行所描述部件的特定功能(例如，功能等同)的任何部件或结构，即使该任何部件或结构不是在结构上等同于所公开的执行这里图示的本发明示例实现中的功能的结构。

Claims (20)

1.一种电子器件，包括：
衬底；
第一半导体元件，包括一个或多个第一接触元件，所述第一半导体元件布置在所述衬底上；
第二半导体元件，包括一个或多个第二接触元件，所述第二半导体元件布置在所述衬底上；以及
键合夹片，将所述第一半导体元件和所述第二半导体元件上的所述第一接触元件和所述第二接触元件中的一个或多个电连接到所述衬底。
2.根据权利要求1所述的电子器件，其中所述第一半导体元件包括基于III-V的半导体材料。
3.根据权利要求2所述的电子器件，其中所述基于III-V的半导体材料包括基于GaN的半导体材料。
4.根据权利要求1所述的电子器件，其中所述第二半导体元件包括基于Si的半导体材料。
5.根据权利要求1所述的电子器件，其中所述第二半导体元件包括二极管、MOSFET、IGBT或续流二极管。
6.根据权利要求1所述的电子器件，其中所述衬底包括引线框架或直接键合铜衬底。
7.根据权利要求1所述的电子器件，其中所述衬底包括多个引线元件。
8.根据权利要求1所述的电子器件，其中所述器件包括单列直插式封装(SIP)。
9.一种电子器件，包括：
第一半导体元件，包括第一接触元件；
第二半导体元件，包括第二接触元件；以及
第一衬底元件和与所述第一衬底元件不同的第二衬底元件，
其中所述第一半导体元件和所述第二半导体元件布置在所述第一衬底元件上。
10.根据权利要求9所述的电子器件，其中所述第一半导体元件包括基于III-V的半导体材料。
11.根据权利要求10所述的电子器件，其中所述基于III-V的半导体材料包括GaN。
12.根据权利要求9所述的电子器件，其中所述第一半导体元件包括高电子迁移率晶体管(HEMT)，并且所述第二半导体元件包括功率MOSFET。
13.根据权利要求9所述的电子器件，其中所述第一半导体元件的源极接触和所述第二半导体元件的漏极接触电连接到所述第一衬底元件。
14.根据权利要求13所述的电子器件，其中所述第一半导体元件的栅极接触连接到所述第二半导体元件的源极接触，并且所述第一半导体元件的漏极接触以及所述第二半导体元件的源极接触和所述第二半导体元件的栅极接触连接到所述第二衬底元件。
15.根据权利要求14所述的电子器件，其中所述第二衬底元件包括多个引线。
16.根据权利要求14所述的电子器件，其中所述连接中的一个或多个包括键合夹片，所述键合夹片包括铝、镍、银、金、铜或金属合金。
17.一种电子器件，包括：
第一半导体元件，包括第一接触元件；
第二半导体元件，包括第二接触元件；以及
第一衬底元件和与所述第一衬底元件不同的第二衬底元件，
其中所述第一半导体元件和所述第二半导体元件布置在所述第一衬底元件上，
其中所述电子器件包括共源共栅电路。
18.根据权利要求17所述的器件，其中所述电子器件包括晶体管外形封装。
19.根据权利要求17所述的器件，其中所述半导体器件中的至少一个包括基于III-V的半导体材料。
20.根据权利要求17所述的器件，其中所述半导体器件中的一个是功率芯片。
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