SG54583A1 - Method and apparatus for design verification using emulation and simulation - Google Patents

Method and apparatus for design verification using emulation and simulation

Info

Publication number
SG54583A1
SG54583A1 SG1997003763A SG1997003763A SG54583A1 SG 54583 A1 SG54583 A1 SG 54583A1 SG 1997003763 A SG1997003763 A SG 1997003763A SG 1997003763 A SG1997003763 A SG 1997003763A SG 54583 A1 SG54583 A1 SG 54583A1
Authority
SG
Singapore
Prior art keywords
emulation
simulation
design verification
verification
design
Prior art date
Application number
SG1997003763A
Other languages
English (en)
Inventor
Stephen P Sample
Mikhail Bershtevn
Original Assignee
Quickturn Design Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Quickturn Design Systems Inc filed Critical Quickturn Design Systems Inc
Publication of SG54583A1 publication Critical patent/SG54583A1/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
    • G06F30/331—Design verification, e.g. functional simulation or model checking using simulation with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • Software Systems (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Management, Administration, Business Operations System, And Electronic Commerce (AREA)
  • Tests Of Electronic Circuits (AREA)
SG1997003763A 1996-10-17 1997-10-16 Method and apparatus for design verification using emulation and simulation SG54583A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/733,352 US5841967A (en) 1996-10-17 1996-10-17 Method and apparatus for design verification using emulation and simulation

Publications (1)

Publication Number Publication Date
SG54583A1 true SG54583A1 (en) 1998-11-16

Family

ID=24947260

Family Applications (1)

Application Number Title Priority Date Filing Date
SG1997003763A SG54583A1 (en) 1996-10-17 1997-10-16 Method and apparatus for design verification using emulation and simulation

Country Status (8)

Country Link
US (2) US5841967A (de)
EP (1) EP0838772A3 (de)
JP (2) JP3131177B2 (de)
KR (1) KR100483636B1 (de)
CA (1) CA2218458C (de)
IL (1) IL121955A (de)
SG (1) SG54583A1 (de)
TW (1) TW464828B (de)

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US6058492A (en) 2000-05-02
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US5841967A (en) 1998-11-24
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