SG165262A1 - Substrate etching method and system - Google Patents

Substrate etching method and system

Info

Publication number
SG165262A1
SG165262A1 SG201001912-3A SG2010019123A SG165262A1 SG 165262 A1 SG165262 A1 SG 165262A1 SG 2010019123 A SG2010019123 A SG 2010019123A SG 165262 A1 SG165262 A1 SG 165262A1
Authority
SG
Singapore
Prior art keywords
gas
etching
silicon
substrate
oxide film
Prior art date
Application number
SG201001912-3A
Other languages
English (en)
Inventor
Hajime Ugajin
Original Assignee
Tokyo Electron Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Electron Ltd filed Critical Tokyo Electron Ltd
Publication of SG165262A1 publication Critical patent/SG165262A1/en

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76814Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041Cleaning
    • H01L21/02057Cleaning during device manufacture
    • H01L21/0206Cleaning during device manufacture during, before or after processing of insulating layers
    • H01L21/02063Cleaning during device manufacture during, before or after processing of insulating layers the processing being the formation of vias or contact holes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065Plasma etching; Reactive-ion etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005Apparatus not specifically provided for elsewhere
    • H01L21/67011Apparatus for manufacture or treatment
    • H01L21/67017Apparatus for fluid treatment
    • H01L21/67063Apparatus for fluid treatment for etching
    • H01L21/67069Apparatus for fluid treatment for etching for drying etching

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
SG201001912-3A 2009-03-19 2010-03-19 Substrate etching method and system SG165262A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2009067868 2009-03-19
JP2010045893A JP4968861B2 (ja) 2009-03-19 2010-03-02 基板のエッチング方法及びシステム

Publications (1)

Publication Number Publication Date
SG165262A1 true SG165262A1 (en) 2010-10-28

Family

ID=42738037

Family Applications (1)

Application Number Title Priority Date Filing Date
SG201001912-3A SG165262A1 (en) 2009-03-19 2010-03-19 Substrate etching method and system

Country Status (6)

Country Link
US (1) US8440568B2 (ko)
JP (1) JP4968861B2 (ko)
KR (1) KR101165970B1 (ko)
CN (1) CN101840884B (ko)
SG (1) SG165262A1 (ko)
TW (1) TWI458010B (ko)

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JP6643045B2 (ja) 2015-11-05 2020-02-12 東京エレクトロン株式会社 基板処理方法及び基板処理装置
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JP6770825B2 (ja) * 2016-04-27 2020-10-21 東京エレクトロン株式会社 基板処理方法及び基板処理装置
JP6656082B2 (ja) * 2016-05-19 2020-03-04 東京エレクトロン株式会社 酸化膜除去方法および除去装置、ならびにコンタクト形成方法およびコンタクト形成システム
JP2017222928A (ja) * 2016-05-31 2017-12-21 東京エレクトロン株式会社 表面処理による選択的堆積
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JP6956551B2 (ja) * 2017-03-08 2021-11-02 東京エレクトロン株式会社 酸化膜除去方法および除去装置、ならびにコンタクト形成方法およびコンタクト形成システム
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JP6869765B2 (ja) * 2017-03-23 2021-05-12 株式会社日立ハイテク プラズマ処理装置及びプラズマ処理方法
JP6399141B1 (ja) * 2017-04-17 2018-10-03 株式会社Sumco シリコンウェーハの金属汚染分析方法およびシリコンウェーハの製造方法
DE102017219312A1 (de) * 2017-10-27 2019-05-02 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. 2-stufiger Trockenätzprozess zur Texturierung kristalliner Siliziumscheiben
JP6981267B2 (ja) * 2018-01-17 2021-12-15 東京エレクトロン株式会社 エッチング方法及びエッチング装置
CN108847391B (zh) * 2018-06-01 2021-06-08 北京北方华创微电子装备有限公司 一种非等离子干法刻蚀方法
JP7362258B2 (ja) * 2019-02-08 2023-10-17 東京エレクトロン株式会社 基板処理方法及び成膜システム
KR102278081B1 (ko) * 2019-06-27 2021-07-19 세메스 주식회사 기판 처리 장치 및 방법
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TW202310038A (zh) * 2021-05-31 2023-03-01 日商東京威力科創股份有限公司 基板處理方法及基板處理裝置
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Also Published As

Publication number Publication date
CN101840884A (zh) 2010-09-22
US20100240218A1 (en) 2010-09-23
JP4968861B2 (ja) 2012-07-04
US8440568B2 (en) 2013-05-14
KR101165970B1 (ko) 2012-07-18
KR20100105398A (ko) 2010-09-29
TW201108323A (en) 2011-03-01
TWI458010B (zh) 2014-10-21
CN101840884B (zh) 2013-03-27
JP2010245512A (ja) 2010-10-28

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