FI20115321A0 - Menetelmä yhden tai useamman monikiteisen piikerroksen kerrrostamiseksi substraatille - Google Patents

Menetelmä yhden tai useamman monikiteisen piikerroksen kerrrostamiseksi substraatille

Info

Publication number
FI20115321A0
FI20115321A0 FI20115321A FI20115321A FI20115321A0 FI 20115321 A0 FI20115321 A0 FI 20115321A0 FI 20115321 A FI20115321 A FI 20115321A FI 20115321 A FI20115321 A FI 20115321A FI 20115321 A0 FI20115321 A0 FI 20115321A0
Authority
FI
Finland
Prior art keywords
depositing
substrate
polycrystalline silicon
silicon layers
reactor
Prior art date
Application number
FI20115321A
Other languages
English (en)
Swedish (sv)
Other versions
FI20115321L (fi
FI124354B (fi
Inventor
Veli Matti Airaksinen
Jari Maekinen
Original Assignee
Okmetic Oyj
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Okmetic Oyj filed Critical Okmetic Oyj
Publication of FI20115321A0 publication Critical patent/FI20115321A0/fi
Priority to FI20115321A priority Critical patent/FI124354B/fi
Priority to EP12768580.8A priority patent/EP2694699B1/en
Priority to PCT/FI2012/050325 priority patent/WO2012136888A1/en
Priority to CN201280024707.5A priority patent/CN103547704B/zh
Priority to CA2832084A priority patent/CA2832084C/en
Priority to US14/009,838 priority patent/US9728452B2/en
Priority to SG2013074000A priority patent/SG194066A1/en
Priority to JP2014503183A priority patent/JP6117769B2/ja
Publication of FI20115321L publication Critical patent/FI20115321L/fi
Application granted granted Critical
Publication of FI124354B publication Critical patent/FI124354B/fi
Priority to JP2017004355A priority patent/JP6374540B2/ja

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76882—Reflowing or applying of pressure to better fill the contact hole
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/04—Coating on selected surface areas, e.g. using masks
    • C23C16/045—Coating cavities or hollow spaces, e.g. interior of tubes; Infiltration of porous substrates
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/24—Deposition of silicon only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Mechanical Engineering (AREA)
  • Organic Chemistry (AREA)
  • Metallurgy (AREA)
  • Materials Engineering (AREA)
  • Inorganic Chemistry (AREA)
  • Chemical Vapour Deposition (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Element Separation (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
FI20115321A 2011-04-04 2011-04-04 Menetelmä yhden tai useamman polykiteisen piikerroksen pinnoittamiseksi substraatille FI124354B (fi)

Priority Applications (9)

Application Number Priority Date Filing Date Title
FI20115321A FI124354B (fi) 2011-04-04 2011-04-04 Menetelmä yhden tai useamman polykiteisen piikerroksen pinnoittamiseksi substraatille
CA2832084A CA2832084C (en) 2011-04-04 2012-03-30 Method for depositing one or more polycrystalline silicon layers on substrate
PCT/FI2012/050325 WO2012136888A1 (en) 2011-04-04 2012-03-30 Method for depositing one or more polycrystalline silicon layers on substrate
CN201280024707.5A CN103547704B (zh) 2011-04-04 2012-03-30 用于在衬底上沉积一个或者多个多晶硅层的方法
EP12768580.8A EP2694699B1 (en) 2011-04-04 2012-03-30 Method for depositing one or more polycrystalline silicon layers on substrate
US14/009,838 US9728452B2 (en) 2011-04-04 2012-03-30 Method for depositing one or more polycrystalline silicon layers on substrate
SG2013074000A SG194066A1 (en) 2011-04-04 2012-03-30 Method for depositing one or more polycrystalline silicon layers on substrate
JP2014503183A JP6117769B2 (ja) 2011-04-04 2012-03-30 スルーウェハービアを基材に形成するための方法
JP2017004355A JP6374540B2 (ja) 2011-04-04 2017-01-13 １層以上の多結晶シリコン層を基材に堆積する方法

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FI20115321 2011-04-04
FI20115321A FI124354B (fi) 2011-04-04 2011-04-04 Menetelmä yhden tai useamman polykiteisen piikerroksen pinnoittamiseksi substraatille

Publications (3)

Publication Number Publication Date
FI20115321A0 true FI20115321A0 (fi) 2011-04-04
FI20115321L FI20115321L (fi) 2012-10-05
FI124354B FI124354B (fi) 2014-07-15

Family

ID=43919644

Family Applications (1)

Application Number Title Priority Date Filing Date
FI20115321A FI124354B (fi) 2011-04-04 2011-04-04 Menetelmä yhden tai useamman polykiteisen piikerroksen pinnoittamiseksi substraatille

Country Status (8)

Country Link
US (1) US9728452B2 (fi)
EP (1) EP2694699B1 (fi)
JP (2) JP6117769B2 (fi)
CN (1) CN103547704B (fi)
CA (1) CA2832084C (fi)
FI (1) FI124354B (fi)
SG (1) SG194066A1 (fi)
WO (1) WO2012136888A1 (fi)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
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KR101706747B1 (ko) * 2015-05-08 2017-02-15 주식회사 유진테크 비정질 박막의 형성방법
CN106894080B (zh) * 2015-12-18 2019-03-29 有研半导体材料有限公司 一种大直径硅基多晶硅膜的制备方法
FR3076292B1 (fr) * 2017-12-28 2020-01-03 Commissariat A L'energie Atomique Et Aux Energies Alternatives Procede de transfert d'une couche utile sur un substrat support
CN111785628A (zh) * 2020-06-28 2020-10-16 上海华虹宏力半导体制造有限公司 Igbt器件的制造方法
CN111883428A (zh) * 2020-07-16 2020-11-03 上海华虹宏力半导体制造有限公司 发射区多晶硅的形成方法及器件
CN112490114B (zh) * 2020-11-27 2023-11-14 上海华虹宏力半导体制造有限公司 一种调整多晶硅沉积速率的方法及锗硅hbt器件的制造方法
CN115613007A (zh) * 2022-10-13 2023-01-17 上海中欣晶圆半导体科技有限公司 一种改善翘曲的成膜方法

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Also Published As

Publication number Publication date
CN103547704B (zh) 2016-03-30
FI20115321L (fi) 2012-10-05
EP2694699B1 (en) 2017-05-03
SG194066A1 (en) 2013-11-29
CN103547704A (zh) 2014-01-29
CA2832084A1 (en) 2012-10-11
JP2017112382A (ja) 2017-06-22
FI124354B (fi) 2014-07-15
JP2014514760A (ja) 2014-06-19
EP2694699A1 (en) 2014-02-12
US9728452B2 (en) 2017-08-08
EP2694699A4 (en) 2014-09-17
WO2012136888A1 (en) 2012-10-11
US20140061867A1 (en) 2014-03-06
CA2832084C (en) 2020-09-08
JP6117769B2 (ja) 2017-04-19
JP6374540B2 (ja) 2018-08-15

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