JP6056136B2 - ドライエッチング方法 - Google Patents
ドライエッチング方法 Download PDFInfo
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- JP6056136B2 JP6056136B2 JP2011267110A JP2011267110A JP6056136B2 JP 6056136 B2 JP6056136 B2 JP 6056136B2 JP 2011267110 A JP2011267110 A JP 2011267110A JP 2011267110 A JP2011267110 A JP 2011267110A JP 6056136 B2 JP6056136 B2 JP 6056136B2
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- 238000000034 method Methods 0.000 title claims description 36
- 238000001312 dry etching Methods 0.000 title claims description 17
- 238000005530 etching Methods 0.000 claims description 124
- 239000000758 substrate Substances 0.000 claims description 40
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 26
- 229910052710 silicon Inorganic materials 0.000 claims description 26
- 239000010703 silicon Substances 0.000 claims description 26
- 238000006243 chemical reaction Methods 0.000 claims description 22
- 239000004065 semiconductor Substances 0.000 claims description 12
- 239000012895 dilution Substances 0.000 description 11
- 238000010790 dilution Methods 0.000 description 11
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 11
- 229920005591 polysilicon Polymers 0.000 description 11
- 230000000052 comparative effect Effects 0.000 description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 239000003085 diluting agent Substances 0.000 description 6
- 125000001153 fluoro group Chemical group F* 0.000 description 6
- 229910052814 silicon oxide Inorganic materials 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- 230000010354 integration Effects 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 230000000149 penetrating effect Effects 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
- H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Plasma & Fusion (AREA)
- Drying Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
本実施例におけるエッチング条件と、その結果を表1に示す。
本比較例におけるエッチング条件と、その結果を表2に示す。
21・・・インターハロゲン供給系
22・・・F2供給系
23・・・希釈ガス供給系
31、32、33・・・バルブ
41、42・・・ガス配管
5・・・ステージ
6・・・ステージ温度調整器
7・・・試料
8・・・真空ポンプ
9・・・酸化シリコン膜
10・・・ポリシリコン膜
11・・・シリコン基板
12・・・窒化ケイ素膜
13・・・孔
Claims (4)
- 基板上に形成されている、シリコン層と絶縁膜が複数積層している層状構造を有する積層膜に、基板面に垂直方向に形成されている孔又は溝を有する三次元構造の半導体素子を反応チャンバー内に設置し、エッチングガスを反応チャンバー内に導入し、前記孔又は溝に接触させ、前記孔又は溝の内側面に現れている複数のシリコン層を前記基板面に対して平行方向に深さ5nm以上90nm以下エッチングするドライエッチング方法において、
エッチングガスとして、ClF3、BrF5、BrF3、IF7、IF5から選ばれる少なくとも1種類のガスとF2とを含有するガスを用いることを特徴とするドライエッチング方法。 - エッチングガスに含有するClF3、BrF5、BrF3、IF7、IF5、又はF2の分圧は、それぞれ1Pa以上2000Pa以下であることを特徴とする請求項1に記載のドライエッチング方法。
- 前記エッチングガスに、更に、N2、He、Arから選ばれる少なくとも1種類のガスを含有することを特徴とする請求項1又は2のいずれか1項に記載のドライエッチング方法。
- −30℃以上100℃以下の基板温度で、前記エッチングガスをシリコン層に接触させることを特徴とする請求項1〜3のいずれか1項に記載のドライエッチング方法。
Priority Applications (7)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2011267110A JP6056136B2 (ja) | 2011-09-07 | 2011-12-06 | ドライエッチング方法 |
PCT/JP2012/070154 WO2013035476A1 (ja) | 2011-09-07 | 2012-08-08 | ドライエッチング方法 |
CN201280043758.2A CN103782369B (zh) | 2011-09-07 | 2012-08-08 | 干蚀刻方法 |
KR1020147006924A KR101703777B1 (ko) | 2011-09-07 | 2012-08-08 | 드라이 에칭 방법 |
EP12830450.8A EP2755229B1 (en) | 2011-09-07 | 2012-08-08 | Dry etching method |
US14/238,639 US9165776B2 (en) | 2011-09-07 | 2012-08-08 | Dry etching method |
TW101130899A TWI502642B (zh) | 2011-09-07 | 2012-08-24 | Dry etching method |
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2011195359 | 2011-09-07 | ||
JP2011195359 | 2011-09-07 | ||
JP2011267110A JP6056136B2 (ja) | 2011-09-07 | 2011-12-06 | ドライエッチング方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2013070012A JP2013070012A (ja) | 2013-04-18 |
JP6056136B2 true JP6056136B2 (ja) | 2017-01-11 |
Family
ID=47831928
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2011267110A Active JP6056136B2 (ja) | 2011-09-07 | 2011-12-06 | ドライエッチング方法 |
Country Status (7)
Country | Link |
---|---|
US (1) | US9165776B2 (ja) |
EP (1) | EP2755229B1 (ja) |
JP (1) | JP6056136B2 (ja) |
KR (1) | KR101703777B1 (ja) |
CN (1) | CN103782369B (ja) |
TW (1) | TWI502642B (ja) |
WO (1) | WO2013035476A1 (ja) |
Families Citing this family (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2015011829A1 (ja) * | 2013-07-26 | 2015-01-29 | 株式会社日立国際電気 | 基板処理装置及び半導体装置の製造方法 |
WO2015016149A1 (ja) * | 2013-07-29 | 2015-02-05 | 株式会社日立国際電気 | 基板処理装置、半導体装置の製造方法および記録媒体 |
JP6454492B2 (ja) * | 2014-08-08 | 2019-01-16 | 東京エレクトロン株式会社 | 多層膜をエッチングする方法 |
WO2016056300A1 (ja) * | 2014-10-10 | 2016-04-14 | 関東電化工業株式会社 | ケイ素化合物用エッチングガス組成物及びエッチング方法 |
US9728422B2 (en) | 2015-01-23 | 2017-08-08 | Central Glass Company, Limited | Dry etching method |
JP6544215B2 (ja) | 2015-01-23 | 2019-07-17 | セントラル硝子株式会社 | ドライエッチング方法 |
FR3051973B1 (fr) | 2016-05-24 | 2018-10-19 | X-Fab France | Procede de formation de transistors pdsoi et fdsoi sur un meme substrat |
JP6823533B2 (ja) * | 2017-04-24 | 2021-02-03 | 東京エレクトロン株式会社 | チタンシリサイド領域を形成する方法 |
JP6971823B2 (ja) * | 2017-12-13 | 2021-11-24 | 東京エレクトロン株式会社 | シリコン含有膜のエッチング方法、コンピュータ記憶媒体、及びシリコン含有膜のエッチング装置 |
US11594429B2 (en) * | 2018-03-16 | 2023-02-28 | Lam Research Corporation | Plasma etching chemistries of high aspect ratio features in dielectrics |
US11447697B2 (en) * | 2018-03-29 | 2022-09-20 | Central Glass Company, Limited | Substrate processing gas, storage container, and substrate processing method |
JP7072440B2 (ja) * | 2018-05-16 | 2022-05-20 | 東京エレクトロン株式会社 | シリコン含有膜のエッチング方法、コンピュータ記憶媒体、及びシリコン含有膜のエッチング装置 |
JP7174180B2 (ja) * | 2018-05-16 | 2022-11-17 | 東京エレクトロン株式会社 | シリコン含有膜のエッチング方法、コンピュータ記憶媒体、及びシリコン含有膜のエッチング装置 |
JP2020068221A (ja) * | 2018-10-22 | 2020-04-30 | 東京エレクトロン株式会社 | エッチング方法及びプラズマ処理装置 |
CN115376910B (zh) * | 2022-09-06 | 2023-06-13 | 兰州大学 | 一种制备平行斜刻凹槽图形化硅衬底的方法 |
Family Cites Families (13)
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US4310380A (en) * | 1980-04-07 | 1982-01-12 | Bell Telephone Laboratories, Incorporated | Plasma etching of silicon |
US5624582A (en) * | 1993-01-21 | 1997-04-29 | Vlsi Technology, Inc. | Optimization of dry etching through the control of helium backside pressure |
TW498440B (en) * | 1998-03-30 | 2002-08-11 | Hitachi Ltd | Manufacture method of semiconductor device |
US7041224B2 (en) * | 1999-10-26 | 2006-05-09 | Reflectivity, Inc. | Method for vapor phase etching of silicon |
AU2002303842A1 (en) * | 2001-05-22 | 2002-12-03 | Reflectivity, Inc. | A method for making a micromechanical device by removing a sacrificial layer with multiple sequential etchants |
JP4446202B2 (ja) | 2006-09-22 | 2010-04-07 | エルピーダメモリ株式会社 | 半導体装置及び半導体装置の製造方法 |
US8278725B2 (en) | 2006-11-10 | 2012-10-02 | Agency For Science, Technology And Research | Micromechanical structure and a method of fabricating a micromechanical structure |
JP2010010596A (ja) * | 2008-06-30 | 2010-01-14 | Toshiba Corp | 不揮発性半導体記憶装置及びその製造方法 |
JP2010177652A (ja) | 2009-02-02 | 2010-08-12 | Toshiba Corp | 半導体装置の製造方法 |
JP2010225694A (ja) * | 2009-03-19 | 2010-10-07 | Toshiba Corp | 半導体装置及びその製造方法 |
JP4968861B2 (ja) | 2009-03-19 | 2012-07-04 | 東京エレクトロン株式会社 | 基板のエッチング方法及びシステム |
JP2011060958A (ja) * | 2009-09-09 | 2011-03-24 | Toshiba Corp | 半導体装置及びその製造方法 |
JP6080166B2 (ja) * | 2011-08-25 | 2017-02-15 | 株式会社Screenホールディングス | パターン形成方法 |
-
2011
- 2011-12-06 JP JP2011267110A patent/JP6056136B2/ja active Active
-
2012
- 2012-08-08 KR KR1020147006924A patent/KR101703777B1/ko active IP Right Grant
- 2012-08-08 EP EP12830450.8A patent/EP2755229B1/en not_active Not-in-force
- 2012-08-08 US US14/238,639 patent/US9165776B2/en active Active
- 2012-08-08 CN CN201280043758.2A patent/CN103782369B/zh active Active
- 2012-08-08 WO PCT/JP2012/070154 patent/WO2013035476A1/ja active Application Filing
- 2012-08-24 TW TW101130899A patent/TWI502642B/zh active
Also Published As
Publication number | Publication date |
---|---|
JP2013070012A (ja) | 2013-04-18 |
TW201314770A (zh) | 2013-04-01 |
CN103782369B (zh) | 2017-02-15 |
WO2013035476A1 (ja) | 2013-03-14 |
KR20140053333A (ko) | 2014-05-07 |
TWI502642B (zh) | 2015-10-01 |
CN103782369A (zh) | 2014-05-07 |
EP2755229A1 (en) | 2014-07-16 |
US9165776B2 (en) | 2015-10-20 |
EP2755229B1 (en) | 2018-04-25 |
KR101703777B1 (ko) | 2017-02-07 |
EP2755229A4 (en) | 2015-01-07 |
US20140206196A1 (en) | 2014-07-24 |
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